projects / thirdparty / kernel / stable.git / blame
| Commit | Line | Data |
|---|---|---|
| f51746ad GU |
1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* | |
| 3 | * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC | |
| 4 | * | |
| 5 | * Copyright (C) 2016-2017 Renesas Electronics Corp. | |
| 6 | */ | |
| 7 | ||
| 8 | #include <dt-bindings/clock/r8a77961-cpg-mssr.h> | |
| 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 10 | #include <dt-bindings/power/r8a77961-sysc.h> | |
| 11 | ||
| f51746ad GU |
12 | / { |
| 13 | compatible = "renesas,r8a77961"; | |
| 14 | #address-cells = <2>; | |
| 15 | #size-cells = <2>; | |
| 16 | ||
| 17 | /* | |
| 18 | * The external audio clocks are configured as 0 Hz fixed frequency | |
| 19 | * clocks by default. | |
| 20 | * Boards that provide audio clocks should override them. | |
| 21 | */ | |
| 22 | audio_clk_a: audio_clk_a { | |
| 23 | compatible = "fixed-clock"; | |
| 24 | #clock-cells = <0>; | |
| 25 | clock-frequency = <0>; | |
| 26 | }; | |
| 27 | ||
| 28 | audio_clk_b: audio_clk_b { | |
| 29 | compatible = "fixed-clock"; | |
| 30 | #clock-cells = <0>; | |
| 31 | clock-frequency = <0>; | |
| 32 | }; | |
| 33 | ||
| 34 | audio_clk_c: audio_clk_c { | |
| 35 | compatible = "fixed-clock"; | |
| 36 | #clock-cells = <0>; | |
| 37 | clock-frequency = <0>; | |
| 38 | }; | |
| 39 | ||
| 40 | /* External CAN clock - to be overridden by boards that provide it */ | |
| 41 | can_clk: can { | |
| 42 | compatible = "fixed-clock"; | |
| 43 | #clock-cells = <0>; | |
| 44 | clock-frequency = <0>; | |
| 45 | }; | |
| 46 | ||
| 7744b393 | 47 | cluster0_opp: opp-table-0 { |
| f51746ad GU |
48 | compatible = "operating-points-v2"; |
| 49 | opp-shared; | |
| 50 | ||
| 51 | opp-500000000 { | |
| 52 | opp-hz = /bits/ 64 <500000000>; | |
| 659b3820 | 53 | opp-microvolt = <830000>; |
| f51746ad GU |
54 | clock-latency-ns = <300000>; |
| 55 | }; | |
| 56 | opp-1000000000 { | |
| 57 | opp-hz = /bits/ 64 <1000000000>; | |
| 659b3820 | 58 | opp-microvolt = <830000>; |
| f51746ad GU |
59 | clock-latency-ns = <300000>; |
| 60 | }; | |
| 61 | opp-1500000000 { | |
| 62 | opp-hz = /bits/ 64 <1500000000>; | |
| 659b3820 | 63 | opp-microvolt = <830000>; |
| f51746ad | 64 | clock-latency-ns = <300000>; |
| 44b615ac | 65 | opp-suspend; |
| f51746ad GU |
66 | }; |
| 67 | opp-1600000000 { | |
| 68 | opp-hz = /bits/ 64 <1600000000>; | |
| 69 | opp-microvolt = <900000>; | |
| 70 | clock-latency-ns = <300000>; | |
| f51746ad GU |
71 | }; |
| 72 | opp-1700000000 { | |
| 73 | opp-hz = /bits/ 64 <1700000000>; | |
| 74 | opp-microvolt = <900000>; | |
| 75 | clock-latency-ns = <300000>; | |
| f51746ad GU |
76 | }; |
| 77 | opp-1800000000 { | |
| 78 | opp-hz = /bits/ 64 <1800000000>; | |
| 79 | opp-microvolt = <960000>; | |
| 80 | clock-latency-ns = <300000>; | |
| 81 | turbo-mode; | |
| 82 | }; | |
| 83 | }; | |
| 84 | ||
| 7744b393 | 85 | cluster1_opp: opp-table-1 { |
| f51746ad GU |
86 | compatible = "operating-points-v2"; |
| 87 | opp-shared; | |
| 88 | ||
| 89 | opp-800000000 { | |
| 90 | opp-hz = /bits/ 64 <800000000>; | |
| 91 | opp-microvolt = <820000>; | |
| 92 | clock-latency-ns = <300000>; | |
| 93 | }; | |
| 94 | opp-1000000000 { | |
| 95 | opp-hz = /bits/ 64 <1000000000>; | |
| 96 | opp-microvolt = <820000>; | |
| 97 | clock-latency-ns = <300000>; | |
| 98 | }; | |
| 99 | opp-1200000000 { | |
| 100 | opp-hz = /bits/ 64 <1200000000>; | |
| 101 | opp-microvolt = <820000>; | |
| 102 | clock-latency-ns = <300000>; | |
| 103 | }; | |
| 104 | opp-1300000000 { | |
| 105 | opp-hz = /bits/ 64 <1300000000>; | |
| 106 | opp-microvolt = <820000>; | |
| 107 | clock-latency-ns = <300000>; | |
| 108 | turbo-mode; | |
| 109 | }; | |
| 110 | }; | |
| 111 | ||
| 112 | cpus { | |
| 113 | #address-cells = <1>; | |
| 114 | #size-cells = <0>; | |
| 115 | ||
| 116 | cpu-map { | |
| 117 | cluster0 { | |
| 118 | core0 { | |
| 119 | cpu = <&a57_0>; | |
| 120 | }; | |
| 121 | core1 { | |
| 122 | cpu = <&a57_1>; | |
| 123 | }; | |
| 124 | }; | |
| 125 | ||
| 126 | cluster1 { | |
| 127 | core0 { | |
| 128 | cpu = <&a53_0>; | |
| 129 | }; | |
| 130 | core1 { | |
| 131 | cpu = <&a53_1>; | |
| 132 | }; | |
| 133 | core2 { | |
| 134 | cpu = <&a53_2>; | |
| 135 | }; | |
| 136 | core3 { | |
| 137 | cpu = <&a53_3>; | |
| 138 | }; | |
| 139 | }; | |
| 140 | }; | |
| 141 | ||
| 142 | a57_0: cpu@0 { | |
| 143 | compatible = "arm,cortex-a57"; | |
| 144 | reg = <0x0>; | |
| 145 | device_type = "cpu"; | |
| 146 | power-domains = <&sysc R8A77961_PD_CA57_CPU0>; | |
| 147 | next-level-cache = <&L2_CA57>; | |
| 148 | enable-method = "psci"; | |
| 149 | cpu-idle-states = <&CPU_SLEEP_0>; | |
| 150 | dynamic-power-coefficient = <854>; | |
| 151 | clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; | |
| 152 | operating-points-v2 = <&cluster0_opp>; | |
| 153 | capacity-dmips-mhz = <1024>; | |
| 154 | #cooling-cells = <2>; | |
| 155 | }; | |
| 156 | ||
| 157 | a57_1: cpu@1 { | |
| 158 | compatible = "arm,cortex-a57"; | |
| 159 | reg = <0x1>; | |
| 160 | device_type = "cpu"; | |
| 161 | power-domains = <&sysc R8A77961_PD_CA57_CPU1>; | |
| 162 | next-level-cache = <&L2_CA57>; | |
| 163 | enable-method = "psci"; | |
| 164 | cpu-idle-states = <&CPU_SLEEP_0>; | |
| 165 | clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; | |
| 166 | operating-points-v2 = <&cluster0_opp>; | |
| 167 | capacity-dmips-mhz = <1024>; | |
| 168 | #cooling-cells = <2>; | |
| 169 | }; | |
| 170 | ||
| 171 | a53_0: cpu@100 { | |
| 172 | compatible = "arm,cortex-a53"; | |
| 173 | reg = <0x100>; | |
| 174 | device_type = "cpu"; | |
| 175 | power-domains = <&sysc R8A77961_PD_CA53_CPU0>; | |
| 176 | next-level-cache = <&L2_CA53>; | |
| 177 | enable-method = "psci"; | |
| 178 | cpu-idle-states = <&CPU_SLEEP_1>; | |
| 179 | #cooling-cells = <2>; | |
| 180 | dynamic-power-coefficient = <277>; | |
| 181 | clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; | |
| 182 | operating-points-v2 = <&cluster1_opp>; | |
| 183 | capacity-dmips-mhz = <535>; | |
| 184 | }; | |
| 185 | ||
| 186 | a53_1: cpu@101 { | |
| 187 | compatible = "arm,cortex-a53"; | |
| 188 | reg = <0x101>; | |
| 189 | device_type = "cpu"; | |
| 190 | power-domains = <&sysc R8A77961_PD_CA53_CPU1>; | |
| 191 | next-level-cache = <&L2_CA53>; | |
| 192 | enable-method = "psci"; | |
| 193 | cpu-idle-states = <&CPU_SLEEP_1>; | |
| 194 | clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; | |
| 195 | operating-points-v2 = <&cluster1_opp>; | |
| 196 | capacity-dmips-mhz = <535>; | |
| 197 | }; | |
| 198 | ||
| 199 | a53_2: cpu@102 { | |
| 200 | compatible = "arm,cortex-a53"; | |
| 201 | reg = <0x102>; | |
| 202 | device_type = "cpu"; | |
| 203 | power-domains = <&sysc R8A77961_PD_CA53_CPU2>; | |
| 204 | next-level-cache = <&L2_CA53>; | |
| 205 | enable-method = "psci"; | |
| 206 | cpu-idle-states = <&CPU_SLEEP_1>; | |
| 207 | clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; | |
| 208 | operating-points-v2 = <&cluster1_opp>; | |
| 209 | capacity-dmips-mhz = <535>; | |
| 210 | }; | |
| 211 | ||
| 212 | a53_3: cpu@103 { | |
| 213 | compatible = "arm,cortex-a53"; | |
| 214 | reg = <0x103>; | |
| 215 | device_type = "cpu"; | |
| 216 | power-domains = <&sysc R8A77961_PD_CA53_CPU3>; | |
| 217 | next-level-cache = <&L2_CA53>; | |
| 218 | enable-method = "psci"; | |
| 219 | cpu-idle-states = <&CPU_SLEEP_1>; | |
| 220 | clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; | |
| 221 | operating-points-v2 = <&cluster1_opp>; | |
| 222 | capacity-dmips-mhz = <535>; | |
| 223 | }; | |
| 224 | ||
| 225 | L2_CA57: cache-controller-0 { | |
| 226 | compatible = "cache"; | |
| 227 | power-domains = <&sysc R8A77961_PD_CA57_SCU>; | |
| 228 | cache-unified; | |
| 229 | cache-level = <2>; | |
| 230 | }; | |
| 231 | ||
| 232 | L2_CA53: cache-controller-1 { | |
| 233 | compatible = "cache"; | |
| 234 | power-domains = <&sysc R8A77961_PD_CA53_SCU>; | |
| 235 | cache-unified; | |
| 236 | cache-level = <2>; | |
| 237 | }; | |
| 238 | ||
| 239 | idle-states { | |
| 240 | entry-method = "psci"; | |
| 241 | ||
| 242 | CPU_SLEEP_0: cpu-sleep-0 { | |
| 243 | compatible = "arm,idle-state"; | |
| 244 | arm,psci-suspend-param = <0x0010000>; | |
| 245 | local-timer-stop; | |
| 246 | entry-latency-us = <400>; | |
| 247 | exit-latency-us = <500>; | |
| 248 | min-residency-us = <4000>; | |
| 249 | }; | |
| 250 | ||
| 251 | CPU_SLEEP_1: cpu-sleep-1 { | |
| 252 | compatible = "arm,idle-state"; | |
| 253 | arm,psci-suspend-param = <0x0010000>; | |
| 254 | local-timer-stop; | |
| 255 | entry-latency-us = <700>; | |
| 256 | exit-latency-us = <700>; | |
| 257 | min-residency-us = <5000>; | |
| 258 | }; | |
| 259 | }; | |
| 260 | }; | |
| 261 | ||
| 262 | extal_clk: extal { | |
| 263 | compatible = "fixed-clock"; | |
| 264 | #clock-cells = <0>; | |
| 265 | /* This value must be overridden by the board */ | |
| 266 | clock-frequency = <0>; | |
| 267 | }; | |
| 268 | ||
| 269 | extalr_clk: extalr { | |
| 270 | compatible = "fixed-clock"; | |
| 271 | #clock-cells = <0>; | |
| 272 | /* This value must be overridden by the board */ | |
| 273 | clock-frequency = <0>; | |
| 274 | }; | |
| 275 | ||
| 276 | /* External PCIe clock - can be overridden by the board */ | |
| 277 | pcie_bus_clk: pcie_bus { | |
| 278 | compatible = "fixed-clock"; | |
| 279 | #clock-cells = <0>; | |
| 280 | clock-frequency = <0>; | |
| 281 | }; | |
| 282 | ||
| 283 | pmu_a53 { | |
| 284 | compatible = "arm,cortex-a53-pmu"; | |
| 285 | interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, | |
| 286 | <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, | |
| 287 | <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, | |
| 288 | <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
| 289 | interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; | |
| 290 | }; | |
| 291 | ||
| 292 | pmu_a57 { | |
| 293 | compatible = "arm,cortex-a57-pmu"; | |
| 294 | interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, | |
| 295 | <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
| 296 | interrupt-affinity = <&a57_0>, <&a57_1>; | |
| 297 | }; | |
| 298 | ||
| 299 | psci { | |
| 300 | compatible = "arm,psci-1.0", "arm,psci-0.2"; | |
| 301 | method = "smc"; | |
| 302 | }; | |
| 303 | ||
| 304 | /* External SCIF clock - to be overridden by boards that provide it */ | |
| 305 | scif_clk: scif { | |
| 306 | compatible = "fixed-clock"; | |
| 307 | #clock-cells = <0>; | |
| 308 | clock-frequency = <0>; | |
| 309 | }; | |
| 310 | ||
| 311 | soc { | |
| 312 | compatible = "simple-bus"; | |
| 313 | interrupt-parent = <&gic>; | |
| 314 | #address-cells = <2>; | |
| 315 | #size-cells = <2>; | |
| 316 | ranges; | |
| 317 | ||
| 318 | rwdt: watchdog@e6020000 { | |
| 36065b07 GU |
319 | compatible = "renesas,r8a77961-wdt", |
| 320 | "renesas,rcar-gen3-wdt"; | |
| f51746ad | 321 | reg = <0 0xe6020000 0 0x0c>; |
| 2bc0aa18 | 322 | interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| 36065b07 GU |
323 | clocks = <&cpg CPG_MOD 402>; |
| 324 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 325 | resets = <&cpg 402>; | |
| 326 | status = "disabled"; | |
| f51746ad GU |
327 | }; |
| 328 | ||
| c6ef2b34 GU |
329 | gpio0: gpio@e6050000 { |
| 330 | compatible = "renesas,gpio-r8a77961", | |
| 331 | "renesas,rcar-gen3-gpio"; | |
| 332 | reg = <0 0xe6050000 0 0x50>; | |
| 333 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
| 334 | #gpio-cells = <2>; | |
| 335 | gpio-controller; | |
| 336 | gpio-ranges = <&pfc 0 0 16>; | |
| 337 | #interrupt-cells = <2>; | |
| 338 | interrupt-controller; | |
| 339 | clocks = <&cpg CPG_MOD 912>; | |
| 340 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 341 | resets = <&cpg 912>; | |
| 342 | }; | |
| 343 | ||
| 344 | gpio1: gpio@e6051000 { | |
| 345 | compatible = "renesas,gpio-r8a77961", | |
| 346 | "renesas,rcar-gen3-gpio"; | |
| 347 | reg = <0 0xe6051000 0 0x50>; | |
| 348 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
| 349 | #gpio-cells = <2>; | |
| 350 | gpio-controller; | |
| 351 | gpio-ranges = <&pfc 0 32 29>; | |
| 352 | #interrupt-cells = <2>; | |
| 353 | interrupt-controller; | |
| 354 | clocks = <&cpg CPG_MOD 911>; | |
| 355 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 356 | resets = <&cpg 911>; | |
| 357 | }; | |
| 358 | ||
| f51746ad | 359 | gpio2: gpio@e6052000 { |
| c6ef2b34 GU |
360 | compatible = "renesas,gpio-r8a77961", |
| 361 | "renesas,rcar-gen3-gpio"; | |
| f51746ad | 362 | reg = <0 0xe6052000 0 0x50>; |
| c6ef2b34 | 363 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| f51746ad GU |
364 | #gpio-cells = <2>; |
| 365 | gpio-controller; | |
| c6ef2b34 | 366 | gpio-ranges = <&pfc 0 64 15>; |
| f51746ad GU |
367 | #interrupt-cells = <2>; |
| 368 | interrupt-controller; | |
| c6ef2b34 GU |
369 | clocks = <&cpg CPG_MOD 910>; |
| 370 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 371 | resets = <&cpg 910>; | |
| f51746ad GU |
372 | }; |
| 373 | ||
| 374 | gpio3: gpio@e6053000 { | |
| c6ef2b34 GU |
375 | compatible = "renesas,gpio-r8a77961", |
| 376 | "renesas,rcar-gen3-gpio"; | |
| f51746ad | 377 | reg = <0 0xe6053000 0 0x50>; |
| c6ef2b34 | 378 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| f51746ad GU |
379 | #gpio-cells = <2>; |
| 380 | gpio-controller; | |
| c6ef2b34 | 381 | gpio-ranges = <&pfc 0 96 16>; |
| f51746ad GU |
382 | #interrupt-cells = <2>; |
| 383 | interrupt-controller; | |
| c6ef2b34 GU |
384 | clocks = <&cpg CPG_MOD 909>; |
| 385 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 386 | resets = <&cpg 909>; | |
| f51746ad GU |
387 | }; |
| 388 | ||
| 389 | gpio4: gpio@e6054000 { | |
| c6ef2b34 GU |
390 | compatible = "renesas,gpio-r8a77961", |
| 391 | "renesas,rcar-gen3-gpio"; | |
| f51746ad | 392 | reg = <0 0xe6054000 0 0x50>; |
| c6ef2b34 | 393 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| f51746ad GU |
394 | #gpio-cells = <2>; |
| 395 | gpio-controller; | |
| c6ef2b34 | 396 | gpio-ranges = <&pfc 0 128 18>; |
| f51746ad GU |
397 | #interrupt-cells = <2>; |
| 398 | interrupt-controller; | |
| c6ef2b34 GU |
399 | clocks = <&cpg CPG_MOD 908>; |
| 400 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 401 | resets = <&cpg 908>; | |
| f51746ad GU |
402 | }; |
| 403 | ||
| 404 | gpio5: gpio@e6055000 { | |
| c6ef2b34 GU |
405 | compatible = "renesas,gpio-r8a77961", |
| 406 | "renesas,rcar-gen3-gpio"; | |
| f51746ad | 407 | reg = <0 0xe6055000 0 0x50>; |
| c6ef2b34 | 408 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| f51746ad GU |
409 | #gpio-cells = <2>; |
| 410 | gpio-controller; | |
| c6ef2b34 | 411 | gpio-ranges = <&pfc 0 160 26>; |
| f51746ad GU |
412 | #interrupt-cells = <2>; |
| 413 | interrupt-controller; | |
| c6ef2b34 GU |
414 | clocks = <&cpg CPG_MOD 907>; |
| 415 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 416 | resets = <&cpg 907>; | |
| f51746ad GU |
417 | }; |
| 418 | ||
| 419 | gpio6: gpio@e6055400 { | |
| c6ef2b34 GU |
420 | compatible = "renesas,gpio-r8a77961", |
| 421 | "renesas,rcar-gen3-gpio"; | |
| f51746ad | 422 | reg = <0 0xe6055400 0 0x50>; |
| c6ef2b34 | 423 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| f51746ad GU |
424 | #gpio-cells = <2>; |
| 425 | gpio-controller; | |
| c6ef2b34 | 426 | gpio-ranges = <&pfc 0 192 32>; |
| f51746ad GU |
427 | #interrupt-cells = <2>; |
| 428 | interrupt-controller; | |
| c6ef2b34 GU |
429 | clocks = <&cpg CPG_MOD 906>; |
| 430 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 431 | resets = <&cpg 906>; | |
| 432 | }; | |
| 433 | ||
| 434 | gpio7: gpio@e6055800 { | |
| 435 | compatible = "renesas,gpio-r8a77961", | |
| 436 | "renesas,rcar-gen3-gpio"; | |
| 437 | reg = <0 0xe6055800 0 0x50>; | |
| 438 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| 439 | #gpio-cells = <2>; | |
| 440 | gpio-controller; | |
| 441 | gpio-ranges = <&pfc 0 224 4>; | |
| 442 | #interrupt-cells = <2>; | |
| 443 | interrupt-controller; | |
| 444 | clocks = <&cpg CPG_MOD 905>; | |
| 445 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 446 | resets = <&cpg 905>; | |
| f51746ad GU |
447 | }; |
| 448 | ||
| a2053990 | 449 | pfc: pinctrl@e6060000 { |
| f51746ad GU |
450 | compatible = "renesas,pfc-r8a77961"; |
| 451 | reg = <0 0xe6060000 0 0x50c>; | |
| 452 | }; | |
| 453 | ||
| 5edf8bd6 NS |
454 | cmt0: timer@e60f0000 { |
| 455 | compatible = "renesas,r8a77961-cmt0", | |
| 456 | "renesas,rcar-gen3-cmt0"; | |
| 457 | reg = <0 0xe60f0000 0 0x1004>; | |
| 458 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
| 459 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
| 460 | clocks = <&cpg CPG_MOD 303>; | |
| 461 | clock-names = "fck"; | |
| 462 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 463 | resets = <&cpg 303>; | |
| 464 | status = "disabled"; | |
| 465 | }; | |
| 466 | ||
| 467 | cmt1: timer@e6130000 { | |
| 468 | compatible = "renesas,r8a77961-cmt1", | |
| 469 | "renesas,rcar-gen3-cmt1"; | |
| 470 | reg = <0 0xe6130000 0 0x1004>; | |
| 471 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, | |
| 472 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
| 473 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | |
| 474 | <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | |
| 475 | <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, | |
| 476 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, | |
| 477 | <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, | |
| 478 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; | |
| 479 | clocks = <&cpg CPG_MOD 302>; | |
| 480 | clock-names = "fck"; | |
| 481 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 482 | resets = <&cpg 302>; | |
| 483 | status = "disabled"; | |
| 484 | }; | |
| 485 | ||
| 486 | cmt2: timer@e6140000 { | |
| 487 | compatible = "renesas,r8a77961-cmt1", | |
| 488 | "renesas,rcar-gen3-cmt1"; | |
| 489 | reg = <0 0xe6140000 0 0x1004>; | |
| 490 | interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, | |
| 491 | <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, | |
| 492 | <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, | |
| 493 | <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, | |
| 494 | <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, | |
| 495 | <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, | |
| 496 | <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, | |
| 497 | <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; | |
| 498 | clocks = <&cpg CPG_MOD 301>; | |
| 499 | clock-names = "fck"; | |
| 500 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 501 | resets = <&cpg 301>; | |
| 502 | status = "disabled"; | |
| 503 | }; | |
| 504 | ||
| 505 | cmt3: timer@e6148000 { | |
| 506 | compatible = "renesas,r8a77961-cmt1", | |
| 507 | "renesas,rcar-gen3-cmt1"; | |
| 508 | reg = <0 0xe6148000 0 0x1004>; | |
| 509 | interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, | |
| 510 | <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, | |
| 511 | <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, | |
| 512 | <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, | |
| 513 | <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, | |
| 514 | <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, | |
| 515 | <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, | |
| 516 | <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; | |
| 517 | clocks = <&cpg CPG_MOD 300>; | |
| 518 | clock-names = "fck"; | |
| 519 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 520 | resets = <&cpg 300>; | |
| 521 | status = "disabled"; | |
| 522 | }; | |
| 523 | ||
| f51746ad GU |
524 | cpg: clock-controller@e6150000 { |
| 525 | compatible = "renesas,r8a77961-cpg-mssr"; | |
| 526 | reg = <0 0xe6150000 0 0x1000>; | |
| 527 | clocks = <&extal_clk>, <&extalr_clk>; | |
| 528 | clock-names = "extal", "extalr"; | |
| 529 | #clock-cells = <2>; | |
| 530 | #power-domain-cells = <0>; | |
| 531 | #reset-cells = <1>; | |
| 532 | }; | |
| 533 | ||
| 534 | rst: reset-controller@e6160000 { | |
| 535 | compatible = "renesas,r8a77961-rst"; | |
| 536 | reg = <0 0xe6160000 0 0x0200>; | |
| 537 | }; | |
| 538 | ||
| 539 | sysc: system-controller@e6180000 { | |
| 540 | compatible = "renesas,r8a77961-sysc"; | |
| 541 | reg = <0 0xe6180000 0 0x0400>; | |
| 542 | #power-domain-cells = <1>; | |
| 543 | }; | |
| 544 | ||
| 17ab3c3e GU |
545 | tsc: thermal@e6198000 { |
| 546 | compatible = "renesas,r8a77961-thermal"; | |
| 547 | reg = <0 0xe6198000 0 0x100>, | |
| 548 | <0 0xe61a0000 0 0x100>, | |
| 549 | <0 0xe61a8000 0 0x100>; | |
| 550 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | |
| 551 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
| 552 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
| 553 | clocks = <&cpg CPG_MOD 522>; | |
| 554 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 555 | resets = <&cpg 522>; | |
| 556 | #thermal-sensor-cells = <1>; | |
| 557 | }; | |
| 558 | ||
| f51746ad | 559 | intc_ex: interrupt-controller@e61c0000 { |
| 479c700c | 560 | compatible = "renesas,intc-ex-r8a77961", "renesas,irqc"; |
| f51746ad GU |
561 | #interrupt-cells = <2>; |
| 562 | interrupt-controller; | |
| 563 | reg = <0 0xe61c0000 0 0x200>; | |
| 479c700c GU |
564 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 565 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
| 566 | <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | |
| 567 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | |
| 568 | <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, | |
| 569 | <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; | |
| 570 | clocks = <&cpg CPG_MOD 407>; | |
| 571 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 572 | resets = <&cpg 407>; | |
| f51746ad GU |
573 | }; |
| 574 | ||
| 4e4c17c6 NS |
575 | tmu0: timer@e61e0000 { |
| 576 | compatible = "renesas,tmu-r8a77961", "renesas,tmu"; | |
| 577 | reg = <0 0xe61e0000 0 0x30>; | |
| 578 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
| 579 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, | |
| 580 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; | |
| c53866cb | 581 | interrupt-names = "tuni0", "tuni1", "tuni2"; |
| 4e4c17c6 NS |
582 | clocks = <&cpg CPG_MOD 125>; |
| 583 | clock-names = "fck"; | |
| 584 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 585 | resets = <&cpg 125>; | |
| 586 | status = "disabled"; | |
| 587 | }; | |
| 588 | ||
| 589 | tmu1: timer@e6fc0000 { | |
| 590 | compatible = "renesas,tmu-r8a77961", "renesas,tmu"; | |
| 591 | reg = <0 0xe6fc0000 0 0x30>; | |
| 592 | interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | |
| 593 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, | |
| c53866cb GU |
594 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
| 595 | <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; | |
| 596 | interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; | |
| 4e4c17c6 NS |
597 | clocks = <&cpg CPG_MOD 124>; |
| 598 | clock-names = "fck"; | |
| 599 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 600 | resets = <&cpg 124>; | |
| 601 | status = "disabled"; | |
| 602 | }; | |
| 603 | ||
| 604 | tmu2: timer@e6fd0000 { | |
| 605 | compatible = "renesas,tmu-r8a77961", "renesas,tmu"; | |
| 606 | reg = <0 0xe6fd0000 0 0x30>; | |
| 607 | interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, | |
| 608 | <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, | |
| c53866cb GU |
609 | <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, |
| 610 | <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; | |
| 611 | interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; | |
| 4e4c17c6 NS |
612 | clocks = <&cpg CPG_MOD 123>; |
| 613 | clock-names = "fck"; | |
| 614 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 615 | resets = <&cpg 123>; | |
| 616 | status = "disabled"; | |
| 617 | }; | |
| 618 | ||
| 619 | tmu3: timer@e6fe0000 { | |
| 620 | compatible = "renesas,tmu-r8a77961", "renesas,tmu"; | |
| 621 | reg = <0 0xe6fe0000 0 0x30>; | |
| 622 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
| 623 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, | |
| 624 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; | |
| c53866cb | 625 | interrupt-names = "tuni0", "tuni1", "tuni2"; |
| 4e4c17c6 NS |
626 | clocks = <&cpg CPG_MOD 122>; |
| 627 | clock-names = "fck"; | |
| 628 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 629 | resets = <&cpg 122>; | |
| 630 | status = "disabled"; | |
| 631 | }; | |
| 632 | ||
| 633 | tmu4: timer@ffc00000 { | |
| 634 | compatible = "renesas,tmu-r8a77961", "renesas,tmu"; | |
| 635 | reg = <0 0xffc00000 0 0x30>; | |
| 636 | interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, | |
| 637 | <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, | |
| 638 | <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; | |
| c53866cb | 639 | interrupt-names = "tuni0", "tuni1", "tuni2"; |
| 4e4c17c6 NS |
640 | clocks = <&cpg CPG_MOD 121>; |
| 641 | clock-names = "fck"; | |
| 642 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 643 | resets = <&cpg 121>; | |
| 644 | status = "disabled"; | |
| 645 | }; | |
| 646 | ||
| 19d40e55 GU |
647 | i2c0: i2c@e6500000 { |
| 648 | #address-cells = <1>; | |
| 649 | #size-cells = <0>; | |
| 650 | compatible = "renesas,i2c-r8a77961", | |
| 651 | "renesas,rcar-gen3-i2c"; | |
| 652 | reg = <0 0xe6500000 0 0x40>; | |
| 653 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; | |
| 654 | clocks = <&cpg CPG_MOD 931>; | |
| 655 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 656 | resets = <&cpg 931>; | |
| 657 | dmas = <&dmac1 0x91>, <&dmac1 0x90>, | |
| 658 | <&dmac2 0x91>, <&dmac2 0x90>; | |
| 659 | dma-names = "tx", "rx", "tx", "rx"; | |
| 660 | i2c-scl-internal-delay-ns = <110>; | |
| 661 | status = "disabled"; | |
| 662 | }; | |
| 663 | ||
| 664 | i2c1: i2c@e6508000 { | |
| 665 | #address-cells = <1>; | |
| 666 | #size-cells = <0>; | |
| 667 | compatible = "renesas,i2c-r8a77961", | |
| 668 | "renesas,rcar-gen3-i2c"; | |
| 669 | reg = <0 0xe6508000 0 0x40>; | |
| 670 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; | |
| 671 | clocks = <&cpg CPG_MOD 930>; | |
| 672 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 673 | resets = <&cpg 930>; | |
| 674 | dmas = <&dmac1 0x93>, <&dmac1 0x92>, | |
| 675 | <&dmac2 0x93>, <&dmac2 0x92>; | |
| 676 | dma-names = "tx", "rx", "tx", "rx"; | |
| 677 | i2c-scl-internal-delay-ns = <6>; | |
| 678 | status = "disabled"; | |
| 679 | }; | |
| 680 | ||
| f51746ad GU |
681 | i2c2: i2c@e6510000 { |
| 682 | #address-cells = <1>; | |
| 683 | #size-cells = <0>; | |
| 19d40e55 GU |
684 | compatible = "renesas,i2c-r8a77961", |
| 685 | "renesas,rcar-gen3-i2c"; | |
| f51746ad | 686 | reg = <0 0xe6510000 0 0x40>; |
| 19d40e55 GU |
687 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; |
| 688 | clocks = <&cpg CPG_MOD 929>; | |
| 689 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 690 | resets = <&cpg 929>; | |
| 691 | dmas = <&dmac1 0x95>, <&dmac1 0x94>, | |
| 692 | <&dmac2 0x95>, <&dmac2 0x94>; | |
| 693 | dma-names = "tx", "rx", "tx", "rx"; | |
| 694 | i2c-scl-internal-delay-ns = <6>; | |
| 695 | status = "disabled"; | |
| 696 | }; | |
| 697 | ||
| 698 | i2c3: i2c@e66d0000 { | |
| 699 | #address-cells = <1>; | |
| 700 | #size-cells = <0>; | |
| 701 | compatible = "renesas,i2c-r8a77961", | |
| 702 | "renesas,rcar-gen3-i2c"; | |
| 703 | reg = <0 0xe66d0000 0 0x40>; | |
| 704 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; | |
| 705 | clocks = <&cpg CPG_MOD 928>; | |
| 706 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 707 | resets = <&cpg 928>; | |
| 708 | dmas = <&dmac0 0x97>, <&dmac0 0x96>; | |
| 709 | dma-names = "tx", "rx"; | |
| 710 | i2c-scl-internal-delay-ns = <110>; | |
| 711 | status = "disabled"; | |
| f51746ad GU |
712 | }; |
| 713 | ||
| 714 | i2c4: i2c@e66d8000 { | |
| 715 | #address-cells = <1>; | |
| 716 | #size-cells = <0>; | |
| 19d40e55 GU |
717 | compatible = "renesas,i2c-r8a77961", |
| 718 | "renesas,rcar-gen3-i2c"; | |
| f51746ad | 719 | reg = <0 0xe66d8000 0 0x40>; |
| 19d40e55 GU |
720 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| 721 | clocks = <&cpg CPG_MOD 927>; | |
| 722 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 723 | resets = <&cpg 927>; | |
| 724 | dmas = <&dmac0 0x99>, <&dmac0 0x98>; | |
| 725 | dma-names = "tx", "rx"; | |
| 726 | i2c-scl-internal-delay-ns = <110>; | |
| 727 | status = "disabled"; | |
| 728 | }; | |
| 729 | ||
| 730 | i2c5: i2c@e66e0000 { | |
| 731 | #address-cells = <1>; | |
| 732 | #size-cells = <0>; | |
| 733 | compatible = "renesas,i2c-r8a77961", | |
| 734 | "renesas,rcar-gen3-i2c"; | |
| 735 | reg = <0 0xe66e0000 0 0x40>; | |
| 736 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
| 737 | clocks = <&cpg CPG_MOD 919>; | |
| 738 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 739 | resets = <&cpg 919>; | |
| 740 | dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; | |
| 741 | dma-names = "tx", "rx"; | |
| 742 | i2c-scl-internal-delay-ns = <110>; | |
| 743 | status = "disabled"; | |
| 744 | }; | |
| 745 | ||
| 746 | i2c6: i2c@e66e8000 { | |
| 747 | #address-cells = <1>; | |
| 748 | #size-cells = <0>; | |
| 749 | compatible = "renesas,i2c-r8a77961", | |
| 750 | "renesas,rcar-gen3-i2c"; | |
| 751 | reg = <0 0xe66e8000 0 0x40>; | |
| 752 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
| 753 | clocks = <&cpg CPG_MOD 918>; | |
| 754 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 755 | resets = <&cpg 918>; | |
| 756 | dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; | |
| 757 | dma-names = "tx", "rx"; | |
| 758 | i2c-scl-internal-delay-ns = <6>; | |
| 759 | status = "disabled"; | |
| f51746ad GU |
760 | }; |
| 761 | ||
| 762 | i2c_dvfs: i2c@e60b0000 { | |
| 763 | #address-cells = <1>; | |
| 764 | #size-cells = <0>; | |
| 19d40e55 GU |
765 | compatible = "renesas,iic-r8a77961", |
| 766 | "renesas,rcar-gen3-iic", | |
| 767 | "renesas,rmobile-iic"; | |
| f51746ad | 768 | reg = <0 0xe60b0000 0 0x425>; |
| 19d40e55 GU |
769 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
| 770 | clocks = <&cpg CPG_MOD 926>; | |
| 771 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 772 | resets = <&cpg 926>; | |
| 773 | dmas = <&dmac0 0x11>, <&dmac0 0x10>; | |
| 774 | dma-names = "tx", "rx"; | |
| 775 | status = "disabled"; | |
| f51746ad GU |
776 | }; |
| 777 | ||
| 3971a773 GU |
778 | hscif0: serial@e6540000 { |
| 779 | compatible = "renesas,hscif-r8a77961", | |
| 780 | "renesas,rcar-gen3-hscif", | |
| 781 | "renesas,hscif"; | |
| 782 | reg = <0 0xe6540000 0 0x60>; | |
| 783 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
| 784 | clocks = <&cpg CPG_MOD 520>, | |
| 785 | <&cpg CPG_CORE R8A77961_CLK_S3D1>, | |
| 786 | <&scif_clk>; | |
| 787 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 788 | dmas = <&dmac1 0x31>, <&dmac1 0x30>, | |
| 789 | <&dmac2 0x31>, <&dmac2 0x30>; | |
| 790 | dma-names = "tx", "rx", "tx", "rx"; | |
| 791 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 792 | resets = <&cpg 520>; | |
| 793 | status = "disabled"; | |
| 794 | }; | |
| 19d40e55 | 795 | |
| f51746ad | 796 | hscif1: serial@e6550000 { |
| 3971a773 GU |
797 | compatible = "renesas,hscif-r8a77961", |
| 798 | "renesas,rcar-gen3-hscif", | |
| 799 | "renesas,hscif"; | |
| f51746ad | 800 | reg = <0 0xe6550000 0 0x60>; |
| 3971a773 GU |
801 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
| 802 | clocks = <&cpg CPG_MOD 519>, | |
| 803 | <&cpg CPG_CORE R8A77961_CLK_S3D1>, | |
| 804 | <&scif_clk>; | |
| 805 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 806 | dmas = <&dmac1 0x33>, <&dmac1 0x32>, | |
| 807 | <&dmac2 0x33>, <&dmac2 0x32>; | |
| 808 | dma-names = "tx", "rx", "tx", "rx"; | |
| 809 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 810 | resets = <&cpg 519>; | |
| 811 | status = "disabled"; | |
| 812 | }; | |
| 813 | ||
| 814 | hscif2: serial@e6560000 { | |
| 815 | compatible = "renesas,hscif-r8a77961", | |
| 816 | "renesas,rcar-gen3-hscif", | |
| 817 | "renesas,hscif"; | |
| 818 | reg = <0 0xe6560000 0 0x60>; | |
| 819 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; | |
| 820 | clocks = <&cpg CPG_MOD 518>, | |
| 821 | <&cpg CPG_CORE R8A77961_CLK_S3D1>, | |
| 822 | <&scif_clk>; | |
| 823 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 824 | dmas = <&dmac1 0x35>, <&dmac1 0x34>, | |
| 825 | <&dmac2 0x35>, <&dmac2 0x34>; | |
| 826 | dma-names = "tx", "rx", "tx", "rx"; | |
| 827 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 828 | resets = <&cpg 518>; | |
| 829 | status = "disabled"; | |
| 830 | }; | |
| 831 | ||
| 832 | hscif3: serial@e66a0000 { | |
| 833 | compatible = "renesas,hscif-r8a77961", | |
| 834 | "renesas,rcar-gen3-hscif", | |
| 835 | "renesas,hscif"; | |
| 836 | reg = <0 0xe66a0000 0 0x60>; | |
| 837 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; | |
| 838 | clocks = <&cpg CPG_MOD 517>, | |
| 839 | <&cpg CPG_CORE R8A77961_CLK_S3D1>, | |
| 840 | <&scif_clk>; | |
| 841 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 842 | dmas = <&dmac0 0x37>, <&dmac0 0x36>; | |
| 843 | dma-names = "tx", "rx"; | |
| 844 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 845 | resets = <&cpg 517>; | |
| 846 | status = "disabled"; | |
| 847 | }; | |
| 848 | ||
| 849 | hscif4: serial@e66b0000 { | |
| 850 | compatible = "renesas,hscif-r8a77961", | |
| 851 | "renesas,rcar-gen3-hscif", | |
| 852 | "renesas,hscif"; | |
| 853 | reg = <0 0xe66b0000 0 0x60>; | |
| 854 | interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; | |
| 855 | clocks = <&cpg CPG_MOD 516>, | |
| 856 | <&cpg CPG_CORE R8A77961_CLK_S3D1>, | |
| 857 | <&scif_clk>; | |
| 858 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 859 | dmas = <&dmac0 0x39>, <&dmac0 0x38>; | |
| 860 | dma-names = "tx", "rx"; | |
| 861 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 862 | resets = <&cpg 516>; | |
| 863 | status = "disabled"; | |
| f51746ad GU |
864 | }; |
| 865 | ||
| 866 | hsusb: usb@e6590000 { | |
| 667fd76f YS |
867 | compatible = "renesas,usbhs-r8a77961", |
| 868 | "renesas,rcar-gen3-usbhs"; | |
| f51746ad | 869 | reg = <0 0xe6590000 0 0x200>; |
| 667fd76f YS |
870 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| 871 | clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; | |
| 872 | dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, | |
| 873 | <&usb_dmac1 0>, <&usb_dmac1 1>; | |
| 874 | dma-names = "ch0", "ch1", "ch2", "ch3"; | |
| 875 | renesas,buswait = <11>; | |
| 876 | phys = <&usb2_phy0 3>; | |
| 877 | phy-names = "usb"; | |
| 878 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 879 | resets = <&cpg 704>, <&cpg 703>; | |
| 880 | status = "disabled"; | |
| 881 | }; | |
| 882 | ||
| 883 | usb_dmac0: dma-controller@e65a0000 { | |
| 884 | compatible = "renesas,r8a77961-usb-dmac", | |
| 885 | "renesas,usb-dmac"; | |
| 886 | reg = <0 0xe65a0000 0 0x100>; | |
| 887 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
| 888 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | |
| 889 | interrupt-names = "ch0", "ch1"; | |
| 890 | clocks = <&cpg CPG_MOD 330>; | |
| 891 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 892 | resets = <&cpg 330>; | |
| 893 | #dma-cells = <1>; | |
| 894 | dma-channels = <2>; | |
| 895 | }; | |
| 896 | ||
| 897 | usb_dmac1: dma-controller@e65b0000 { | |
| 898 | compatible = "renesas,r8a77961-usb-dmac", | |
| 899 | "renesas,usb-dmac"; | |
| 900 | reg = <0 0xe65b0000 0 0x100>; | |
| 901 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
| 902 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; | |
| 903 | interrupt-names = "ch0", "ch1"; | |
| 904 | clocks = <&cpg CPG_MOD 331>; | |
| 905 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 906 | resets = <&cpg 331>; | |
| 907 | #dma-cells = <1>; | |
| 908 | dma-channels = <2>; | |
| f51746ad GU |
909 | }; |
| 910 | ||
| 911 | usb3_phy0: usb-phy@e65ee000 { | |
| 8ab47ffc YS |
912 | compatible = "renesas,r8a77961-usb3-phy", |
| 913 | "renesas,rcar-gen3-usb3-phy"; | |
| f51746ad | 914 | reg = <0 0xe65ee000 0 0x90>; |
| 8ab47ffc YS |
915 | clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, |
| 916 | <&usb_extal_clk>; | |
| 917 | clock-names = "usb3-if", "usb3s_clk", "usb_extal"; | |
| 918 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 919 | resets = <&cpg 328>; | |
| f51746ad | 920 | #phy-cells = <0>; |
| 8ab47ffc | 921 | status = "disabled"; |
| f51746ad GU |
922 | }; |
| 923 | ||
| a582013b GU |
924 | arm_cc630p: crypto@e6601000 { |
| 925 | compatible = "arm,cryptocell-630p-ree"; | |
| 926 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
| 927 | reg = <0x0 0xe6601000 0 0x1000>; | |
| 928 | clocks = <&cpg CPG_MOD 229>; | |
| 929 | resets = <&cpg 229>; | |
| 930 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 931 | }; | |
| 932 | ||
| 8372579d GU |
933 | dmac0: dma-controller@e6700000 { |
| 934 | compatible = "renesas,dmac-r8a77961", | |
| 935 | "renesas,rcar-dmac"; | |
| 936 | reg = <0 0xe6700000 0 0x10000>; | |
| 937 | interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, | |
| 938 | <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, | |
| 939 | <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, | |
| 940 | <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, | |
| 941 | <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, | |
| 942 | <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, | |
| 943 | <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, | |
| 944 | <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, | |
| 945 | <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, | |
| 946 | <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, | |
| 947 | <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, | |
| 948 | <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, | |
| 949 | <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, | |
| 950 | <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, | |
| 951 | <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, | |
| 952 | <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, | |
| 953 | <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; | |
| 954 | interrupt-names = "error", | |
| 955 | "ch0", "ch1", "ch2", "ch3", | |
| 956 | "ch4", "ch5", "ch6", "ch7", | |
| 957 | "ch8", "ch9", "ch10", "ch11", | |
| 958 | "ch12", "ch13", "ch14", "ch15"; | |
| 959 | clocks = <&cpg CPG_MOD 219>; | |
| 960 | clock-names = "fck"; | |
| 961 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 962 | resets = <&cpg 219>; | |
| 963 | #dma-cells = <1>; | |
| 964 | dma-channels = <16>; | |
| 651f8cff YS |
965 | iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, |
| 966 | <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, | |
| 967 | <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, | |
| 968 | <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, | |
| 969 | <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, | |
| 970 | <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, | |
| 971 | <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, | |
| 972 | <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; | |
| 8372579d GU |
973 | }; |
| 974 | ||
| 975 | dmac1: dma-controller@e7300000 { | |
| 976 | compatible = "renesas,dmac-r8a77961", | |
| 977 | "renesas,rcar-dmac"; | |
| 978 | reg = <0 0xe7300000 0 0x10000>; | |
| 979 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, | |
| 980 | <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, | |
| 981 | <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, | |
| 982 | <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, | |
| 983 | <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, | |
| 984 | <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, | |
| 985 | <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, | |
| 986 | <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, | |
| 987 | <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, | |
| 988 | <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, | |
| 989 | <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, | |
| 990 | <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, | |
| 991 | <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, | |
| 992 | <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, | |
| 993 | <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, | |
| 994 | <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, | |
| 995 | <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; | |
| 996 | interrupt-names = "error", | |
| 997 | "ch0", "ch1", "ch2", "ch3", | |
| 998 | "ch4", "ch5", "ch6", "ch7", | |
| 999 | "ch8", "ch9", "ch10", "ch11", | |
| 1000 | "ch12", "ch13", "ch14", "ch15"; | |
| 1001 | clocks = <&cpg CPG_MOD 218>; | |
| 1002 | clock-names = "fck"; | |
| 1003 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1004 | resets = <&cpg 218>; | |
| 1005 | #dma-cells = <1>; | |
| 1006 | dma-channels = <16>; | |
| 651f8cff YS |
1007 | iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, |
| 1008 | <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, | |
| 1009 | <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, | |
| 1010 | <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, | |
| 1011 | <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, | |
| 1012 | <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, | |
| 1013 | <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, | |
| 1014 | <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; | |
| 8372579d GU |
1015 | }; |
| 1016 | ||
| 1017 | dmac2: dma-controller@e7310000 { | |
| 1018 | compatible = "renesas,dmac-r8a77961", | |
| 1019 | "renesas,rcar-dmac"; | |
| 1020 | reg = <0 0xe7310000 0 0x10000>; | |
| 1021 | interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, | |
| 1022 | <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, | |
| 1023 | <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, | |
| 1024 | <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, | |
| 1025 | <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, | |
| 1026 | <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, | |
| 1027 | <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, | |
| 1028 | <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, | |
| 1029 | <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, | |
| 1030 | <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, | |
| 1031 | <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, | |
| 1032 | <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, | |
| 1033 | <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, | |
| 1034 | <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, | |
| 1035 | <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, | |
| 1036 | <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, | |
| 1037 | <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; | |
| 1038 | interrupt-names = "error", | |
| 1039 | "ch0", "ch1", "ch2", "ch3", | |
| 1040 | "ch4", "ch5", "ch6", "ch7", | |
| 1041 | "ch8", "ch9", "ch10", "ch11", | |
| 1042 | "ch12", "ch13", "ch14", "ch15"; | |
| 1043 | clocks = <&cpg CPG_MOD 217>; | |
| 1044 | clock-names = "fck"; | |
| 1045 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1046 | resets = <&cpg 217>; | |
| 1047 | #dma-cells = <1>; | |
| 1048 | dma-channels = <16>; | |
| 651f8cff YS |
1049 | iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, |
| 1050 | <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, | |
| 1051 | <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, | |
| 1052 | <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, | |
| 1053 | <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, | |
| 1054 | <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, | |
| 1055 | <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, | |
| 1056 | <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; | |
| 8372579d GU |
1057 | }; |
| 1058 | ||
| 8bd35145 YS |
1059 | ipmmu_ds0: iommu@e6740000 { |
| 1060 | compatible = "renesas,ipmmu-r8a77961"; | |
| 1061 | reg = <0 0xe6740000 0 0x1000>; | |
| 1062 | renesas,ipmmu-main = <&ipmmu_mm 0>; | |
| 1063 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1064 | #iommu-cells = <1>; | |
| 1065 | }; | |
| 1066 | ||
| 1067 | ipmmu_ds1: iommu@e7740000 { | |
| 1068 | compatible = "renesas,ipmmu-r8a77961"; | |
| 1069 | reg = <0 0xe7740000 0 0x1000>; | |
| 1070 | renesas,ipmmu-main = <&ipmmu_mm 1>; | |
| 1071 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1072 | #iommu-cells = <1>; | |
| 1073 | }; | |
| 1074 | ||
| 1075 | ipmmu_hc: iommu@e6570000 { | |
| 1076 | compatible = "renesas,ipmmu-r8a77961"; | |
| 1077 | reg = <0 0xe6570000 0 0x1000>; | |
| 1078 | renesas,ipmmu-main = <&ipmmu_mm 2>; | |
| 1079 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1080 | #iommu-cells = <1>; | |
| 1081 | }; | |
| 1082 | ||
| 1083 | ipmmu_ir: iommu@ff8b0000 { | |
| 1084 | compatible = "renesas,ipmmu-r8a77961"; | |
| 1085 | reg = <0 0xff8b0000 0 0x1000>; | |
| 1086 | renesas,ipmmu-main = <&ipmmu_mm 3>; | |
| 1087 | power-domains = <&sysc R8A77961_PD_A3IR>; | |
| 1088 | #iommu-cells = <1>; | |
| 1089 | }; | |
| 1090 | ||
| 1091 | ipmmu_mm: iommu@e67b0000 { | |
| 1092 | compatible = "renesas,ipmmu-r8a77961"; | |
| 1093 | reg = <0 0xe67b0000 0 0x1000>; | |
| 1094 | interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, | |
| 1095 | <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; | |
| 1096 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1097 | #iommu-cells = <1>; | |
| 1098 | }; | |
| 1099 | ||
| 1100 | ipmmu_mp: iommu@ec670000 { | |
| 1101 | compatible = "renesas,ipmmu-r8a77961"; | |
| 1102 | reg = <0 0xec670000 0 0x1000>; | |
| 1103 | renesas,ipmmu-main = <&ipmmu_mm 4>; | |
| 1104 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1105 | #iommu-cells = <1>; | |
| 1106 | }; | |
| 1107 | ||
| 1108 | ipmmu_pv0: iommu@fd800000 { | |
| 1109 | compatible = "renesas,ipmmu-r8a77961"; | |
| 1110 | reg = <0 0xfd800000 0 0x1000>; | |
| 1111 | renesas,ipmmu-main = <&ipmmu_mm 5>; | |
| 1112 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1113 | #iommu-cells = <1>; | |
| 1114 | }; | |
| 1115 | ||
| 1116 | ipmmu_pv1: iommu@fd950000 { | |
| 1117 | compatible = "renesas,ipmmu-r8a77961"; | |
| 1118 | reg = <0 0xfd950000 0 0x1000>; | |
| 1119 | renesas,ipmmu-main = <&ipmmu_mm 6>; | |
| 1120 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1121 | #iommu-cells = <1>; | |
| 1122 | }; | |
| 1123 | ||
| 1124 | ipmmu_rt: iommu@ffc80000 { | |
| 1125 | compatible = "renesas,ipmmu-r8a77961"; | |
| 1126 | reg = <0 0xffc80000 0 0x1000>; | |
| 1127 | renesas,ipmmu-main = <&ipmmu_mm 7>; | |
| 1128 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1129 | #iommu-cells = <1>; | |
| 1130 | }; | |
| 1131 | ||
| 1132 | ipmmu_vc0: iommu@fe6b0000 { | |
| 1133 | compatible = "renesas,ipmmu-r8a77961"; | |
| 1134 | reg = <0 0xfe6b0000 0 0x1000>; | |
| 1135 | renesas,ipmmu-main = <&ipmmu_mm 8>; | |
| 1136 | power-domains = <&sysc R8A77961_PD_A3VC>; | |
| 1137 | #iommu-cells = <1>; | |
| 1138 | }; | |
| 1139 | ||
| 1140 | ipmmu_vi0: iommu@febd0000 { | |
| 1141 | compatible = "renesas,ipmmu-r8a77961"; | |
| 1142 | reg = <0 0xfebd0000 0 0x1000>; | |
| 1143 | renesas,ipmmu-main = <&ipmmu_mm 9>; | |
| 1144 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1145 | #iommu-cells = <1>; | |
| 1146 | }; | |
| 1147 | ||
| f51746ad | 1148 | avb: ethernet@e6800000 { |
| 9ccf74a9 GU |
1149 | compatible = "renesas,etheravb-r8a77961", |
| 1150 | "renesas,etheravb-rcar-gen3"; | |
| f51746ad | 1151 | reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; |
| 9ccf74a9 GU |
1152 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
| 1153 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
| 1154 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
| 1155 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
| 1156 | <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, | |
| 1157 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | |
| 1158 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, | |
| 1159 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | |
| 1160 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, | |
| 1161 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, | |
| 1162 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
| 1163 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, | |
| 1164 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | |
| 1165 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | |
| 1166 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
| 1167 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
| 1168 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
| 1169 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | |
| 1170 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, | |
| 1171 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | |
| 1172 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
| 1173 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
| 1174 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, | |
| 1175 | <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, | |
| 1176 | <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
| 1177 | interrupt-names = "ch0", "ch1", "ch2", "ch3", | |
| 1178 | "ch4", "ch5", "ch6", "ch7", | |
| 1179 | "ch8", "ch9", "ch10", "ch11", | |
| 1180 | "ch12", "ch13", "ch14", "ch15", | |
| 1181 | "ch16", "ch17", "ch18", "ch19", | |
| 1182 | "ch20", "ch21", "ch22", "ch23", | |
| 1183 | "ch24"; | |
| 1184 | clocks = <&cpg CPG_MOD 812>; | |
| 56ed0b3b | 1185 | clock-names = "fck"; |
| 9ccf74a9 GU |
1186 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; |
| 1187 | resets = <&cpg 812>; | |
| 1188 | phy-mode = "rgmii"; | |
| 9b810181 GU |
1189 | rx-internal-delay-ps = <0>; |
| 1190 | tx-internal-delay-ps = <0>; | |
| 651f8cff | 1191 | iommus = <&ipmmu_ds0 16>; |
| f51746ad GU |
1192 | #address-cells = <1>; |
| 1193 | #size-cells = <0>; | |
| 9ccf74a9 | 1194 | status = "disabled"; |
| f51746ad GU |
1195 | }; |
| 1196 | ||
| f8a1620c | 1197 | can0: can@e6c30000 { |
| 92c406ed YS |
1198 | compatible = "renesas,can-r8a77961", |
| 1199 | "renesas,rcar-gen3-can"; | |
| f8a1620c | 1200 | reg = <0 0xe6c30000 0 0x1000>; |
| 92c406ed YS |
1201 | interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; |
| 1202 | clocks = <&cpg CPG_MOD 916>, | |
| 1203 | <&cpg CPG_CORE R8A77961_CLK_CANFD>, | |
| 1204 | <&can_clk>; | |
| 1205 | clock-names = "clkp1", "clkp2", "can_clk"; | |
| 1206 | assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; | |
| 1207 | assigned-clock-rates = <40000000>; | |
| 1208 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1209 | resets = <&cpg 916>; | |
| 1210 | status = "disabled"; | |
| f8a1620c ER |
1211 | }; |
| 1212 | ||
| 1213 | can1: can@e6c38000 { | |
| 92c406ed YS |
1214 | compatible = "renesas,can-r8a77961", |
| 1215 | "renesas,rcar-gen3-can"; | |
| f8a1620c | 1216 | reg = <0 0xe6c38000 0 0x1000>; |
| 92c406ed YS |
1217 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; |
| 1218 | clocks = <&cpg CPG_MOD 915>, | |
| 1219 | <&cpg CPG_CORE R8A77961_CLK_CANFD>, | |
| 1220 | <&can_clk>; | |
| 1221 | clock-names = "clkp1", "clkp2", "can_clk"; | |
| 1222 | assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; | |
| 1223 | assigned-clock-rates = <40000000>; | |
| 1224 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1225 | resets = <&cpg 915>; | |
| 1226 | status = "disabled"; | |
| f8a1620c ER |
1227 | }; |
| 1228 | ||
| 0182581a KM |
1229 | canfd: can@e66c0000 { |
| 1230 | compatible = "renesas,r8a77961-canfd", | |
| 1231 | "renesas,rcar-gen3-canfd"; | |
| 1232 | reg = <0 0xe66c0000 0 0x8000>; | |
| 1233 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, | |
| 1234 | <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
| 6af663af | 1235 | interrupt-names = "ch_int", "g_int"; |
| 0182581a KM |
1236 | clocks = <&cpg CPG_MOD 914>, |
| 1237 | <&cpg CPG_CORE R8A77961_CLK_CANFD>, | |
| 1238 | <&can_clk>; | |
| 1239 | clock-names = "fck", "canfd", "can_clk"; | |
| 1240 | assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; | |
| 1241 | assigned-clock-rates = <40000000>; | |
| 1242 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1243 | resets = <&cpg 914>; | |
| 1244 | status = "disabled"; | |
| 1245 | ||
| 1246 | channel0 { | |
| 1247 | status = "disabled"; | |
| 1248 | }; | |
| 1249 | ||
| 1250 | channel1 { | |
| 1251 | status = "disabled"; | |
| 1252 | }; | |
| 1253 | }; | |
| 1254 | ||
| 174d0967 YS |
1255 | pwm0: pwm@e6e30000 { |
| 1256 | compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; | |
| 1257 | reg = <0 0xe6e30000 0 8>; | |
| 1258 | #pwm-cells = <2>; | |
| 1259 | clocks = <&cpg CPG_MOD 523>; | |
| 1260 | resets = <&cpg 523>; | |
| 1261 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1262 | status = "disabled"; | |
| 1263 | }; | |
| 1264 | ||
| f51746ad | 1265 | pwm1: pwm@e6e31000 { |
| 174d0967 | 1266 | compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; |
| f51746ad GU |
1267 | reg = <0 0xe6e31000 0 8>; |
| 1268 | #pwm-cells = <2>; | |
| 174d0967 YS |
1269 | clocks = <&cpg CPG_MOD 523>; |
| 1270 | resets = <&cpg 523>; | |
| 1271 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1272 | status = "disabled"; | |
| 1273 | }; | |
| 1274 | ||
| 1275 | pwm2: pwm@e6e32000 { | |
| 1276 | compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; | |
| 1277 | reg = <0 0xe6e32000 0 8>; | |
| 1278 | #pwm-cells = <2>; | |
| 1279 | clocks = <&cpg CPG_MOD 523>; | |
| 1280 | resets = <&cpg 523>; | |
| 1281 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1282 | status = "disabled"; | |
| 1283 | }; | |
| 1284 | ||
| 1285 | pwm3: pwm@e6e33000 { | |
| 1286 | compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; | |
| 1287 | reg = <0 0xe6e33000 0 8>; | |
| 1288 | #pwm-cells = <2>; | |
| 1289 | clocks = <&cpg CPG_MOD 523>; | |
| 1290 | resets = <&cpg 523>; | |
| 1291 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1292 | status = "disabled"; | |
| 1293 | }; | |
| 1294 | ||
| 1295 | pwm4: pwm@e6e34000 { | |
| 1296 | compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; | |
| 1297 | reg = <0 0xe6e34000 0 8>; | |
| 1298 | #pwm-cells = <2>; | |
| 1299 | clocks = <&cpg CPG_MOD 523>; | |
| 1300 | resets = <&cpg 523>; | |
| 1301 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1302 | status = "disabled"; | |
| 1303 | }; | |
| 1304 | ||
| 1305 | pwm5: pwm@e6e35000 { | |
| 1306 | compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; | |
| 1307 | reg = <0 0xe6e35000 0 8>; | |
| 1308 | #pwm-cells = <2>; | |
| 1309 | clocks = <&cpg CPG_MOD 523>; | |
| 1310 | resets = <&cpg 523>; | |
| 1311 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1312 | status = "disabled"; | |
| 1313 | }; | |
| 1314 | ||
| 1315 | pwm6: pwm@e6e36000 { | |
| 1316 | compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; | |
| 1317 | reg = <0 0xe6e36000 0 8>; | |
| 1318 | #pwm-cells = <2>; | |
| 1319 | clocks = <&cpg CPG_MOD 523>; | |
| 1320 | resets = <&cpg 523>; | |
| 1321 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1322 | status = "disabled"; | |
| f51746ad GU |
1323 | }; |
| 1324 | ||
| 3971a773 GU |
1325 | scif0: serial@e6e60000 { |
| 1326 | compatible = "renesas,scif-r8a77961", | |
| 1327 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 1328 | reg = <0 0xe6e60000 0 64>; | |
| 1329 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
| 1330 | clocks = <&cpg CPG_MOD 207>, | |
| 1331 | <&cpg CPG_CORE R8A77961_CLK_S3D1>, | |
| 1332 | <&scif_clk>; | |
| 1333 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 1334 | dmas = <&dmac1 0x51>, <&dmac1 0x50>, | |
| 1335 | <&dmac2 0x51>, <&dmac2 0x50>; | |
| 1336 | dma-names = "tx", "rx", "tx", "rx"; | |
| 1337 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1338 | resets = <&cpg 207>; | |
| 1339 | status = "disabled"; | |
| 1340 | }; | |
| 1341 | ||
| f51746ad | 1342 | scif1: serial@e6e68000 { |
| 3971a773 GU |
1343 | compatible = "renesas,scif-r8a77961", |
| 1344 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| f51746ad | 1345 | reg = <0 0xe6e68000 0 64>; |
| 3971a773 GU |
1346 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
| 1347 | clocks = <&cpg CPG_MOD 206>, | |
| 1348 | <&cpg CPG_CORE R8A77961_CLK_S3D1>, | |
| 1349 | <&scif_clk>; | |
| 1350 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 1351 | dmas = <&dmac1 0x53>, <&dmac1 0x52>, | |
| 1352 | <&dmac2 0x53>, <&dmac2 0x52>; | |
| 1353 | dma-names = "tx", "rx", "tx", "rx"; | |
| 1354 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1355 | resets = <&cpg 206>; | |
| 1356 | status = "disabled"; | |
| f51746ad GU |
1357 | }; |
| 1358 | ||
| 1359 | scif2: serial@e6e88000 { | |
| 1360 | compatible = "renesas,scif-r8a77961", | |
| 1361 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 1362 | reg = <0 0xe6e88000 0 64>; | |
| 1363 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
| 1364 | clocks = <&cpg CPG_MOD 310>, | |
| 1365 | <&cpg CPG_CORE R8A77961_CLK_S3D1>, | |
| 1366 | <&scif_clk>; | |
| 1367 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 3971a773 GU |
1368 | dmas = <&dmac1 0x13>, <&dmac1 0x12>, |
| 1369 | <&dmac2 0x13>, <&dmac2 0x12>; | |
| 1370 | dma-names = "tx", "rx", "tx", "rx"; | |
| f51746ad GU |
1371 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; |
| 1372 | resets = <&cpg 310>; | |
| 1373 | status = "disabled"; | |
| 1374 | }; | |
| 1375 | ||
| 3971a773 GU |
1376 | scif3: serial@e6c50000 { |
| 1377 | compatible = "renesas,scif-r8a77961", | |
| 1378 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 1379 | reg = <0 0xe6c50000 0 64>; | |
| 1380 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
| 1381 | clocks = <&cpg CPG_MOD 204>, | |
| 1382 | <&cpg CPG_CORE R8A77961_CLK_S3D1>, | |
| 1383 | <&scif_clk>; | |
| 1384 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 1385 | dmas = <&dmac0 0x57>, <&dmac0 0x56>; | |
| 1386 | dma-names = "tx", "rx"; | |
| 1387 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1388 | resets = <&cpg 204>; | |
| 1389 | status = "disabled"; | |
| 1390 | }; | |
| 1391 | ||
| 1392 | scif4: serial@e6c40000 { | |
| 1393 | compatible = "renesas,scif-r8a77961", | |
| 1394 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 1395 | reg = <0 0xe6c40000 0 64>; | |
| 1396 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
| 1397 | clocks = <&cpg CPG_MOD 203>, | |
| 1398 | <&cpg CPG_CORE R8A77961_CLK_S3D1>, | |
| 1399 | <&scif_clk>; | |
| 1400 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 1401 | dmas = <&dmac0 0x59>, <&dmac0 0x58>; | |
| 1402 | dma-names = "tx", "rx"; | |
| 1403 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1404 | resets = <&cpg 203>; | |
| 1405 | status = "disabled"; | |
| 1406 | }; | |
| 1407 | ||
| 1408 | scif5: serial@e6f30000 { | |
| 1409 | compatible = "renesas,scif-r8a77961", | |
| 1410 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 1411 | reg = <0 0xe6f30000 0 64>; | |
| 1412 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
| 1413 | clocks = <&cpg CPG_MOD 202>, | |
| 1414 | <&cpg CPG_CORE R8A77961_CLK_S3D1>, | |
| 1415 | <&scif_clk>; | |
| 1416 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 1417 | dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, | |
| 1418 | <&dmac2 0x5b>, <&dmac2 0x5a>; | |
| 1419 | dma-names = "tx", "rx", "tx", "rx"; | |
| 1420 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1421 | resets = <&cpg 202>; | |
| 1422 | status = "disabled"; | |
| 1423 | }; | |
| 1424 | ||
| c6d38761 WS |
1425 | tpu: pwm@e6e80000 { |
| 1426 | compatible = "renesas,tpu-r8a77961", "renesas,tpu"; | |
| 1427 | reg = <0 0xe6e80000 0 0x148>; | |
| 1428 | interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; | |
| 1429 | clocks = <&cpg CPG_MOD 304>; | |
| 1430 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1431 | resets = <&cpg 304>; | |
| 1432 | #pwm-cells = <3>; | |
| 1433 | status = "disabled"; | |
| 1434 | }; | |
| 1435 | ||
| ca3b4330 GU |
1436 | msiof0: spi@e6e90000 { |
| 1437 | compatible = "renesas,msiof-r8a77961", | |
| 1438 | "renesas,rcar-gen3-msiof"; | |
| 1439 | reg = <0 0xe6e90000 0 0x0064>; | |
| 1440 | interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; | |
| 1441 | clocks = <&cpg CPG_MOD 211>; | |
| 1442 | dmas = <&dmac1 0x41>, <&dmac1 0x40>, | |
| 1443 | <&dmac2 0x41>, <&dmac2 0x40>; | |
| 1444 | dma-names = "tx", "rx", "tx", "rx"; | |
| 1445 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1446 | resets = <&cpg 211>; | |
| 1447 | #address-cells = <1>; | |
| 1448 | #size-cells = <0>; | |
| 1449 | status = "disabled"; | |
| 1450 | }; | |
| 1451 | ||
| 1452 | msiof1: spi@e6ea0000 { | |
| 1453 | compatible = "renesas,msiof-r8a77961", | |
| 1454 | "renesas,rcar-gen3-msiof"; | |
| 1455 | reg = <0 0xe6ea0000 0 0x0064>; | |
| 1456 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; | |
| 1457 | clocks = <&cpg CPG_MOD 210>; | |
| 1458 | dmas = <&dmac1 0x43>, <&dmac1 0x42>, | |
| 1459 | <&dmac2 0x43>, <&dmac2 0x42>; | |
| 1460 | dma-names = "tx", "rx", "tx", "rx"; | |
| 1461 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1462 | resets = <&cpg 210>; | |
| 1463 | #address-cells = <1>; | |
| 1464 | #size-cells = <0>; | |
| 1465 | status = "disabled"; | |
| 1466 | }; | |
| 1467 | ||
| 1468 | msiof2: spi@e6c00000 { | |
| 1469 | compatible = "renesas,msiof-r8a77961", | |
| 1470 | "renesas,rcar-gen3-msiof"; | |
| 1471 | reg = <0 0xe6c00000 0 0x0064>; | |
| 1472 | interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; | |
| 1473 | clocks = <&cpg CPG_MOD 209>; | |
| 1474 | dmas = <&dmac0 0x45>, <&dmac0 0x44>; | |
| 1475 | dma-names = "tx", "rx"; | |
| 1476 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1477 | resets = <&cpg 209>; | |
| 1478 | #address-cells = <1>; | |
| 1479 | #size-cells = <0>; | |
| 1480 | status = "disabled"; | |
| 1481 | }; | |
| 1482 | ||
| 1483 | msiof3: spi@e6c10000 { | |
| 1484 | compatible = "renesas,msiof-r8a77961", | |
| 1485 | "renesas,rcar-gen3-msiof"; | |
| 1486 | reg = <0 0xe6c10000 0 0x0064>; | |
| 1487 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; | |
| 1488 | clocks = <&cpg CPG_MOD 208>; | |
| 1489 | dmas = <&dmac0 0x47>, <&dmac0 0x46>; | |
| 1490 | dma-names = "tx", "rx"; | |
| 1491 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1492 | resets = <&cpg 208>; | |
| 1493 | #address-cells = <1>; | |
| 1494 | #size-cells = <0>; | |
| 1495 | status = "disabled"; | |
| 1496 | }; | |
| 1497 | ||
| f51746ad | 1498 | vin0: video@e6ef0000 { |
| c7b22b50 | 1499 | compatible = "renesas,vin-r8a77961"; |
| f51746ad | 1500 | reg = <0 0xe6ef0000 0 0x1000>; |
| c7b22b50 NS |
1501 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; |
| 1502 | clocks = <&cpg CPG_MOD 811>; | |
| 1503 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1504 | resets = <&cpg 811>; | |
| 1505 | renesas,id = <0>; | |
| 1506 | status = "disabled"; | |
| 1507 | ||
| 1508 | ports { | |
| 1509 | #address-cells = <1>; | |
| 1510 | #size-cells = <0>; | |
| 1511 | ||
| 1512 | port@1 { | |
| 1513 | #address-cells = <1>; | |
| 1514 | #size-cells = <0>; | |
| 1515 | ||
| 1516 | reg = <1>; | |
| 1517 | ||
| 1518 | vin0csi20: endpoint@0 { | |
| 1519 | reg = <0>; | |
| 1520 | remote-endpoint = <&csi20vin0>; | |
| 1521 | }; | |
| 1522 | vin0csi40: endpoint@2 { | |
| 1523 | reg = <2>; | |
| 1524 | remote-endpoint = <&csi40vin0>; | |
| 1525 | }; | |
| 1526 | }; | |
| 1527 | }; | |
| f51746ad GU |
1528 | }; |
| 1529 | ||
| 1530 | vin1: video@e6ef1000 { | |
| c7b22b50 | 1531 | compatible = "renesas,vin-r8a77961"; |
| f51746ad | 1532 | reg = <0 0xe6ef1000 0 0x1000>; |
| c7b22b50 NS |
1533 | interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; |
| 1534 | clocks = <&cpg CPG_MOD 810>; | |
| 1535 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1536 | resets = <&cpg 810>; | |
| 1537 | renesas,id = <1>; | |
| 1538 | status = "disabled"; | |
| 1539 | ||
| 1540 | ports { | |
| 1541 | #address-cells = <1>; | |
| 1542 | #size-cells = <0>; | |
| 1543 | ||
| 1544 | port@1 { | |
| 1545 | #address-cells = <1>; | |
| 1546 | #size-cells = <0>; | |
| 1547 | ||
| 1548 | reg = <1>; | |
| 1549 | ||
| 1550 | vin1csi20: endpoint@0 { | |
| 1551 | reg = <0>; | |
| 1552 | remote-endpoint = <&csi20vin1>; | |
| 1553 | }; | |
| 1554 | vin1csi40: endpoint@2 { | |
| 1555 | reg = <2>; | |
| 1556 | remote-endpoint = <&csi40vin1>; | |
| 1557 | }; | |
| 1558 | }; | |
| 1559 | }; | |
| f51746ad GU |
1560 | }; |
| 1561 | ||
| 1562 | vin2: video@e6ef2000 { | |
| c7b22b50 | 1563 | compatible = "renesas,vin-r8a77961"; |
| f51746ad | 1564 | reg = <0 0xe6ef2000 0 0x1000>; |
| c7b22b50 NS |
1565 | interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; |
| 1566 | clocks = <&cpg CPG_MOD 809>; | |
| 1567 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1568 | resets = <&cpg 809>; | |
| 1569 | renesas,id = <2>; | |
| 1570 | status = "disabled"; | |
| 1571 | ||
| 1572 | ports { | |
| 1573 | #address-cells = <1>; | |
| 1574 | #size-cells = <0>; | |
| 1575 | ||
| 1576 | port@1 { | |
| 1577 | #address-cells = <1>; | |
| 1578 | #size-cells = <0>; | |
| 1579 | ||
| 1580 | reg = <1>; | |
| 1581 | ||
| 1582 | vin2csi20: endpoint@0 { | |
| 1583 | reg = <0>; | |
| 1584 | remote-endpoint = <&csi20vin2>; | |
| 1585 | }; | |
| 1586 | vin2csi40: endpoint@2 { | |
| 1587 | reg = <2>; | |
| 1588 | remote-endpoint = <&csi40vin2>; | |
| 1589 | }; | |
| 1590 | }; | |
| 1591 | }; | |
| f51746ad GU |
1592 | }; |
| 1593 | ||
| 1594 | vin3: video@e6ef3000 { | |
| c7b22b50 | 1595 | compatible = "renesas,vin-r8a77961"; |
| f51746ad | 1596 | reg = <0 0xe6ef3000 0 0x1000>; |
| c7b22b50 NS |
1597 | interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; |
| 1598 | clocks = <&cpg CPG_MOD 808>; | |
| 1599 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1600 | resets = <&cpg 808>; | |
| 1601 | renesas,id = <3>; | |
| 1602 | status = "disabled"; | |
| 1603 | ||
| 1604 | ports { | |
| 1605 | #address-cells = <1>; | |
| 1606 | #size-cells = <0>; | |
| 1607 | ||
| 1608 | port@1 { | |
| 1609 | #address-cells = <1>; | |
| 1610 | #size-cells = <0>; | |
| 1611 | ||
| 1612 | reg = <1>; | |
| 1613 | ||
| 1614 | vin3csi20: endpoint@0 { | |
| 1615 | reg = <0>; | |
| 1616 | remote-endpoint = <&csi20vin3>; | |
| 1617 | }; | |
| 1618 | vin3csi40: endpoint@2 { | |
| 1619 | reg = <2>; | |
| 1620 | remote-endpoint = <&csi40vin3>; | |
| 1621 | }; | |
| 1622 | }; | |
| 1623 | }; | |
| f51746ad GU |
1624 | }; |
| 1625 | ||
| 1626 | vin4: video@e6ef4000 { | |
| c7b22b50 | 1627 | compatible = "renesas,vin-r8a77961"; |
| f51746ad | 1628 | reg = <0 0xe6ef4000 0 0x1000>; |
| c7b22b50 NS |
1629 | interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
| 1630 | clocks = <&cpg CPG_MOD 807>; | |
| 1631 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1632 | resets = <&cpg 807>; | |
| 1633 | renesas,id = <4>; | |
| 1634 | status = "disabled"; | |
| 1635 | ||
| 1636 | ports { | |
| 1637 | #address-cells = <1>; | |
| 1638 | #size-cells = <0>; | |
| 1639 | ||
| 1640 | port@1 { | |
| 1641 | #address-cells = <1>; | |
| 1642 | #size-cells = <0>; | |
| 1643 | ||
| 1644 | reg = <1>; | |
| 1645 | ||
| 1646 | vin4csi20: endpoint@0 { | |
| 1647 | reg = <0>; | |
| 1648 | remote-endpoint = <&csi20vin4>; | |
| 1649 | }; | |
| 1650 | vin4csi40: endpoint@2 { | |
| 1651 | reg = <2>; | |
| 1652 | remote-endpoint = <&csi40vin4>; | |
| 1653 | }; | |
| 1654 | }; | |
| 1655 | }; | |
| f51746ad GU |
1656 | }; |
| 1657 | ||
| 1658 | vin5: video@e6ef5000 { | |
| c7b22b50 | 1659 | compatible = "renesas,vin-r8a77961"; |
| f51746ad | 1660 | reg = <0 0xe6ef5000 0 0x1000>; |
| c7b22b50 NS |
1661 | interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; |
| 1662 | clocks = <&cpg CPG_MOD 806>; | |
| 1663 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1664 | resets = <&cpg 806>; | |
| 1665 | renesas,id = <5>; | |
| 1666 | status = "disabled"; | |
| 1667 | ||
| 1668 | ports { | |
| 1669 | #address-cells = <1>; | |
| 1670 | #size-cells = <0>; | |
| 1671 | ||
| 1672 | port@1 { | |
| 1673 | #address-cells = <1>; | |
| 1674 | #size-cells = <0>; | |
| 1675 | ||
| 1676 | reg = <1>; | |
| 1677 | ||
| 1678 | vin5csi20: endpoint@0 { | |
| 1679 | reg = <0>; | |
| 1680 | remote-endpoint = <&csi20vin5>; | |
| 1681 | }; | |
| 1682 | vin5csi40: endpoint@2 { | |
| 1683 | reg = <2>; | |
| 1684 | remote-endpoint = <&csi40vin5>; | |
| 1685 | }; | |
| 1686 | }; | |
| 1687 | }; | |
| f51746ad GU |
1688 | }; |
| 1689 | ||
| 1690 | vin6: video@e6ef6000 { | |
| c7b22b50 | 1691 | compatible = "renesas,vin-r8a77961"; |
| f51746ad | 1692 | reg = <0 0xe6ef6000 0 0x1000>; |
| c7b22b50 NS |
1693 | interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; |
| 1694 | clocks = <&cpg CPG_MOD 805>; | |
| 1695 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1696 | resets = <&cpg 805>; | |
| 1697 | renesas,id = <6>; | |
| 1698 | status = "disabled"; | |
| 1699 | ||
| 1700 | ports { | |
| 1701 | #address-cells = <1>; | |
| 1702 | #size-cells = <0>; | |
| 1703 | ||
| 1704 | port@1 { | |
| 1705 | #address-cells = <1>; | |
| 1706 | #size-cells = <0>; | |
| 1707 | ||
| 1708 | reg = <1>; | |
| 1709 | ||
| 1710 | vin6csi20: endpoint@0 { | |
| 1711 | reg = <0>; | |
| 1712 | remote-endpoint = <&csi20vin6>; | |
| 1713 | }; | |
| 1714 | vin6csi40: endpoint@2 { | |
| 1715 | reg = <2>; | |
| 1716 | remote-endpoint = <&csi40vin6>; | |
| 1717 | }; | |
| 1718 | }; | |
| 1719 | }; | |
| f51746ad GU |
1720 | }; |
| 1721 | ||
| 1722 | vin7: video@e6ef7000 { | |
| c7b22b50 | 1723 | compatible = "renesas,vin-r8a77961"; |
| f51746ad | 1724 | reg = <0 0xe6ef7000 0 0x1000>; |
| c7b22b50 NS |
1725 | interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; |
| 1726 | clocks = <&cpg CPG_MOD 804>; | |
| 1727 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1728 | resets = <&cpg 804>; | |
| 1729 | renesas,id = <7>; | |
| 1730 | status = "disabled"; | |
| 1731 | ||
| 1732 | ports { | |
| 1733 | #address-cells = <1>; | |
| 1734 | #size-cells = <0>; | |
| 1735 | ||
| 1736 | port@1 { | |
| 1737 | #address-cells = <1>; | |
| 1738 | #size-cells = <0>; | |
| 1739 | ||
| 1740 | reg = <1>; | |
| 1741 | ||
| 1742 | vin7csi20: endpoint@0 { | |
| 1743 | reg = <0>; | |
| 1744 | remote-endpoint = <&csi20vin7>; | |
| 1745 | }; | |
| 1746 | vin7csi40: endpoint@2 { | |
| 1747 | reg = <2>; | |
| 1748 | remote-endpoint = <&csi40vin7>; | |
| 1749 | }; | |
| 1750 | }; | |
| 1751 | }; | |
| f51746ad GU |
1752 | }; |
| 1753 | ||
| 1754 | rcar_sound: sound@ec500000 { | |
| bce8ac22 | 1755 | /* |
| 9e72606c | 1756 | * #sound-dai-cells is required if simple-card |
| bce8ac22 KM |
1757 | * |
| 1758 | * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; | |
| 1759 | * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; | |
| 1760 | */ | |
| 1761 | /* | |
| 1762 | * #clock-cells is required for audio_clkout0/1/2/3 | |
| 1763 | * | |
| 1764 | * clkout : #clock-cells = <0>; <&rcar_sound>; | |
| 1765 | * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; | |
| 1766 | */ | |
| 953b392a | 1767 | compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; |
| f51746ad GU |
1768 | reg = <0 0xec500000 0 0x1000>, /* SCU */ |
| 1769 | <0 0xec5a0000 0 0x100>, /* ADG */ | |
| 1770 | <0 0xec540000 0 0x1000>, /* SSIU */ | |
| 1771 | <0 0xec541000 0 0x280>, /* SSI */ | |
| 1772 | <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ | |
| bce8ac22 KM |
1773 | reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; |
| 1774 | ||
| 1775 | clocks = <&cpg CPG_MOD 1005>, | |
| 1776 | <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, | |
| 1777 | <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, | |
| 1778 | <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, | |
| 1779 | <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, | |
| 1780 | <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, | |
| 1781 | <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, | |
| 1782 | <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, | |
| 1783 | <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, | |
| 1784 | <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, | |
| 1785 | <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, | |
| 1786 | <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, | |
| 1787 | <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, | |
| 1788 | <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, | |
| 1789 | <&audio_clk_a>, <&audio_clk_b>, | |
| 1790 | <&audio_clk_c>, | |
| f2802c62 | 1791 | <&cpg CPG_MOD 922>; |
| bce8ac22 KM |
1792 | clock-names = "ssi-all", |
| 1793 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", | |
| 1794 | "ssi.5", "ssi.4", "ssi.3", "ssi.2", | |
| 1795 | "ssi.1", "ssi.0", | |
| 1796 | "src.9", "src.8", "src.7", "src.6", | |
| 1797 | "src.5", "src.4", "src.3", "src.2", | |
| 1798 | "src.1", "src.0", | |
| 1799 | "mix.1", "mix.0", | |
| 1800 | "ctu.1", "ctu.0", | |
| 1801 | "dvc.0", "dvc.1", | |
| 1802 | "clk_a", "clk_b", "clk_c", "clk_i"; | |
| 1803 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 1804 | resets = <&cpg 1005>, | |
| 1805 | <&cpg 1006>, <&cpg 1007>, | |
| 1806 | <&cpg 1008>, <&cpg 1009>, | |
| 1807 | <&cpg 1010>, <&cpg 1011>, | |
| 1808 | <&cpg 1012>, <&cpg 1013>, | |
| 1809 | <&cpg 1014>, <&cpg 1015>; | |
| 1810 | reset-names = "ssi-all", | |
| 1811 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", | |
| 1812 | "ssi.5", "ssi.4", "ssi.3", "ssi.2", | |
| 1813 | "ssi.1", "ssi.0"; | |
| 1814 | status = "disabled"; | |
| 1815 | ||
| 1816 | rcar_sound,ctu { | |
| 1817 | ctu00: ctu-0 { }; | |
| 1818 | ctu01: ctu-1 { }; | |
| 1819 | ctu02: ctu-2 { }; | |
| 1820 | ctu03: ctu-3 { }; | |
| 1821 | ctu10: ctu-4 { }; | |
| 1822 | ctu11: ctu-5 { }; | |
| 1823 | ctu12: ctu-6 { }; | |
| 1824 | ctu13: ctu-7 { }; | |
| 1825 | }; | |
| 1826 | ||
| f51746ad | 1827 | rcar_sound,dvc { |
| bce8ac22 KM |
1828 | dvc0: dvc-0 { |
| 1829 | dmas = <&audma1 0xbc>; | |
| 1830 | dma-names = "tx"; | |
| 1831 | }; | |
| 1832 | dvc1: dvc-1 { | |
| 1833 | dmas = <&audma1 0xbe>; | |
| 1834 | dma-names = "tx"; | |
| 1835 | }; | |
| 1836 | }; | |
| 1837 | ||
| 1838 | rcar_sound,mix { | |
| 1839 | mix0: mix-0 { }; | |
| 1840 | mix1: mix-1 { }; | |
| f51746ad GU |
1841 | }; |
| 1842 | ||
| 1843 | rcar_sound,src { | |
| bce8ac22 KM |
1844 | src0: src-0 { |
| 1845 | interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; | |
| 1846 | dmas = <&audma0 0x85>, <&audma1 0x9a>; | |
| 1847 | dma-names = "rx", "tx"; | |
| 1848 | }; | |
| 1849 | src1: src-1 { | |
| 1850 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; | |
| 1851 | dmas = <&audma0 0x87>, <&audma1 0x9c>; | |
| 1852 | dma-names = "rx", "tx"; | |
| 1853 | }; | |
| 1854 | src2: src-2 { | |
| 1855 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; | |
| 1856 | dmas = <&audma0 0x89>, <&audma1 0x9e>; | |
| 1857 | dma-names = "rx", "tx"; | |
| 1858 | }; | |
| 1859 | src3: src-3 { | |
| 1860 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; | |
| 1861 | dmas = <&audma0 0x8b>, <&audma1 0xa0>; | |
| 1862 | dma-names = "rx", "tx"; | |
| 1863 | }; | |
| 1864 | src4: src-4 { | |
| 1865 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; | |
| 1866 | dmas = <&audma0 0x8d>, <&audma1 0xb0>; | |
| 1867 | dma-names = "rx", "tx"; | |
| 1868 | }; | |
| 1869 | src5: src-5 { | |
| 1870 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; | |
| 1871 | dmas = <&audma0 0x8f>, <&audma1 0xb2>; | |
| 1872 | dma-names = "rx", "tx"; | |
| 1873 | }; | |
| 1874 | src6: src-6 { | |
| 1875 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; | |
| 1876 | dmas = <&audma0 0x91>, <&audma1 0xb4>; | |
| 1877 | dma-names = "rx", "tx"; | |
| 1878 | }; | |
| 1879 | src7: src-7 { | |
| 1880 | interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; | |
| 1881 | dmas = <&audma0 0x93>, <&audma1 0xb6>; | |
| 1882 | dma-names = "rx", "tx"; | |
| 1883 | }; | |
| 1884 | src8: src-8 { | |
| 1885 | interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; | |
| 1886 | dmas = <&audma0 0x95>, <&audma1 0xb8>; | |
| 1887 | dma-names = "rx", "tx"; | |
| 1888 | }; | |
| 1889 | src9: src-9 { | |
| 1890 | interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; | |
| 1891 | dmas = <&audma0 0x97>, <&audma1 0xba>; | |
| 1892 | dma-names = "rx", "tx"; | |
| 1893 | }; | |
| f51746ad GU |
1894 | }; |
| 1895 | ||
| 1896 | rcar_sound,ssi { | |
| bce8ac22 KM |
1897 | ssi0: ssi-0 { |
| 1898 | interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; | |
| 1899 | dmas = <&audma0 0x01>, <&audma1 0x02>; | |
| 1900 | dma-names = "rx", "tx"; | |
| 1901 | }; | |
| 1902 | ssi1: ssi-1 { | |
| 1903 | interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; | |
| 1904 | dmas = <&audma0 0x03>, <&audma1 0x04>; | |
| 1905 | dma-names = "rx", "tx"; | |
| 1906 | }; | |
| 1907 | ssi2: ssi-2 { | |
| 1908 | interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; | |
| 1909 | dmas = <&audma0 0x05>, <&audma1 0x06>; | |
| 1910 | dma-names = "rx", "tx"; | |
| 1911 | }; | |
| 1912 | ssi3: ssi-3 { | |
| 1913 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; | |
| 1914 | dmas = <&audma0 0x07>, <&audma1 0x08>; | |
| 1915 | dma-names = "rx", "tx"; | |
| 1916 | }; | |
| 1917 | ssi4: ssi-4 { | |
| 1918 | interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; | |
| 1919 | dmas = <&audma0 0x09>, <&audma1 0x0a>; | |
| 1920 | dma-names = "rx", "tx"; | |
| 1921 | }; | |
| 1922 | ssi5: ssi-5 { | |
| 1923 | interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; | |
| 1924 | dmas = <&audma0 0x0b>, <&audma1 0x0c>; | |
| 1925 | dma-names = "rx", "tx"; | |
| 1926 | }; | |
| 1927 | ssi6: ssi-6 { | |
| 1928 | interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; | |
| 1929 | dmas = <&audma0 0x0d>, <&audma1 0x0e>; | |
| 1930 | dma-names = "rx", "tx"; | |
| 1931 | }; | |
| 1932 | ssi7: ssi-7 { | |
| 1933 | interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; | |
| 1934 | dmas = <&audma0 0x0f>, <&audma1 0x10>; | |
| 1935 | dma-names = "rx", "tx"; | |
| 1936 | }; | |
| 1937 | ssi8: ssi-8 { | |
| 1938 | interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; | |
| 1939 | dmas = <&audma0 0x11>, <&audma1 0x12>; | |
| 1940 | dma-names = "rx", "tx"; | |
| 1941 | }; | |
| 1942 | ssi9: ssi-9 { | |
| 1943 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; | |
| 1944 | dmas = <&audma0 0x13>, <&audma1 0x14>; | |
| 1945 | dma-names = "rx", "tx"; | |
| 1946 | }; | |
| 1947 | }; | |
| 1948 | ||
| 1949 | rcar_sound,ssiu { | |
| 1950 | ssiu00: ssiu-0 { | |
| 1951 | dmas = <&audma0 0x15>, <&audma1 0x16>; | |
| 1952 | dma-names = "rx", "tx"; | |
| 1953 | }; | |
| 1954 | ssiu01: ssiu-1 { | |
| 1955 | dmas = <&audma0 0x35>, <&audma1 0x36>; | |
| 1956 | dma-names = "rx", "tx"; | |
| 1957 | }; | |
| 1958 | ssiu02: ssiu-2 { | |
| 1959 | dmas = <&audma0 0x37>, <&audma1 0x38>; | |
| 1960 | dma-names = "rx", "tx"; | |
| 1961 | }; | |
| 1962 | ssiu03: ssiu-3 { | |
| 1963 | dmas = <&audma0 0x47>, <&audma1 0x48>; | |
| 1964 | dma-names = "rx", "tx"; | |
| 1965 | }; | |
| 1966 | ssiu04: ssiu-4 { | |
| 1967 | dmas = <&audma0 0x3F>, <&audma1 0x40>; | |
| 1968 | dma-names = "rx", "tx"; | |
| 1969 | }; | |
| 1970 | ssiu05: ssiu-5 { | |
| 1971 | dmas = <&audma0 0x43>, <&audma1 0x44>; | |
| 1972 | dma-names = "rx", "tx"; | |
| 1973 | }; | |
| 1974 | ssiu06: ssiu-6 { | |
| 1975 | dmas = <&audma0 0x4F>, <&audma1 0x50>; | |
| 1976 | dma-names = "rx", "tx"; | |
| 1977 | }; | |
| 1978 | ssiu07: ssiu-7 { | |
| 1979 | dmas = <&audma0 0x53>, <&audma1 0x54>; | |
| 1980 | dma-names = "rx", "tx"; | |
| 1981 | }; | |
| 1982 | ssiu10: ssiu-8 { | |
| 1983 | dmas = <&audma0 0x49>, <&audma1 0x4a>; | |
| 1984 | dma-names = "rx", "tx"; | |
| 1985 | }; | |
| 1986 | ssiu11: ssiu-9 { | |
| 1987 | dmas = <&audma0 0x4B>, <&audma1 0x4C>; | |
| 1988 | dma-names = "rx", "tx"; | |
| 1989 | }; | |
| 1990 | ssiu12: ssiu-10 { | |
| 1991 | dmas = <&audma0 0x57>, <&audma1 0x58>; | |
| 1992 | dma-names = "rx", "tx"; | |
| 1993 | }; | |
| 1994 | ssiu13: ssiu-11 { | |
| 1995 | dmas = <&audma0 0x59>, <&audma1 0x5A>; | |
| 1996 | dma-names = "rx", "tx"; | |
| 1997 | }; | |
| 1998 | ssiu14: ssiu-12 { | |
| 1999 | dmas = <&audma0 0x5F>, <&audma1 0x60>; | |
| 2000 | dma-names = "rx", "tx"; | |
| 2001 | }; | |
| 2002 | ssiu15: ssiu-13 { | |
| 2003 | dmas = <&audma0 0xC3>, <&audma1 0xC4>; | |
| 2004 | dma-names = "rx", "tx"; | |
| 2005 | }; | |
| 2006 | ssiu16: ssiu-14 { | |
| 2007 | dmas = <&audma0 0xC7>, <&audma1 0xC8>; | |
| 2008 | dma-names = "rx", "tx"; | |
| 2009 | }; | |
| 2010 | ssiu17: ssiu-15 { | |
| 2011 | dmas = <&audma0 0xCB>, <&audma1 0xCC>; | |
| 2012 | dma-names = "rx", "tx"; | |
| 2013 | }; | |
| 2014 | ssiu20: ssiu-16 { | |
| 2015 | dmas = <&audma0 0x63>, <&audma1 0x64>; | |
| 2016 | dma-names = "rx", "tx"; | |
| 2017 | }; | |
| 2018 | ssiu21: ssiu-17 { | |
| 2019 | dmas = <&audma0 0x67>, <&audma1 0x68>; | |
| 2020 | dma-names = "rx", "tx"; | |
| 2021 | }; | |
| 2022 | ssiu22: ssiu-18 { | |
| 2023 | dmas = <&audma0 0x6B>, <&audma1 0x6C>; | |
| 2024 | dma-names = "rx", "tx"; | |
| 2025 | }; | |
| 2026 | ssiu23: ssiu-19 { | |
| 2027 | dmas = <&audma0 0x6D>, <&audma1 0x6E>; | |
| 2028 | dma-names = "rx", "tx"; | |
| 2029 | }; | |
| 2030 | ssiu24: ssiu-20 { | |
| 2031 | dmas = <&audma0 0xCF>, <&audma1 0xCE>; | |
| 2032 | dma-names = "rx", "tx"; | |
| 2033 | }; | |
| 2034 | ssiu25: ssiu-21 { | |
| 2035 | dmas = <&audma0 0xEB>, <&audma1 0xEC>; | |
| 2036 | dma-names = "rx", "tx"; | |
| 2037 | }; | |
| 2038 | ssiu26: ssiu-22 { | |
| 2039 | dmas = <&audma0 0xED>, <&audma1 0xEE>; | |
| 2040 | dma-names = "rx", "tx"; | |
| 2041 | }; | |
| 2042 | ssiu27: ssiu-23 { | |
| 2043 | dmas = <&audma0 0xEF>, <&audma1 0xF0>; | |
| 2044 | dma-names = "rx", "tx"; | |
| 2045 | }; | |
| 2046 | ssiu30: ssiu-24 { | |
| 2047 | dmas = <&audma0 0x6f>, <&audma1 0x70>; | |
| 2048 | dma-names = "rx", "tx"; | |
| 2049 | }; | |
| 2050 | ssiu31: ssiu-25 { | |
| 2051 | dmas = <&audma0 0x21>, <&audma1 0x22>; | |
| 2052 | dma-names = "rx", "tx"; | |
| 2053 | }; | |
| 2054 | ssiu32: ssiu-26 { | |
| 2055 | dmas = <&audma0 0x23>, <&audma1 0x24>; | |
| 2056 | dma-names = "rx", "tx"; | |
| 2057 | }; | |
| 2058 | ssiu33: ssiu-27 { | |
| 2059 | dmas = <&audma0 0x25>, <&audma1 0x26>; | |
| 2060 | dma-names = "rx", "tx"; | |
| 2061 | }; | |
| 2062 | ssiu34: ssiu-28 { | |
| 2063 | dmas = <&audma0 0x27>, <&audma1 0x28>; | |
| 2064 | dma-names = "rx", "tx"; | |
| 2065 | }; | |
| 2066 | ssiu35: ssiu-29 { | |
| 2067 | dmas = <&audma0 0x29>, <&audma1 0x2A>; | |
| 2068 | dma-names = "rx", "tx"; | |
| 2069 | }; | |
| 2070 | ssiu36: ssiu-30 { | |
| 2071 | dmas = <&audma0 0x2B>, <&audma1 0x2C>; | |
| 2072 | dma-names = "rx", "tx"; | |
| 2073 | }; | |
| 2074 | ssiu37: ssiu-31 { | |
| 2075 | dmas = <&audma0 0x2D>, <&audma1 0x2E>; | |
| 2076 | dma-names = "rx", "tx"; | |
| 2077 | }; | |
| 2078 | ssiu40: ssiu-32 { | |
| 953b392a | 2079 | dmas = <&audma0 0x71>, <&audma1 0x72>; |
| bce8ac22 KM |
2080 | dma-names = "rx", "tx"; |
| 2081 | }; | |
| 2082 | ssiu41: ssiu-33 { | |
| 2083 | dmas = <&audma0 0x17>, <&audma1 0x18>; | |
| 2084 | dma-names = "rx", "tx"; | |
| 2085 | }; | |
| 2086 | ssiu42: ssiu-34 { | |
| 2087 | dmas = <&audma0 0x19>, <&audma1 0x1A>; | |
| 2088 | dma-names = "rx", "tx"; | |
| 2089 | }; | |
| 2090 | ssiu43: ssiu-35 { | |
| 2091 | dmas = <&audma0 0x1B>, <&audma1 0x1C>; | |
| 2092 | dma-names = "rx", "tx"; | |
| 2093 | }; | |
| 2094 | ssiu44: ssiu-36 { | |
| 2095 | dmas = <&audma0 0x1D>, <&audma1 0x1E>; | |
| 2096 | dma-names = "rx", "tx"; | |
| 2097 | }; | |
| 2098 | ssiu45: ssiu-37 { | |
| 2099 | dmas = <&audma0 0x1F>, <&audma1 0x20>; | |
| 2100 | dma-names = "rx", "tx"; | |
| 2101 | }; | |
| 2102 | ssiu46: ssiu-38 { | |
| 2103 | dmas = <&audma0 0x31>, <&audma1 0x32>; | |
| 2104 | dma-names = "rx", "tx"; | |
| 2105 | }; | |
| 2106 | ssiu47: ssiu-39 { | |
| 2107 | dmas = <&audma0 0x33>, <&audma1 0x34>; | |
| 2108 | dma-names = "rx", "tx"; | |
| 2109 | }; | |
| 2110 | ssiu50: ssiu-40 { | |
| 2111 | dmas = <&audma0 0x73>, <&audma1 0x74>; | |
| 2112 | dma-names = "rx", "tx"; | |
| 2113 | }; | |
| 2114 | ssiu60: ssiu-41 { | |
| 2115 | dmas = <&audma0 0x75>, <&audma1 0x76>; | |
| 2116 | dma-names = "rx", "tx"; | |
| 2117 | }; | |
| 2118 | ssiu70: ssiu-42 { | |
| 2119 | dmas = <&audma0 0x79>, <&audma1 0x7a>; | |
| 2120 | dma-names = "rx", "tx"; | |
| 2121 | }; | |
| 2122 | ssiu80: ssiu-43 { | |
| 2123 | dmas = <&audma0 0x7b>, <&audma1 0x7c>; | |
| 2124 | dma-names = "rx", "tx"; | |
| 2125 | }; | |
| 2126 | ssiu90: ssiu-44 { | |
| 2127 | dmas = <&audma0 0x7d>, <&audma1 0x7e>; | |
| 2128 | dma-names = "rx", "tx"; | |
| 2129 | }; | |
| 2130 | ssiu91: ssiu-45 { | |
| 2131 | dmas = <&audma0 0x7F>, <&audma1 0x80>; | |
| 2132 | dma-names = "rx", "tx"; | |
| 2133 | }; | |
| 2134 | ssiu92: ssiu-46 { | |
| 2135 | dmas = <&audma0 0x81>, <&audma1 0x82>; | |
| 2136 | dma-names = "rx", "tx"; | |
| 2137 | }; | |
| 2138 | ssiu93: ssiu-47 { | |
| 2139 | dmas = <&audma0 0x83>, <&audma1 0x84>; | |
| 2140 | dma-names = "rx", "tx"; | |
| 2141 | }; | |
| 2142 | ssiu94: ssiu-48 { | |
| 2143 | dmas = <&audma0 0xA3>, <&audma1 0xA4>; | |
| 2144 | dma-names = "rx", "tx"; | |
| 2145 | }; | |
| 2146 | ssiu95: ssiu-49 { | |
| 2147 | dmas = <&audma0 0xA5>, <&audma1 0xA6>; | |
| 2148 | dma-names = "rx", "tx"; | |
| 2149 | }; | |
| 2150 | ssiu96: ssiu-50 { | |
| 2151 | dmas = <&audma0 0xA7>, <&audma1 0xA8>; | |
| 2152 | dma-names = "rx", "tx"; | |
| 2153 | }; | |
| 2154 | ssiu97: ssiu-51 { | |
| 2155 | dmas = <&audma0 0xA9>, <&audma1 0xAA>; | |
| 2156 | dma-names = "rx", "tx"; | |
| 2157 | }; | |
| f51746ad GU |
2158 | }; |
| 2159 | }; | |
| 2160 | ||
| fb912a1b NY |
2161 | mlp: mlp@ec520000 { |
| 2162 | compatible = "renesas,r8a77961-mlp", | |
| 2163 | "renesas,rcar-gen3-mlp"; | |
| 2164 | reg = <0 0xec520000 0 0x800>; | |
| 2165 | interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, | |
| 2166 | <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>; | |
| 2167 | clocks = <&cpg CPG_MOD 802>; | |
| 2168 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2169 | resets = <&cpg 802>; | |
| 2170 | status = "disabled"; | |
| 2171 | }; | |
| 2172 | ||
| bce8ac22 KM |
2173 | audma0: dma-controller@ec700000 { |
| 2174 | compatible = "renesas,dmac-r8a77961", | |
| 2175 | "renesas,rcar-dmac"; | |
| 2176 | reg = <0 0xec700000 0 0x10000>; | |
| 2177 | interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, | |
| 2178 | <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, | |
| 2179 | <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, | |
| 2180 | <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, | |
| 2181 | <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, | |
| 2182 | <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, | |
| 2183 | <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, | |
| 2184 | <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, | |
| 2185 | <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, | |
| 2186 | <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, | |
| 2187 | <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, | |
| 2188 | <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, | |
| 2189 | <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, | |
| 2190 | <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, | |
| 2191 | <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, | |
| 2192 | <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, | |
| 2193 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; | |
| 2194 | interrupt-names = "error", | |
| 2195 | "ch0", "ch1", "ch2", "ch3", | |
| 2196 | "ch4", "ch5", "ch6", "ch7", | |
| 2197 | "ch8", "ch9", "ch10", "ch11", | |
| 2198 | "ch12", "ch13", "ch14", "ch15"; | |
| 2199 | clocks = <&cpg CPG_MOD 502>; | |
| 2200 | clock-names = "fck"; | |
| 2201 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2202 | resets = <&cpg 502>; | |
| 2203 | #dma-cells = <1>; | |
| 2204 | dma-channels = <16>; | |
| 2205 | iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, | |
| 2206 | <&ipmmu_mp 2>, <&ipmmu_mp 3>, | |
| 2207 | <&ipmmu_mp 4>, <&ipmmu_mp 5>, | |
| 2208 | <&ipmmu_mp 6>, <&ipmmu_mp 7>, | |
| 2209 | <&ipmmu_mp 8>, <&ipmmu_mp 9>, | |
| 2210 | <&ipmmu_mp 10>, <&ipmmu_mp 11>, | |
| 2211 | <&ipmmu_mp 12>, <&ipmmu_mp 13>, | |
| 2212 | <&ipmmu_mp 14>, <&ipmmu_mp 15>; | |
| 2213 | }; | |
| 2214 | ||
| 2215 | audma1: dma-controller@ec720000 { | |
| 2216 | compatible = "renesas,dmac-r8a77961", | |
| 2217 | "renesas,rcar-dmac"; | |
| 2218 | reg = <0 0xec720000 0 0x10000>; | |
| 2219 | interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, | |
| 2220 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, | |
| 2221 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, | |
| 2222 | <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, | |
| 2223 | <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, | |
| 2224 | <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, | |
| 2225 | <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, | |
| 2226 | <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, | |
| 2227 | <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, | |
| 2228 | <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, | |
| 2229 | <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, | |
| 2230 | <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, | |
| 2231 | <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, | |
| 2232 | <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, | |
| 2233 | <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, | |
| 2234 | <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, | |
| 2235 | <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; | |
| 2236 | interrupt-names = "error", | |
| 2237 | "ch0", "ch1", "ch2", "ch3", | |
| 2238 | "ch4", "ch5", "ch6", "ch7", | |
| 2239 | "ch8", "ch9", "ch10", "ch11", | |
| 2240 | "ch12", "ch13", "ch14", "ch15"; | |
| 2241 | clocks = <&cpg CPG_MOD 501>; | |
| 2242 | clock-names = "fck"; | |
| 2243 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2244 | resets = <&cpg 501>; | |
| 2245 | #dma-cells = <1>; | |
| 2246 | dma-channels = <16>; | |
| 2247 | iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, | |
| 2248 | <&ipmmu_mp 18>, <&ipmmu_mp 19>, | |
| 2249 | <&ipmmu_mp 20>, <&ipmmu_mp 21>, | |
| 2250 | <&ipmmu_mp 22>, <&ipmmu_mp 23>, | |
| 2251 | <&ipmmu_mp 24>, <&ipmmu_mp 25>, | |
| 2252 | <&ipmmu_mp 26>, <&ipmmu_mp 27>, | |
| 2253 | <&ipmmu_mp 28>, <&ipmmu_mp 29>, | |
| 2254 | <&ipmmu_mp 30>, <&ipmmu_mp 31>; | |
| 2255 | }; | |
| 2256 | ||
| f51746ad | 2257 | xhci0: usb@ee000000 { |
| 8ab47ffc YS |
2258 | compatible = "renesas,xhci-r8a77961", |
| 2259 | "renesas,rcar-gen3-xhci"; | |
| f51746ad | 2260 | reg = <0 0xee000000 0 0xc00>; |
| 8ab47ffc YS |
2261 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| 2262 | clocks = <&cpg CPG_MOD 328>; | |
| 2263 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2264 | resets = <&cpg 328>; | |
| 2265 | status = "disabled"; | |
| f51746ad GU |
2266 | }; |
| 2267 | ||
| 2268 | usb3_peri0: usb@ee020000 { | |
| 8ab47ffc YS |
2269 | compatible = "renesas,r8a77961-usb3-peri", |
| 2270 | "renesas,rcar-gen3-usb3-peri"; | |
| f51746ad | 2271 | reg = <0 0xee020000 0 0x400>; |
| 8ab47ffc YS |
2272 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; |
| 2273 | clocks = <&cpg CPG_MOD 328>; | |
| 2274 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2275 | resets = <&cpg 328>; | |
| 2276 | status = "disabled"; | |
| f51746ad GU |
2277 | }; |
| 2278 | ||
| 2279 | ohci0: usb@ee080000 { | |
| 667fd76f | 2280 | compatible = "generic-ohci"; |
| f51746ad | 2281 | reg = <0 0xee080000 0 0x100>; |
| 667fd76f YS |
2282 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| 2283 | clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; | |
| 2284 | phys = <&usb2_phy0 1>; | |
| 2285 | phy-names = "usb"; | |
| 2286 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2287 | resets = <&cpg 703>, <&cpg 704>; | |
| 2288 | status = "disabled"; | |
| f51746ad GU |
2289 | }; |
| 2290 | ||
| 2291 | ohci1: usb@ee0a0000 { | |
| 667fd76f | 2292 | compatible = "generic-ohci"; |
| f51746ad | 2293 | reg = <0 0xee0a0000 0 0x100>; |
| 667fd76f YS |
2294 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| 2295 | clocks = <&cpg CPG_MOD 702>; | |
| 2296 | phys = <&usb2_phy1 1>; | |
| 2297 | phy-names = "usb"; | |
| 2298 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2299 | resets = <&cpg 702>; | |
| 2300 | status = "disabled"; | |
| f51746ad GU |
2301 | }; |
| 2302 | ||
| 2303 | ehci0: usb@ee080100 { | |
| 667fd76f | 2304 | compatible = "generic-ehci"; |
| f51746ad | 2305 | reg = <0 0xee080100 0 0x100>; |
| 667fd76f YS |
2306 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| 2307 | clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; | |
| 2308 | phys = <&usb2_phy0 2>; | |
| 2309 | phy-names = "usb"; | |
| 2310 | companion = <&ohci0>; | |
| 2311 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2312 | resets = <&cpg 703>, <&cpg 704>; | |
| 2313 | status = "disabled"; | |
| f51746ad GU |
2314 | }; |
| 2315 | ||
| 2316 | ehci1: usb@ee0a0100 { | |
| 667fd76f | 2317 | compatible = "generic-ehci"; |
| f51746ad | 2318 | reg = <0 0xee0a0100 0 0x100>; |
| 667fd76f YS |
2319 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| 2320 | clocks = <&cpg CPG_MOD 702>; | |
| 2321 | phys = <&usb2_phy1 2>; | |
| 2322 | phy-names = "usb"; | |
| 2323 | companion = <&ohci1>; | |
| 2324 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2325 | resets = <&cpg 702>; | |
| 2326 | status = "disabled"; | |
| f51746ad GU |
2327 | }; |
| 2328 | ||
| 2329 | usb2_phy0: usb-phy@ee080200 { | |
| 667fd76f YS |
2330 | compatible = "renesas,usb2-phy-r8a77961", |
| 2331 | "renesas,rcar-gen3-usb2-phy"; | |
| f51746ad | 2332 | reg = <0 0xee080200 0 0x700>; |
| 667fd76f YS |
2333 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| 2334 | clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; | |
| 2335 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2336 | resets = <&cpg 703>, <&cpg 704>; | |
| 2337 | #phy-cells = <1>; | |
| 2338 | status = "disabled"; | |
| f51746ad GU |
2339 | }; |
| 2340 | ||
| 2341 | usb2_phy1: usb-phy@ee0a0200 { | |
| 667fd76f YS |
2342 | compatible = "renesas,usb2-phy-r8a77961", |
| 2343 | "renesas,rcar-gen3-usb2-phy"; | |
| f51746ad | 2344 | reg = <0 0xee0a0200 0 0x700>; |
| 667fd76f YS |
2345 | clocks = <&cpg CPG_MOD 702>; |
| 2346 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2347 | resets = <&cpg 702>; | |
| 2348 | #phy-cells = <1>; | |
| 2349 | status = "disabled"; | |
| f51746ad GU |
2350 | }; |
| 2351 | ||
| a6cb262a | 2352 | sdhi0: mmc@ee100000 { |
| 111cc9ac GU |
2353 | compatible = "renesas,sdhi-r8a77961", |
| 2354 | "renesas,rcar-gen3-sdhi"; | |
| f51746ad | 2355 | reg = <0 0xee100000 0 0x2000>; |
| 111cc9ac | 2356 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; |
| eca6ab6e WS |
2357 | clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77961_CLK_SD0H>; |
| 2358 | clock-names = "core", "clkh"; | |
| 111cc9ac GU |
2359 | max-frequency = <200000000>; |
| 2360 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2361 | resets = <&cpg 314>; | |
| 651f8cff | 2362 | iommus = <&ipmmu_ds1 32>; |
| 111cc9ac GU |
2363 | status = "disabled"; |
| 2364 | }; | |
| 2365 | ||
| a6cb262a | 2366 | sdhi1: mmc@ee120000 { |
| 111cc9ac GU |
2367 | compatible = "renesas,sdhi-r8a77961", |
| 2368 | "renesas,rcar-gen3-sdhi"; | |
| 2369 | reg = <0 0xee120000 0 0x2000>; | |
| 2370 | interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; | |
| eca6ab6e WS |
2371 | clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77961_CLK_SD1H>; |
| 2372 | clock-names = "core", "clkh"; | |
| 111cc9ac GU |
2373 | max-frequency = <200000000>; |
| 2374 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2375 | resets = <&cpg 313>; | |
| 651f8cff | 2376 | iommus = <&ipmmu_ds1 33>; |
| 111cc9ac | 2377 | status = "disabled"; |
| f51746ad GU |
2378 | }; |
| 2379 | ||
| a6cb262a | 2380 | sdhi2: mmc@ee140000 { |
| 111cc9ac GU |
2381 | compatible = "renesas,sdhi-r8a77961", |
| 2382 | "renesas,rcar-gen3-sdhi"; | |
| f51746ad | 2383 | reg = <0 0xee140000 0 0x2000>; |
| 111cc9ac | 2384 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; |
| eca6ab6e WS |
2385 | clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77961_CLK_SD2H>; |
| 2386 | clock-names = "core", "clkh"; | |
| 111cc9ac GU |
2387 | max-frequency = <200000000>; |
| 2388 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2389 | resets = <&cpg 312>; | |
| 651f8cff | 2390 | iommus = <&ipmmu_ds1 34>; |
| 111cc9ac | 2391 | status = "disabled"; |
| f51746ad GU |
2392 | }; |
| 2393 | ||
| a6cb262a | 2394 | sdhi3: mmc@ee160000 { |
| 111cc9ac GU |
2395 | compatible = "renesas,sdhi-r8a77961", |
| 2396 | "renesas,rcar-gen3-sdhi"; | |
| f51746ad | 2397 | reg = <0 0xee160000 0 0x2000>; |
| 111cc9ac | 2398 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
| eca6ab6e WS |
2399 | clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77961_CLK_SD3H>; |
| 2400 | clock-names = "core", "clkh"; | |
| 111cc9ac GU |
2401 | max-frequency = <200000000>; |
| 2402 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2403 | resets = <&cpg 311>; | |
| 651f8cff | 2404 | iommus = <&ipmmu_ds1 35>; |
| 111cc9ac | 2405 | status = "disabled"; |
| f51746ad GU |
2406 | }; |
| 2407 | ||
| f191fba7 GU |
2408 | rpc: spi@ee200000 { |
| 2409 | compatible = "renesas,r8a77961-rpc-if", | |
| 2410 | "renesas,rcar-gen3-rpc-if"; | |
| 2411 | reg = <0 0xee200000 0 0x200>, | |
| 2412 | <0 0x08000000 0 0x04000000>, | |
| 2413 | <0 0xee208000 0 0x100>; | |
| 2414 | reg-names = "regs", "dirmap", "wbuf"; | |
| 2415 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
| 2416 | clocks = <&cpg CPG_MOD 917>; | |
| 2417 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2418 | resets = <&cpg 917>; | |
| 2419 | #address-cells = <1>; | |
| 2420 | #size-cells = <0>; | |
| 2421 | status = "disabled"; | |
| 2422 | }; | |
| 2423 | ||
| f51746ad GU |
2424 | gic: interrupt-controller@f1010000 { |
| 2425 | compatible = "arm,gic-400"; | |
| 2426 | #interrupt-cells = <3>; | |
| 2427 | #address-cells = <0>; | |
| 2428 | interrupt-controller; | |
| 2429 | reg = <0x0 0xf1010000 0 0x1000>, | |
| 2430 | <0x0 0xf1020000 0 0x20000>, | |
| 2431 | <0x0 0xf1040000 0 0x20000>, | |
| 2432 | <0x0 0xf1060000 0 0x20000>; | |
| 2433 | interrupts = <GIC_PPI 9 | |
| 2434 | (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; | |
| 2435 | clocks = <&cpg CPG_MOD 408>; | |
| 2436 | clock-names = "clk"; | |
| 2437 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2438 | resets = <&cpg 408>; | |
| 2439 | }; | |
| 2440 | ||
| 2441 | pciec0: pcie@fe000000 { | |
| 76e6c82c YS |
2442 | compatible = "renesas,pcie-r8a77961", |
| 2443 | "renesas,pcie-rcar-gen3"; | |
| f51746ad | 2444 | reg = <0 0xfe000000 0 0x80000>; |
| 76e6c82c YS |
2445 | #address-cells = <3>; |
| 2446 | #size-cells = <2>; | |
| 2447 | bus-range = <0x00 0xff>; | |
| 2448 | device_type = "pci"; | |
| 2449 | ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, | |
| 2450 | <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, | |
| 2451 | <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, | |
| 2452 | <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; | |
| 86d904b6 YS |
2453 | /* Map all possible DDR/IOMMU as inbound ranges */ |
| 2454 | dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; | |
| 76e6c82c YS |
2455 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 2456 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
| 2457 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; | |
| 2458 | #interrupt-cells = <1>; | |
| 2459 | interrupt-map-mask = <0 0 0 0>; | |
| 2460 | interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
| 2461 | clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; | |
| 2462 | clock-names = "pcie", "pcie_bus"; | |
| 2463 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2464 | resets = <&cpg 319>; | |
| 86d904b6 YS |
2465 | iommu-map = <0 &ipmmu_hc 0 1>; |
| 2466 | iommu-map-mask = <0>; | |
| 76e6c82c | 2467 | status = "disabled"; |
| f51746ad GU |
2468 | }; |
| 2469 | ||
| 2470 | pciec1: pcie@ee800000 { | |
| 76e6c82c YS |
2471 | compatible = "renesas,pcie-r8a77961", |
| 2472 | "renesas,pcie-rcar-gen3"; | |
| f51746ad | 2473 | reg = <0 0xee800000 0 0x80000>; |
| 76e6c82c YS |
2474 | #address-cells = <3>; |
| 2475 | #size-cells = <2>; | |
| 2476 | bus-range = <0x00 0xff>; | |
| 2477 | device_type = "pci"; | |
| 2478 | ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, | |
| 2479 | <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, | |
| 2480 | <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, | |
| 2481 | <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; | |
| 86d904b6 YS |
2482 | /* Map all possible DDR/IOMMU as inbound ranges */ |
| 2483 | dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; | |
| 76e6c82c YS |
2484 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, |
| 2485 | <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, | |
| 2486 | <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; | |
| 2487 | #interrupt-cells = <1>; | |
| 2488 | interrupt-map-mask = <0 0 0 0>; | |
| 2489 | interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; | |
| 2490 | clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; | |
| 2491 | clock-names = "pcie", "pcie_bus"; | |
| 2492 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2493 | resets = <&cpg 318>; | |
| 86d904b6 YS |
2494 | iommu-map = <0 &ipmmu_hc 1 1>; |
| 2495 | iommu-map-mask = <0>; | |
| 76e6c82c | 2496 | status = "disabled"; |
| f51746ad GU |
2497 | }; |
| 2498 | ||
| 9ab84704 KM |
2499 | fcpf0: fcp@fe950000 { |
| 2500 | compatible = "renesas,fcpf"; | |
| 2501 | reg = <0 0xfe950000 0 0x200>; | |
| 2502 | clocks = <&cpg CPG_MOD 615>; | |
| 2503 | power-domains = <&sysc R8A77961_PD_A3VC>; | |
| 2504 | resets = <&cpg 615>; | |
| 2505 | }; | |
| 2506 | ||
| 2507 | fcpvb0: fcp@fe96f000 { | |
| 2508 | compatible = "renesas,fcpv"; | |
| 2509 | reg = <0 0xfe96f000 0 0x200>; | |
| 2510 | clocks = <&cpg CPG_MOD 607>; | |
| 2511 | power-domains = <&sysc R8A77961_PD_A3VC>; | |
| 2512 | resets = <&cpg 607>; | |
| 2513 | }; | |
| 2514 | ||
| 2515 | fcpvi0: fcp@fe9af000 { | |
| 2516 | compatible = "renesas,fcpv"; | |
| 2517 | reg = <0 0xfe9af000 0 0x200>; | |
| 2518 | clocks = <&cpg CPG_MOD 611>; | |
| 2519 | power-domains = <&sysc R8A77961_PD_A3VC>; | |
| 2520 | resets = <&cpg 611>; | |
| 2521 | iommus = <&ipmmu_vc0 19>; | |
| 2522 | }; | |
| 2523 | ||
| 2524 | fcpvd0: fcp@fea27000 { | |
| 2525 | compatible = "renesas,fcpv"; | |
| 2526 | reg = <0 0xfea27000 0 0x200>; | |
| 2527 | clocks = <&cpg CPG_MOD 603>; | |
| 2528 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2529 | resets = <&cpg 603>; | |
| 2530 | iommus = <&ipmmu_vi0 8>; | |
| 2531 | }; | |
| 2532 | ||
| 2533 | fcpvd1: fcp@fea2f000 { | |
| 2534 | compatible = "renesas,fcpv"; | |
| 2535 | reg = <0 0xfea2f000 0 0x200>; | |
| 2536 | clocks = <&cpg CPG_MOD 602>; | |
| 2537 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2538 | resets = <&cpg 602>; | |
| 2539 | iommus = <&ipmmu_vi0 9>; | |
| 2540 | }; | |
| 2541 | ||
| 2542 | fcpvd2: fcp@fea37000 { | |
| 2543 | compatible = "renesas,fcpv"; | |
| 2544 | reg = <0 0xfea37000 0 0x200>; | |
| 2545 | clocks = <&cpg CPG_MOD 601>; | |
| 2546 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2547 | resets = <&cpg 601>; | |
| 2548 | iommus = <&ipmmu_vi0 10>; | |
| 2549 | }; | |
| 2550 | ||
| 298b0c8b KM |
2551 | vspb: vsp@fe960000 { |
| 2552 | compatible = "renesas,vsp2"; | |
| 2553 | reg = <0 0xfe960000 0 0x8000>; | |
| 2554 | interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; | |
| 2555 | clocks = <&cpg CPG_MOD 626>; | |
| 2556 | power-domains = <&sysc R8A77961_PD_A3VC>; | |
| 2557 | resets = <&cpg 626>; | |
| 2558 | ||
| 2559 | renesas,fcp = <&fcpvb0>; | |
| 2560 | }; | |
| 2561 | ||
| 2562 | vspd0: vsp@fea20000 { | |
| 2563 | compatible = "renesas,vsp2"; | |
| 2564 | reg = <0 0xfea20000 0 0x5000>; | |
| 2565 | interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; | |
| 2566 | clocks = <&cpg CPG_MOD 623>; | |
| 2567 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2568 | resets = <&cpg 623>; | |
| 2569 | ||
| 2570 | renesas,fcp = <&fcpvd0>; | |
| 2571 | }; | |
| 2572 | ||
| 2573 | vspd1: vsp@fea28000 { | |
| 2574 | compatible = "renesas,vsp2"; | |
| 2575 | reg = <0 0xfea28000 0 0x5000>; | |
| 2576 | interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; | |
| 2577 | clocks = <&cpg CPG_MOD 622>; | |
| 2578 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2579 | resets = <&cpg 622>; | |
| 2580 | ||
| 2581 | renesas,fcp = <&fcpvd1>; | |
| 2582 | }; | |
| 2583 | ||
| 2584 | vspd2: vsp@fea30000 { | |
| 2585 | compatible = "renesas,vsp2"; | |
| 2586 | reg = <0 0xfea30000 0 0x5000>; | |
| 2587 | interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; | |
| 2588 | clocks = <&cpg CPG_MOD 621>; | |
| 2589 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2590 | resets = <&cpg 621>; | |
| 2591 | ||
| 2592 | renesas,fcp = <&fcpvd2>; | |
| 2593 | }; | |
| 2594 | ||
| 2595 | vspi0: vsp@fe9a0000 { | |
| 2596 | compatible = "renesas,vsp2"; | |
| 2597 | reg = <0 0xfe9a0000 0 0x8000>; | |
| 2598 | interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; | |
| 2599 | clocks = <&cpg CPG_MOD 631>; | |
| 2600 | power-domains = <&sysc R8A77961_PD_A3VC>; | |
| 2601 | resets = <&cpg 631>; | |
| 2602 | ||
| 2603 | renesas,fcp = <&fcpvi0>; | |
| 2604 | }; | |
| 2605 | ||
| f51746ad | 2606 | csi20: csi2@fea80000 { |
| c7b22b50 | 2607 | compatible = "renesas,r8a77961-csi2"; |
| f51746ad | 2608 | reg = <0 0xfea80000 0 0x10000>; |
| c7b22b50 NS |
2609 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
| 2610 | clocks = <&cpg CPG_MOD 714>; | |
| 2611 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2612 | resets = <&cpg 714>; | |
| 2613 | status = "disabled"; | |
| f51746ad GU |
2614 | |
| 2615 | ports { | |
| 2616 | #address-cells = <1>; | |
| 2617 | #size-cells = <0>; | |
| 2618 | ||
| 0a96c059 NS |
2619 | port@0 { |
| 2620 | reg = <0>; | |
| 2621 | }; | |
| 2622 | ||
| f51746ad GU |
2623 | port@1 { |
| 2624 | #address-cells = <1>; | |
| 2625 | #size-cells = <0>; | |
| c7b22b50 | 2626 | |
| f51746ad | 2627 | reg = <1>; |
| c7b22b50 NS |
2628 | |
| 2629 | csi20vin0: endpoint@0 { | |
| 2630 | reg = <0>; | |
| 2631 | remote-endpoint = <&vin0csi20>; | |
| 2632 | }; | |
| 2633 | csi20vin1: endpoint@1 { | |
| 2634 | reg = <1>; | |
| 2635 | remote-endpoint = <&vin1csi20>; | |
| 2636 | }; | |
| 2637 | csi20vin2: endpoint@2 { | |
| 2638 | reg = <2>; | |
| 2639 | remote-endpoint = <&vin2csi20>; | |
| 2640 | }; | |
| 2641 | csi20vin3: endpoint@3 { | |
| 2642 | reg = <3>; | |
| 2643 | remote-endpoint = <&vin3csi20>; | |
| 2644 | }; | |
| 2645 | csi20vin4: endpoint@4 { | |
| 2646 | reg = <4>; | |
| 2647 | remote-endpoint = <&vin4csi20>; | |
| 2648 | }; | |
| 2649 | csi20vin5: endpoint@5 { | |
| 2650 | reg = <5>; | |
| 2651 | remote-endpoint = <&vin5csi20>; | |
| 2652 | }; | |
| 2653 | csi20vin6: endpoint@6 { | |
| 2654 | reg = <6>; | |
| 2655 | remote-endpoint = <&vin6csi20>; | |
| 2656 | }; | |
| 2657 | csi20vin7: endpoint@7 { | |
| 2658 | reg = <7>; | |
| 2659 | remote-endpoint = <&vin7csi20>; | |
| 2660 | }; | |
| f51746ad GU |
2661 | }; |
| 2662 | }; | |
| 2663 | }; | |
| 2664 | ||
| 2665 | csi40: csi2@feaa0000 { | |
| c7b22b50 | 2666 | compatible = "renesas,r8a77961-csi2"; |
| f51746ad | 2667 | reg = <0 0xfeaa0000 0 0x10000>; |
| c7b22b50 NS |
2668 | interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; |
| 2669 | clocks = <&cpg CPG_MOD 716>; | |
| 2670 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2671 | resets = <&cpg 716>; | |
| 2672 | status = "disabled"; | |
| f51746ad GU |
2673 | |
| 2674 | ports { | |
| 2675 | #address-cells = <1>; | |
| 2676 | #size-cells = <0>; | |
| 2677 | ||
| 0a96c059 NS |
2678 | port@0 { |
| 2679 | reg = <0>; | |
| 2680 | }; | |
| 2681 | ||
| f51746ad GU |
2682 | port@1 { |
| 2683 | #address-cells = <1>; | |
| 2684 | #size-cells = <0>; | |
| 2685 | ||
| 2686 | reg = <1>; | |
| c7b22b50 NS |
2687 | |
| 2688 | csi40vin0: endpoint@0 { | |
| 2689 | reg = <0>; | |
| 2690 | remote-endpoint = <&vin0csi40>; | |
| 2691 | }; | |
| 2692 | csi40vin1: endpoint@1 { | |
| 2693 | reg = <1>; | |
| 2694 | remote-endpoint = <&vin1csi40>; | |
| 2695 | }; | |
| 2696 | csi40vin2: endpoint@2 { | |
| 2697 | reg = <2>; | |
| 2698 | remote-endpoint = <&vin2csi40>; | |
| 2699 | }; | |
| 2700 | csi40vin3: endpoint@3 { | |
| 2701 | reg = <3>; | |
| 2702 | remote-endpoint = <&vin3csi40>; | |
| 2703 | }; | |
| 2704 | csi40vin4: endpoint@4 { | |
| 2705 | reg = <4>; | |
| 2706 | remote-endpoint = <&vin4csi40>; | |
| 2707 | }; | |
| 2708 | csi40vin5: endpoint@5 { | |
| 2709 | reg = <5>; | |
| 2710 | remote-endpoint = <&vin5csi40>; | |
| 2711 | }; | |
| 2712 | csi40vin6: endpoint@6 { | |
| 2713 | reg = <6>; | |
| 2714 | remote-endpoint = <&vin6csi40>; | |
| 2715 | }; | |
| 2716 | csi40vin7: endpoint@7 { | |
| 2717 | reg = <7>; | |
| 2718 | remote-endpoint = <&vin7csi40>; | |
| 2719 | }; | |
| f51746ad | 2720 | }; |
| c7b22b50 | 2721 | |
| f51746ad GU |
2722 | }; |
| 2723 | }; | |
| 2724 | ||
| 2725 | hdmi0: hdmi@fead0000 { | |
| 0ecbe08b | 2726 | compatible = "renesas,r8a77961-hdmi", "renesas,rcar-gen3-hdmi"; |
| f51746ad | 2727 | reg = <0 0xfead0000 0 0x10000>; |
| 0ecbe08b KM |
2728 | interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; |
| 2729 | clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A77961_CLK_HDMI>; | |
| 2730 | clock-names = "iahb", "isfr"; | |
| 2731 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2732 | resets = <&cpg 729>; | |
| 2733 | status = "disabled"; | |
| f51746ad GU |
2734 | |
| 2735 | ports { | |
| 2736 | #address-cells = <1>; | |
| 2737 | #size-cells = <0>; | |
| 2738 | port@0 { | |
| 2739 | reg = <0>; | |
| 0ecbe08b KM |
2740 | dw_hdmi0_in: endpoint { |
| 2741 | remote-endpoint = <&du_out_hdmi0>; | |
| 2742 | }; | |
| f51746ad GU |
2743 | }; |
| 2744 | port@1 { | |
| 2745 | reg = <1>; | |
| 2746 | }; | |
| 2747 | port@2 { | |
| 2748 | /* HDMI sound */ | |
| 2749 | reg = <2>; | |
| 2750 | }; | |
| 2751 | }; | |
| 2752 | }; | |
| 2753 | ||
| 2754 | du: display@feb00000 { | |
| d56896a4 | 2755 | compatible = "renesas,du-r8a77961"; |
| f51746ad | 2756 | reg = <0 0xfeb00000 0 0x70000>; |
| d56896a4 KM |
2757 | interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
| 2758 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, | |
| 2759 | <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; | |
| 2760 | clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, | |
| 2761 | <&cpg CPG_MOD 722>; | |
| 2762 | clock-names = "du.0", "du.1", "du.2"; | |
| 2763 | resets = <&cpg 724>, <&cpg 722>; | |
| 2764 | reset-names = "du.0", "du.2"; | |
| 2765 | ||
| 2766 | renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; | |
| 2767 | status = "disabled"; | |
| f51746ad GU |
2768 | |
| 2769 | ports { | |
| 2770 | #address-cells = <1>; | |
| 2771 | #size-cells = <0>; | |
| 2772 | ||
| 2773 | port@0 { | |
| 2774 | reg = <0>; | |
| f51746ad GU |
2775 | }; |
| 2776 | port@1 { | |
| 2777 | reg = <1>; | |
| 2778 | du_out_hdmi0: endpoint { | |
| 0ecbe08b | 2779 | remote-endpoint = <&dw_hdmi0_in>; |
| f51746ad GU |
2780 | }; |
| 2781 | }; | |
| 2782 | port@2 { | |
| 2783 | reg = <2>; | |
| 2784 | du_out_lvds0: endpoint { | |
| d45db61c NY |
2785 | remote-endpoint = <&lvds0_in>; |
| 2786 | }; | |
| 2787 | }; | |
| 2788 | }; | |
| 2789 | }; | |
| 2790 | ||
| 2791 | lvds0: lvds@feb90000 { | |
| 2792 | compatible = "renesas,r8a77961-lvds"; | |
| 2793 | reg = <0 0xfeb90000 0 0x14>; | |
| 2794 | clocks = <&cpg CPG_MOD 727>; | |
| 2795 | power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; | |
| 2796 | resets = <&cpg 727>; | |
| 2797 | status = "disabled"; | |
| 2798 | ||
| 2799 | ports { | |
| 2800 | #address-cells = <1>; | |
| 2801 | #size-cells = <0>; | |
| 2802 | ||
| 2803 | port@0 { | |
| 2804 | reg = <0>; | |
| 2805 | lvds0_in: endpoint { | |
| 2806 | remote-endpoint = <&du_out_lvds0>; | |
| 2807 | }; | |
| 2808 | }; | |
| 2809 | port@1 { | |
| 2810 | reg = <1>; | |
| f51746ad GU |
2811 | }; |
| 2812 | }; | |
| 2813 | }; | |
| 2814 | ||
| 2815 | prr: chipid@fff00044 { | |
| 2816 | compatible = "renesas,prr"; | |
| 2817 | reg = <0 0xfff00044 0 4>; | |
| 2818 | }; | |
| 2819 | }; | |
| 2820 | ||
| 17ab3c3e | 2821 | thermal-zones { |
| 82ce7939 | 2822 | sensor1_thermal: sensor1-thermal { |
| 17ab3c3e GU |
2823 | polling-delay-passive = <250>; |
| 2824 | polling-delay = <1000>; | |
| 2825 | thermal-sensors = <&tsc 0>; | |
| 2826 | sustainable-power = <3874>; | |
| 2827 | ||
| 2828 | trips { | |
| 2829 | sensor1_crit: sensor1-crit { | |
| 2830 | temperature = <120000>; | |
| 2831 | hysteresis = <1000>; | |
| 2832 | type = "critical"; | |
| 2833 | }; | |
| 2834 | }; | |
| 2835 | }; | |
| 2836 | ||
| 82ce7939 | 2837 | sensor2_thermal: sensor2-thermal { |
| 17ab3c3e GU |
2838 | polling-delay-passive = <250>; |
| 2839 | polling-delay = <1000>; | |
| 2840 | thermal-sensors = <&tsc 1>; | |
| 2841 | sustainable-power = <3874>; | |
| 2842 | ||
| 2843 | trips { | |
| 2844 | sensor2_crit: sensor2-crit { | |
| 2845 | temperature = <120000>; | |
| 2846 | hysteresis = <1000>; | |
| 2847 | type = "critical"; | |
| 2848 | }; | |
| 2849 | }; | |
| 2850 | }; | |
| 2851 | ||
| 82ce7939 | 2852 | sensor3_thermal: sensor3-thermal { |
| 17ab3c3e GU |
2853 | polling-delay-passive = <250>; |
| 2854 | polling-delay = <1000>; | |
| 2855 | thermal-sensors = <&tsc 2>; | |
| 2856 | sustainable-power = <3874>; | |
| 2857 | ||
| 2858 | cooling-maps { | |
| 2859 | map0 { | |
| 2860 | trip = <&target>; | |
| 2861 | cooling-device = <&a57_0 2 4>; | |
| 2862 | contribution = <1024>; | |
| 2863 | }; | |
| 2864 | map1 { | |
| 2865 | trip = <&target>; | |
| 2866 | cooling-device = <&a53_0 0 2>; | |
| 2867 | contribution = <1024>; | |
| 2868 | }; | |
| 2869 | }; | |
| 2870 | trips { | |
| 2871 | target: trip-point1 { | |
| 2872 | temperature = <100000>; | |
| 2873 | hysteresis = <1000>; | |
| 2874 | type = "passive"; | |
| 2875 | }; | |
| 2876 | ||
| 2877 | sensor3_crit: sensor3-crit { | |
| 2878 | temperature = <120000>; | |
| 2879 | hysteresis = <1000>; | |
| 2880 | type = "critical"; | |
| 2881 | }; | |
| 2882 | }; | |
| 2883 | }; | |
| 2884 | }; | |
| 2885 | ||
| f51746ad GU |
2886 | timer { |
| 2887 | compatible = "arm,armv8-timer"; | |
| 2888 | interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, | |
| 2889 | <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, | |
| 2890 | <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, | |
| 2891 | <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; | |
| 2892 | }; | |
| 2893 | ||
| 2894 | /* External USB clocks - can be overridden by the board */ | |
| 2895 | usb3s0_clk: usb3s0 { | |
| 2896 | compatible = "fixed-clock"; | |
| 2897 | #clock-cells = <0>; | |
| 2898 | clock-frequency = <0>; | |
| 2899 | }; | |
| 2900 | ||
| 2901 | usb_extal_clk: usb_extal { | |
| 2902 | compatible = "fixed-clock"; | |
| 2903 | #clock-cells = <0>; | |
| 2904 | clock-frequency = <0>; | |
| 2905 | }; | |
| 2906 | }; |