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Merge tag 'io_uring-5.7-2020-05-22' of git://git.kernel.dk/linux-block
[thirdparty/linux.git] / arch / arm64 / boot / dts / renesas / r8a77980.dtsi
CommitLineData
f3a54d6c
SS		 1// SPDX-License-Identifier: GPL-2.0
2/*
e18a31a7 3 * Device Tree Source for the R-Car V3H (R8A77980) SoC
f3a54d6c
SS		 4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8
c64cc368 9#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
f3a54d6c
SS		 10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
1184ea3f 12#include <dt-bindings/power/r8a77980-sysc.h>
f3a54d6c
SS		 13
14/ {
15 compatible = "renesas,r8a77980";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
bc620474
SS		 19 aliases {
20 i2c0 = &i2c0;
21 i2c1 = &i2c1;
22 i2c2 = &i2c2;
23 i2c3 = &i2c3;
24 i2c4 = &i2c4;
25 i2c5 = &i2c5;
26 };
27
18281dec
SS		 28 /* External CAN clock - to be overridden by boards that provide it */
29 can_clk: can {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
33 };
34
f3a54d6c
SS		 35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 a53_0: cpu@0 {
40 device_type = "cpu";
31af04cd 41 compatible = "arm,cortex-a53";
f3a54d6c 42 reg = <0>;
c64cc368 43 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
1184ea3f 44 power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
f3a54d6c
SS		 45 next-level-cache = <&L2_CA53>;
46 enable-method = "psci";
47 };
48
2ec1e4b4
SS		 49 a53_1: cpu@1 {
50 device_type = "cpu";
31af04cd 51 compatible = "arm,cortex-a53";
2ec1e4b4
SS		 52 reg = <1>;
53 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
54 power-domains = <&sysc R8A77980_PD_CA53_CPU1>;
55 next-level-cache = <&L2_CA53>;
56 enable-method = "psci";
57 };
58
59 a53_2: cpu@2 {
60 device_type = "cpu";
31af04cd 61 compatible = "arm,cortex-a53";
2ec1e4b4
SS		 62 reg = <2>;
63 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
64 power-domains = <&sysc R8A77980_PD_CA53_CPU2>;
65 next-level-cache = <&L2_CA53>;
66 enable-method = "psci";
67 };
68
69 a53_3: cpu@3 {
70 device_type = "cpu";
31af04cd 71 compatible = "arm,cortex-a53";
2ec1e4b4
SS		 72 reg = <3>;
73 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
74 power-domains = <&sysc R8A77980_PD_CA53_CPU3>;
75 next-level-cache = <&L2_CA53>;
76 enable-method = "psci";
77 };
78
f3a54d6c
SS		 79 L2_CA53: cache-controller {
80 compatible = "cache";
1184ea3f 81 power-domains = <&sysc R8A77980_PD_CA53_SCU>;
f3a54d6c
SS		 82 cache-unified;
83 cache-level = <2>;
84 };
85 };
86
87 extal_clk: extal {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 /* This value must be overridden by the board */
91 clock-frequency = <0>;
92 };
93
94 extalr_clk: extalr {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 /* This value must be overridden by the board */
98 clock-frequency = <0>;
99 };
100
ffa967e2
SS		 101 /* External PCIe clock - can be overridden by the board */
102 pcie_bus_clk: pcie_bus {
103 compatible = "fixed-clock";
104 #clock-cells = <0>;
105 clock-frequency = <0>;
106 };
107
0dba24a8
SS		 108 pmu_a53 {
109 compatible = "arm,cortex-a53-pmu";
110 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
111 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
112 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
113 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
114 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
115 };
116
f3a54d6c
SS		 117 psci {
118 compatible = "arm,psci-1.0", "arm,psci-0.2";
119 method = "smc";
120 };
121
3601d98c
SS		 122 /* External SCIF clock - to be overridden by boards that provide it */
123 scif_clk: scif {
124 compatible = "fixed-clock";
125 #clock-cells = <0>;
126 clock-frequency = <0>;
127 };
128
f3a54d6c
SS		 129 soc {
130 compatible = "simple-bus";
131 interrupt-parent = <&gic>;
132
133 #address-cells = <2>;
134 #size-cells = <2>;
135 ranges;
136
bcee502c
SS		 137 rwdt: watchdog@e6020000 {
138 compatible = "renesas,r8a77980-wdt",
139 "renesas,rcar-gen3-wdt";
140 reg = <0 0xe6020000 0 0x0c>;
141 clocks = <&cpg CPG_MOD 402>;
142 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
143 resets = <&cpg 402>;
144 status = "disabled";
145 };
146
efcb52e3
SS		 147 gpio0: gpio@e6050000 {
148 compatible = "renesas,gpio-r8a77980",
149 "renesas,rcar-gen3-gpio";
150 reg = <0 0xe6050000 0 0x50>;
151 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
152 #gpio-cells = <2>;
153 gpio-controller;
154 gpio-ranges = <&pfc 0 0 22>;
155 #interrupt-cells = <2>;
156 interrupt-controller;
157 clocks = <&cpg CPG_MOD 912>;
158 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
159 resets = <&cpg 912>;
160 };
161
162 gpio1: gpio@e6051000 {
163 compatible = "renesas,gpio-r8a77980",
164 "renesas,rcar-gen3-gpio";
165 reg = <0 0xe6051000 0 0x50>;
166 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
167 #gpio-cells = <2>;
168 gpio-controller;
169 gpio-ranges = <&pfc 0 32 28>;
170 #interrupt-cells = <2>;
171 interrupt-controller;
172 clocks = <&cpg CPG_MOD 911>;
173 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
174 resets = <&cpg 911>;
175 };
176
177 gpio2: gpio@e6052000 {
178 compatible = "renesas,gpio-r8a77980",
179 "renesas,rcar-gen3-gpio";
180 reg = <0 0xe6052000 0 0x50>;
181 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
182 #gpio-cells = <2>;
183 gpio-controller;
184 gpio-ranges = <&pfc 0 64 30>;
185 #interrupt-cells = <2>;
186 interrupt-controller;
187 clocks = <&cpg CPG_MOD 910>;
188 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
189 resets = <&cpg 910>;
190 };
191
192 gpio3: gpio@e6053000 {
193 compatible = "renesas,gpio-r8a77980",
194 "renesas,rcar-gen3-gpio";
195 reg = <0 0xe6053000 0 0x50>;
196 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
197 #gpio-cells = <2>;
198 gpio-controller;
199 gpio-ranges = <&pfc 0 96 17>;
200 #interrupt-cells = <2>;
201 interrupt-controller;
202 clocks = <&cpg CPG_MOD 909>;
203 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
204 resets = <&cpg 909>;
205 };
206
207 gpio4: gpio@e6054000 {
208 compatible = "renesas,gpio-r8a77980",
209 "renesas,rcar-gen3-gpio";
210 reg = <0 0xe6054000 0 0x50>;
211 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
212 #gpio-cells = <2>;
213 gpio-controller;
214 gpio-ranges = <&pfc 0 128 25>;
215 #interrupt-cells = <2>;
216 interrupt-controller;
217 clocks = <&cpg CPG_MOD 908>;
218 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
219 resets = <&cpg 908>;
220 };
221
222 gpio5: gpio@e6055000 {
223 compatible = "renesas,gpio-r8a77980",
224 "renesas,rcar-gen3-gpio";
225 reg = <0 0xe6055000 0 0x50>;
226 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
227 #gpio-cells = <2>;
228 gpio-controller;
229 gpio-ranges = <&pfc 0 160 15>;
230 #interrupt-cells = <2>;
231 interrupt-controller;
232 clocks = <&cpg CPG_MOD 907>;
233 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
234 resets = <&cpg 907>;
235 };
236
cef26946
SS		 237 pfc: pin-controller@e6060000 {
238 compatible = "renesas,pfc-r8a77980";
239 reg = <0 0xe6060000 0 0x50c>;
240 };
241
a215af75
SS		 242 cmt0: timer@e60f0000 {
243 compatible = "renesas,r8a77980-cmt0",
244 "renesas,rcar-gen3-cmt0";
245 reg = <0 0xe60f0000 0 0x1004>;
246 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cpg CPG_MOD 303>;
249 clock-names = "fck";
250 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
251 resets = <&cpg 303>;
252 status = "disabled";
253 };
254
255 cmt1: timer@e6130000 {
256 compatible = "renesas,r8a77980-cmt1",
257 "renesas,rcar-gen3-cmt1";
258 reg = <0 0xe6130000 0 0x1004>;
259 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&cpg CPG_MOD 302>;
268 clock-names = "fck";
269 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
270 resets = <&cpg 302>;
271 status = "disabled";
272 };
273
274 cmt2: timer@e6140000 {
275 compatible = "renesas,r8a77980-cmt1",
276 "renesas,rcar-gen3-cmt1";
277 reg = <0 0xe6140000 0 0x1004>;
278 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&cpg CPG_MOD 301>;
287 clock-names = "fck";
288 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
289 resets = <&cpg 301>;
290 status = "disabled";
291 };
292
293 cmt3: timer@e6148000 {
294 compatible = "renesas,r8a77980-cmt1",
295 "renesas,rcar-gen3-cmt1";
296 reg = <0 0xe6148000 0 0x1004>;
297 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&cpg CPG_MOD 300>;
306 clock-names = "fck";
307 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
308 resets = <&cpg 300>;
309 status = "disabled";
310 };
311
f3a54d6c
SS		 312 cpg: clock-controller@e6150000 {
313 compatible = "renesas,r8a77980-cpg-mssr";
314 reg = <0 0xe6150000 0 0x1000>;
315 clocks = <&extal_clk>, <&extalr_clk>;
316 clock-names = "extal", "extalr";
317 #clock-cells = <2>;
318 #power-domain-cells = <0>;
319 #reset-cells = <1>;
320 };
321
322 rst: reset-controller@e6160000 {
323 compatible = "renesas,r8a77980-rst";
324 reg = <0 0xe6160000 0 0x200>;
325 };
326
327 sysc: system-controller@e6180000 {
328 compatible = "renesas,r8a77980-sysc";
329 reg = <0 0xe6180000 0 0x440>;
330 #power-domain-cells = <1>;
331 };
332
69c5e602
SS		 333 tsc: thermal@e6198000 {
334 compatible = "renesas,r8a77980-thermal";
335 reg = <0 0xe6198000 0 0x100>,
336 <0 0xe61a0000 0 0x100>;
337 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&cpg CPG_MOD 522>;
341 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
342 resets = <&cpg 522>;
343 #thermal-sensor-cells = <1>;
344 };
345
9a6c158f
SS		 346 intc_ex: interrupt-controller@e61c0000 {
347 compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
348 #interrupt-cells = <2>;
349 interrupt-controller;
350 reg = <0 0xe61c0000 0 0x200>;
0aab5b91
GU		 351 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
9a6c158f
SS		 357 clocks = <&cpg CPG_MOD 407>;
358 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
359 resets = <&cpg 407>;
360 };
361
cb202e7c
SS		 362 tmu0: timer@e61e0000 {
363 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
364 reg = <0 0xe61e0000 0 0x30>;
365 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&cpg CPG_MOD 125>;
369 clock-names = "fck";
370 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
371 resets = <&cpg 125>;
372 status = "disabled";
373 };
374
375 tmu1: timer@e6fc0000 {
376 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
377 reg = <0 0xe6fc0000 0 0x30>;
378 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&cpg CPG_MOD 124>;
382 clock-names = "fck";
383 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
384 resets = <&cpg 124>;
385 status = "disabled";
386 };
387
388 tmu2: timer@e6fd0000 {
389 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
390 reg = <0 0xe6fd0000 0 0x30>;
391 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&cpg CPG_MOD 123>;
395 clock-names = "fck";
396 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
397 resets = <&cpg 123>;
398 status = "disabled";
399 };
400
401 tmu3: timer@e6fe0000 {
402 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
403 reg = <0 0xe6fe0000 0 0x30>;
404 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&cpg CPG_MOD 122>;
408 clock-names = "fck";
409 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
410 resets = <&cpg 122>;
411 status = "disabled";
412 };
413
414 tmu4: timer@ffc00000 {
415 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
416 reg = <0 0xffc00000 0 0x30>;
417 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&cpg CPG_MOD 121>;
421 clock-names = "fck";
422 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
423 resets = <&cpg 121>;
424 status = "disabled";
425 };
426
bc620474
SS		 427 i2c0: i2c@e6500000 {
428 compatible = "renesas,i2c-r8a77980",
429 "renesas,rcar-gen3-i2c";
430 reg = <0 0xe6500000 0 0x40>;
431 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&cpg CPG_MOD 931>;
433 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
434 resets = <&cpg 931>;
435 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
436 <&dmac2 0x91>, <&dmac2 0x90>;
437 dma-names = "tx", "rx", "tx", "rx";
438 i2c-scl-internal-delay-ns = <6>;
439 #address-cells = <1>;
440 #size-cells = <0>;
441 status = "disabled";
442 };
443
444 i2c1: i2c@e6508000 {
445 compatible = "renesas,i2c-r8a77980",
446 "renesas,rcar-gen3-i2c";
447 reg = <0 0xe6508000 0 0x40>;
448 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&cpg CPG_MOD 930>;
450 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
451 resets = <&cpg 930>;
452 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
453 <&dmac2 0x93>, <&dmac2 0x92>;
454 dma-names = "tx", "rx", "tx", "rx";
455 i2c-scl-internal-delay-ns = <6>;
456 #address-cells = <1>;
457 #size-cells = <0>;
458 status = "disabled";
459 };
460
461 i2c2: i2c@e6510000 {
462 compatible = "renesas,i2c-r8a77980",
463 "renesas,rcar-gen3-i2c";
464 reg = <0 0xe6510000 0 0x40>;
465 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&cpg CPG_MOD 929>;
467 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
468 resets = <&cpg 929>;
469 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
470 <&dmac2 0x95>, <&dmac2 0x94>;
471 dma-names = "tx", "rx", "tx", "rx";
472 i2c-scl-internal-delay-ns = <6>;
473 #address-cells = <1>;
474 #size-cells = <0>;
475 status = "disabled";
476 };
477
478 i2c3: i2c@e66d0000 {
479 compatible = "renesas,i2c-r8a77980",
480 "renesas,rcar-gen3-i2c";
481 reg = <0 0xe66d0000 0 0x40>;
482 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&cpg CPG_MOD 928>;
484 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
485 resets = <&cpg 928>;
486 i2c-scl-internal-delay-ns = <6>;
487 #address-cells = <1>;
488 #size-cells = <0>;
489 status = "disabled";
490 };
491
492 i2c4: i2c@e66d8000 {
493 compatible = "renesas,i2c-r8a77980",
494 "renesas,rcar-gen3-i2c";
495 reg = <0 0xe66d8000 0 0x40>;
496 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&cpg CPG_MOD 927>;
498 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
499 resets = <&cpg 927>;
500 i2c-scl-internal-delay-ns = <6>;
501 #address-cells = <1>;
502 #size-cells = <0>;
503 status = "disabled";
504 };
505
506 i2c5: i2c@e66e0000 {
507 compatible = "renesas,i2c-r8a77980",
508 "renesas,rcar-gen3-i2c";
509 reg = <0 0xe66e0000 0 0x40>;
510 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cpg CPG_MOD 919>;
512 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
513 resets = <&cpg 919>;
514 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
515 <&dmac2 0x9b>, <&dmac2 0x9a>;
516 dma-names = "tx", "rx", "tx", "rx";
517 i2c-scl-internal-delay-ns = <6>;
518 #address-cells = <1>;
519 #size-cells = <0>;
520 status = "disabled";
521 };
522
3601d98c
SS		 523 hscif0: serial@e6540000 {
524 compatible = "renesas,hscif-r8a77980",
525 "renesas,rcar-gen3-hscif",
526 "renesas,hscif";
527 reg = <0 0xe6540000 0 0x60>;
528 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&cpg CPG_MOD 520>,
c64cc368 530 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
3601d98c
SS		 531 <&scif_clk>;
532 clock-names = "fck", "brg_int", "scif_clk";
533 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
534 <&dmac2 0x31>, <&dmac2 0x30>;
535 dma-names = "tx", "rx", "tx", "rx";
1184ea3f 536 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
3601d98c
SS		 537 resets = <&cpg 520>;
538 status = "disabled";
539 };
540
541 hscif1: serial@e6550000 {
542 compatible = "renesas,hscif-r8a77980",
543 "renesas,rcar-gen3-hscif",
544 "renesas,hscif";
545 reg = <0 0xe6550000 0 0x60>;
546 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&cpg CPG_MOD 519>,
c64cc368 548 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
3601d98c
SS		 549 <&scif_clk>;
550 clock-names = "fck", "brg_int", "scif_clk";
551 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
552 <&dmac2 0x33>, <&dmac2 0x32>;
553 dma-names = "tx", "rx", "tx", "rx";
1184ea3f 554 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
3601d98c
SS		 555 resets = <&cpg 519>;
556 status = "disabled";
557 };
558
559 hscif2: serial@e6560000 {
560 compatible = "renesas,hscif-r8a77980",
561 "renesas,rcar-gen3-hscif",
562 "renesas,hscif";
563 reg = <0 0xe6560000 0 0x60>;
564 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&cpg CPG_MOD 518>,
c64cc368 566 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
3601d98c
SS		 567 <&scif_clk>;
568 clock-names = "fck", "brg_int", "scif_clk";
569 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
570 <&dmac2 0x35>, <&dmac2 0x34>;
571 dma-names = "tx", "rx", "tx", "rx";
1184ea3f 572 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
3601d98c
SS		 573 resets = <&cpg 518>;
574 status = "disabled";
575 };
576
577 hscif3: serial@e66a0000 {
578 compatible = "renesas,hscif-r8a77980",
579 "renesas,rcar-gen3-hscif",
580 "renesas,hscif";
581 reg = <0 0xe66a0000 0 0x60>;
582 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&cpg CPG_MOD 517>,
c64cc368 584 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
3601d98c
SS		 585 <&scif_clk>;
586 clock-names = "fck", "brg_int", "scif_clk";
587 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
588 <&dmac2 0x37>, <&dmac2 0x36>;
589 dma-names = "tx", "rx", "tx", "rx";
1184ea3f 590 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
3601d98c
SS		 591 resets = <&cpg 517>;
592 status = "disabled";
593 };
594
ffa967e2
SS		 595 pcie_phy: pcie-phy@e65d0000 {
596 compatible = "renesas,r8a77980-pcie-phy";
597 reg = <0 0xe65d0000 0 0x8000>;
598 #phy-cells = <0>;
599 clocks = <&cpg CPG_MOD 319>;
600 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
601 resets = <&cpg 319>;
602 status = "disabled";
603 };
604
f38c4172
SS		 605 canfd: can@e66c0000 {
606 compatible = "renesas,r8a77980-canfd",
607 "renesas,rcar-gen3-canfd";
608 reg = <0 0xe66c0000 0 0x8000>;
609 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&cpg CPG_MOD 914>,
612 <&cpg CPG_CORE R8A77980_CLK_CANFD>,
613 <&can_clk>;
614 clock-names = "fck", "canfd", "can_clk";
615 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
616 assigned-clock-rates = <40000000>;
617 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
22fb06cd 618 resets = <&cpg 914>;
f38c4172
SS		 619 status = "disabled";
620
621 channel0 {
622 status = "disabled";
623 };
624
625 channel1 {
626 status = "disabled";
627 };
628 };
629
bf6f9083
SS		 630 avb: ethernet@e6800000 {
631 compatible = "renesas,etheravb-r8a77980",
632 "renesas,etheravb-rcar-gen3";
633 reg = <0 0xe6800000 0 0x800>;
634 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
659 interrupt-names = "ch0", "ch1", "ch2", "ch3",
660 "ch4", "ch5", "ch6", "ch7",
661 "ch8", "ch9", "ch10", "ch11",
662 "ch12", "ch13", "ch14", "ch15",
663 "ch16", "ch17", "ch18", "ch19",
664 "ch20", "ch21", "ch22", "ch23",
665 "ch24";
666 clocks = <&cpg CPG_MOD 812>;
1184ea3f 667 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
bf6f9083
SS		 668 resets = <&cpg 812>;
669 phy-mode = "rgmii";
7ffbcb23 670 iommus = <&ipmmu_ds1 33>;
bf6f9083
SS		 671 #address-cells = <1>;
672 #size-cells = <0>;
52d2e0ce 673 status = "disabled";
bf6f9083
SS		 674 };
675
de625477
SS		 676 pwm0: pwm@e6e30000 {
677 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
678 reg = <0 0xe6e30000 0 0x10>;
679 #pwm-cells = <2>;
680 clocks = <&cpg CPG_MOD 523>;
681 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
682 resets = <&cpg 523>;
683 status = "disabled";
684 };
685
686 pwm1: pwm@e6e31000 {
687 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
688 reg = <0 0xe6e31000 0 0x10>;
689 #pwm-cells = <2>;
690 clocks = <&cpg CPG_MOD 523>;
691 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
692 resets = <&cpg 523>;
693 status = "disabled";
694 };
695
696 pwm2: pwm@e6e32000 {
697 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
698 reg = <0 0xe6e32000 0 0x10>;
699 #pwm-cells = <2>;
700 clocks = <&cpg CPG_MOD 523>;
701 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
702 resets = <&cpg 523>;
703 status = "disabled";
704 };
705
706 pwm3: pwm@e6e33000 {
707 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
708 reg = <0 0xe6e33000 0 0x10>;
709 #pwm-cells = <2>;
710 clocks = <&cpg CPG_MOD 523>;
711 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
712 resets = <&cpg 523>;
713 status = "disabled";
714 };
715
716 pwm4: pwm@e6e34000 {
717 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
718 reg = <0 0xe6e34000 0 0x10>;
719 #pwm-cells = <2>;
720 clocks = <&cpg CPG_MOD 523>;
721 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
722 resets = <&cpg 523>;
723 status = "disabled";
724 };
725
3601d98c
SS		 726 scif0: serial@e6e60000 {
727 compatible = "renesas,scif-r8a77980",
728 "renesas,rcar-gen3-scif",
729 "renesas,scif";
730 reg = <0 0xe6e60000 0 0x40>;
731 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&cpg CPG_MOD 207>,
c64cc368 733 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
3601d98c
SS		 734 <&scif_clk>;
735 clock-names = "fck", "brg_int", "scif_clk";
736 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
737 <&dmac2 0x51>, <&dmac2 0x50>;
738 dma-names = "tx", "rx", "tx", "rx";
1184ea3f 739 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
3601d98c
SS		 740 resets = <&cpg 207>;
741 status = "disabled";
742 };
743
744 scif1: serial@e6e68000 {
745 compatible = "renesas,scif-r8a77980",
746 "renesas,rcar-gen3-scif",
747 "renesas,scif";
748 reg = <0 0xe6e68000 0 0x40>;
749 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&cpg CPG_MOD 206>,
c64cc368 751 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
3601d98c
SS		 752 <&scif_clk>;
753 clock-names = "fck", "brg_int", "scif_clk";
754 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
755 <&dmac2 0x53>, <&dmac2 0x52>;
756 dma-names = "tx", "rx", "tx", "rx";
1184ea3f 757 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
3601d98c
SS		 758 resets = <&cpg 206>;
759 status = "disabled";
760 };
761
762 scif3: serial@e6c50000 {
763 compatible = "renesas,scif-r8a77980",
764 "renesas,rcar-gen3-scif",
765 "renesas,scif";
766 reg = <0 0xe6c50000 0 0x40>;
767 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&cpg CPG_MOD 204>,
c64cc368 769 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
3601d98c
SS		 770 <&scif_clk>;
771 clock-names = "fck", "brg_int", "scif_clk";
772 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
773 <&dmac2 0x57>, <&dmac2 0x56>;
774 dma-names = "tx", "rx", "tx", "rx";
1184ea3f 775 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
3601d98c
SS		 776 resets = <&cpg 204>;
777 status = "disabled";
778 };
779
780 scif4: serial@e6c40000 {
781 compatible = "renesas,scif-r8a77980",
782 "renesas,rcar-gen3-scif",
783 "renesas,scif";
784 reg = <0 0xe6c40000 0 0x40>;
785 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&cpg CPG_MOD 203>,
c64cc368 787 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
3601d98c
SS		 788 <&scif_clk>;
789 clock-names = "fck", "brg_int", "scif_clk";
790 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
791 <&dmac2 0x59>, <&dmac2 0x58>;
792 dma-names = "tx", "rx", "tx", "rx";
1184ea3f 793 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
3601d98c
SS		 794 resets = <&cpg 203>;
795 status = "disabled";
796 };
797
dd809b7d
SS		 798 tpu: pwm@e6e80000 {
799 compatible = "renesas,tpu-r8a77980", "renesas,tpu";
800 reg = <0 0xe6e80000 0 0x148>;
801 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&cpg CPG_MOD 304>;
803 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
804 resets = <&cpg 304>;
805 #pwm-cells = <3>;
806 status = "disabled";
807 };
808
122ddb71
SS		 809 msiof0: spi@e6e90000 {
810 compatible = "renesas,msiof-r8a77980",
811 "renesas,rcar-gen3-msiof";
812 reg = <0 0xe6e90000 0 0x64>;
813 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&cpg CPG_MOD 211>;
815 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
816 resets = <&cpg 211>;
817 #address-cells = <1>;
818 #size-cells = <0>;
819 status = "disabled";
820 };
821
822 msiof1: spi@e6ea0000 {
823 compatible = "renesas,msiof-r8a77980",
824 "renesas,rcar-gen3-msiof";
825 reg = <0 0xe6ea0000 0 0x0064>;
826 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
827 clocks = <&cpg CPG_MOD 210>;
828 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
829 resets = <&cpg 210>;
830 #address-cells = <1>;
831 #size-cells = <0>;
832 status = "disabled";
833 };
834
835 msiof2: spi@e6c00000 {
836 compatible = "renesas,msiof-r8a77980",
837 "renesas,rcar-gen3-msiof";
838 reg = <0 0xe6c00000 0 0x0064>;
839 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
840 clocks = <&cpg CPG_MOD 209>;
841 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
842 resets = <&cpg 209>;
843 #address-cells = <1>;
844 #size-cells = <0>;
845 status = "disabled";
846 };
847
848 msiof3: spi@e6c10000 {
849 compatible = "renesas,msiof-r8a77980",
850 "renesas,rcar-gen3-msiof";
851 reg = <0 0xe6c10000 0 0x0064>;
852 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&cpg CPG_MOD 208>;
854 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
855 resets = <&cpg 208>;
856 #address-cells = <1>;
857 #size-cells = <0>;
858 status = "disabled";
859 };
860
3182aa4e
SS		 861 vin0: video@e6ef0000 {
862 compatible = "renesas,vin-r8a77980";
863 reg = <0 0xe6ef0000 0 0x1000>;
864 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&cpg CPG_MOD 811>;
866 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
867 resets = <&cpg 811>;
b7f5a8e4 868 renesas,id = <0>;
3182aa4e
SS		 869 status = "disabled";
870
871 ports {
872 #address-cells = <1>;
873 #size-cells = <0>;
874
875 port@1 {
876 #address-cells = <1>;
877 #size-cells = <0>;
878
879 reg = <1>;
880
881 vin0csi40: endpoint@2 {
882 reg = <2>;
fced3a97 883 remote-endpoint = <&csi40vin0>;
3182aa4e
SS		 884 };
885 };
886 };
887 };
888
889 vin1: video@e6ef1000 {
890 compatible = "renesas,vin-r8a77980";
891 reg = <0 0xe6ef1000 0 0x1000>;
892 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&cpg CPG_MOD 810>;
894 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
895 status = "disabled";
b7f5a8e4 896 renesas,id = <1>;
3182aa4e
SS		 897 resets = <&cpg 810>;
898
899 ports {
900 #address-cells = <1>;
901 #size-cells = <0>;
902
903 port@1 {
904 #address-cells = <1>;
905 #size-cells = <0>;
906
907 reg = <1>;
908
909 vin1csi40: endpoint@2 {
910 reg = <2>;
fced3a97 911 remote-endpoint = <&csi40vin1>;
3182aa4e
SS		 912 };
913 };
914 };
915 };
916
917 vin2: video@e6ef2000 {
918 compatible = "renesas,vin-r8a77980";
919 reg = <0 0xe6ef2000 0 0x1000>;
920 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&cpg CPG_MOD 809>;
922 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
923 resets = <&cpg 809>;
b7f5a8e4 924 renesas,id = <2>;
3182aa4e
SS		 925 status = "disabled";
926
927 ports {
928 #address-cells = <1>;
929 #size-cells = <0>;
930
931 port@1 {
932 #address-cells = <1>;
933 #size-cells = <0>;
934
935 reg = <1>;
936
937 vin2csi40: endpoint@2 {
938 reg = <2>;
fced3a97 939 remote-endpoint = <&csi40vin2>;
3182aa4e
SS		 940 };
941 };
942 };
943 };
944
945 vin3: video@e6ef3000 {
946 compatible = "renesas,vin-r8a77980";
947 reg = <0 0xe6ef3000 0 0x1000>;
948 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&cpg CPG_MOD 808>;
950 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
951 resets = <&cpg 808>;
b7f5a8e4 952 renesas,id = <3>;
3182aa4e
SS		 953 status = "disabled";
954
955 ports {
956 #address-cells = <1>;
957 #size-cells = <0>;
958
959 port@1 {
960 #address-cells = <1>;
961 #size-cells = <0>;
962
963 reg = <1>;
964
965 vin3csi40: endpoint@2 {
966 reg = <2>;
fced3a97 967 remote-endpoint = <&csi40vin3>;
3182aa4e
SS		 968 };
969 };
970 };
971 };
972
973 vin4: video@e6ef4000 {
974 compatible = "renesas,vin-r8a77980";
975 reg = <0 0xe6ef4000 0 0x1000>;
976 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
977 clocks = <&cpg CPG_MOD 807>;
978 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
979 resets = <&cpg 807>;
b7f5a8e4 980 renesas,id = <4>;
3182aa4e
SS		 981 status = "disabled";
982
983 ports {
984 #address-cells = <1>;
985 #size-cells = <0>;
986
987 port@1 {
988 #address-cells = <1>;
989 #size-cells = <0>;
990
991 reg = <1>;
992
993 vin4csi41: endpoint@2 {
994 reg = <2>;
fced3a97 995 remote-endpoint = <&csi41vin4>;
3182aa4e
SS		 996 };
997 };
998 };
999 };
1000
1001 vin5: video@e6ef5000 {
1002 compatible = "renesas,vin-r8a77980";
1003 reg = <0 0xe6ef5000 0 0x1000>;
1004 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1005 clocks = <&cpg CPG_MOD 806>;
1006 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1007 resets = <&cpg 806>;
b7f5a8e4 1008 renesas,id = <5>;
3182aa4e
SS		 1009 status = "disabled";
1010
1011 ports {
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1014
1015 port@1 {
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1018
1019 reg = <1>;
1020
1021 vin5csi41: endpoint@2 {
1022 reg = <2>;
fced3a97 1023 remote-endpoint = <&csi41vin5>;
3182aa4e
SS		 1024 };
1025 };
1026 };
1027 };
1028
1029 vin6: video@e6ef6000 {
1030 compatible = "renesas,vin-r8a77980";
1031 reg = <0 0xe6ef6000 0 0x1000>;
1032 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1033 clocks = <&cpg CPG_MOD 805>;
1034 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1035 resets = <&cpg 805>;
b7f5a8e4 1036 renesas,id = <6>;
3182aa4e
SS		 1037 status = "disabled";
1038
1039 ports {
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1042
1043 port@1 {
1044 #address-cells = <1>;
1045 #size-cells = <0>;
1046
1047 reg = <1>;
1048
1049 vin6csi41: endpoint@2 {
1050 reg = <2>;
fced3a97 1051 remote-endpoint = <&csi41vin6>;
3182aa4e
SS		 1052 };
1053 };
1054 };
1055 };
1056
1057 vin7: video@e6ef7000 {
1058 compatible = "renesas,vin-r8a77980";
1059 reg = <0 0xe6ef7000 0 0x1000>;
1060 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1061 clocks = <&cpg CPG_MOD 804>;
1062 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1063 resets = <&cpg 804>;
b7f5a8e4 1064 renesas,id = <7>;
3182aa4e
SS		 1065 status = "disabled";
1066
1067 ports {
1068 #address-cells = <1>;
1069 #size-cells = <0>;
1070
1071 port@1 {
1072 #address-cells = <1>;
1073 #size-cells = <0>;
1074
1075 reg = <1>;
1076
1077 vin7csi41: endpoint@2 {
1078 reg = <2>;
fced3a97 1079 remote-endpoint = <&csi41vin7>;
3182aa4e
SS		 1080 };
1081 };
1082 };
1083 };
1084
1085 vin8: video@e6ef8000 {
1086 compatible = "renesas,vin-r8a77980";
1087 reg = <0 0xe6ef8000 0 0x1000>;
1088 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1089 clocks = <&cpg CPG_MOD 628>;
1090 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1091 resets = <&cpg 628>;
b7f5a8e4 1092 renesas,id = <8>;
3182aa4e
SS		 1093 status = "disabled";
1094 };
1095
1096 vin9: video@e6ef9000 {
1097 compatible = "renesas,vin-r8a77980";
1098 reg = <0 0xe6ef9000 0 0x1000>;
1099 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1100 clocks = <&cpg CPG_MOD 627>;
1101 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1102 resets = <&cpg 627>;
b7f5a8e4 1103 renesas,id = <9>;
3182aa4e
SS		 1104 status = "disabled";
1105 };
1106
1107 vin10: video@e6efa000 {
1108 compatible = "renesas,vin-r8a77980";
1109 reg = <0 0xe6efa000 0 0x1000>;
1110 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
1111 clocks = <&cpg CPG_MOD 625>;
1112 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1113 resets = <&cpg 625>;
b7f5a8e4 1114 renesas,id = <10>;
3182aa4e
SS		 1115 status = "disabled";
1116 };
1117
1118 vin11: video@e6efb000 {
1119 compatible = "renesas,vin-r8a77980";
1120 reg = <0 0xe6efb000 0 0x1000>;
1121 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1122 clocks = <&cpg CPG_MOD 618>;
1123 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1124 resets = <&cpg 618>;
b7f5a8e4 1125 renesas,id = <11>;
3182aa4e
SS		 1126 status = "disabled";
1127 };
1128
1129 vin12: video@e6efc000 {
1130 compatible = "renesas,vin-r8a77980";
1131 reg = <0 0xe6efc000 0 0x1000>;
1132 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1133 clocks = <&cpg CPG_MOD 612>;
1134 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1135 resets = <&cpg 612>;
b7f5a8e4 1136 renesas,id = <12>;
3182aa4e
SS		 1137 status = "disabled";
1138 };
1139
1140 vin13: video@e6efd000 {
1141 compatible = "renesas,vin-r8a77980";
1142 reg = <0 0xe6efd000 0 0x1000>;
1143 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1144 clocks = <&cpg CPG_MOD 608>;
1145 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1146 resets = <&cpg 608>;
b7f5a8e4 1147 renesas,id = <13>;
3182aa4e
SS		 1148 status = "disabled";
1149 };
1150
1151 vin14: video@e6efe000 {
1152 compatible = "renesas,vin-r8a77980";
1153 reg = <0 0xe6efe000 0 0x1000>;
1154 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
1155 clocks = <&cpg CPG_MOD 605>;
1156 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1157 resets = <&cpg 605>;
b7f5a8e4 1158 renesas,id = <14>;
3182aa4e
SS		 1159 status = "disabled";
1160 };
1161
1162 vin15: video@e6eff000 {
1163 compatible = "renesas,vin-r8a77980";
1164 reg = <0 0xe6eff000 0 0x1000>;
1165 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
1166 clocks = <&cpg CPG_MOD 604>;
1167 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1168 resets = <&cpg 604>;
b7f5a8e4 1169 renesas,id = <15>;
3182aa4e
SS		 1170 status = "disabled";
1171 };
1172
00d3375f
SS		 1173 dmac1: dma-controller@e7300000 {
1174 compatible = "renesas,dmac-r8a77980",
1175 "renesas,rcar-dmac";
1176 reg = <0 0xe7300000 0 0x10000>;
0aab5b91
GU		 1177 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1178 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1179 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1180 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1181 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1182 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1183 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1184 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1185 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
1186 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
1189 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
1190 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
1191 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
1192 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
1193 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
00d3375f
SS		 1194 interrupt-names = "error",
1195 "ch0", "ch1", "ch2", "ch3",
1196 "ch4", "ch5", "ch6", "ch7",
1197 "ch8", "ch9", "ch10", "ch11",
1198 "ch12", "ch13", "ch14", "ch15";
1199 clocks = <&cpg CPG_MOD 218>;
1200 clock-names = "fck";
1184ea3f 1201 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
00d3375f
SS		 1202 resets = <&cpg 218>;
1203 #dma-cells = <1>;
1204 dma-channels = <16>;
d59b0784
MD		 1205 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1206 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
1207 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
1208 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
1209 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
1210 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
1211 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
1212 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
00d3375f
SS		 1213 };
1214
1215 dmac2: dma-controller@e7310000 {
1216 compatible = "renesas,dmac-r8a77980",
1217 "renesas,rcar-dmac";
1218 reg = <0 0xe7310000 0 0x10000>;
0aab5b91
GU		 1219 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
00d3375f
SS		 1236 interrupt-names = "error",
1237 "ch0", "ch1", "ch2", "ch3",
1238 "ch4", "ch5", "ch6", "ch7",
1239 "ch8", "ch9", "ch10", "ch11",
1240 "ch12", "ch13", "ch14", "ch15";
1241 clocks = <&cpg CPG_MOD 217>;
1242 clock-names = "fck";
1184ea3f 1243 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
00d3375f
SS		 1244 resets = <&cpg 217>;
1245 #dma-cells = <1>;
1246 dma-channels = <16>;
d59b0784
MD		 1247 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1248 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1249 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1250 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1251 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1252 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1253 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1254 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
00d3375f
SS		 1255 };
1256
87bea678
SS		 1257 gether: ethernet@e7400000 {
1258 compatible = "renesas,gether-r8a77980";
1259 reg = <0 0xe7400000 0 0x1000>;
1260 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1261 clocks = <&cpg CPG_MOD 813>;
1262 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1263 resets = <&cpg 813>;
1264 #address-cells = <1>;
1265 #size-cells = <0>;
1266 status = "disabled";
1267 };
1268
f14bfabc
SS		 1269 ipmmu_ds1: mmu@e7740000 {
1270 compatible = "renesas,ipmmu-r8a77980";
1271 reg = <0 0xe7740000 0 0x1000>;
1272 renesas,ipmmu-main = <&ipmmu_mm 0>;
1273 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1274 #iommu-cells = <1>;
1275 };
1276
1277 ipmmu_ir: mmu@ff8b0000 {
1278 compatible = "renesas,ipmmu-r8a77980";
1279 reg = <0 0xff8b0000 0 0x1000>;
1280 renesas,ipmmu-main = <&ipmmu_mm 3>;
1281 power-domains = <&sysc R8A77980_PD_A3IR>;
1282 #iommu-cells = <1>;
1283 };
1284
1285 ipmmu_mm: mmu@e67b0000 {
1286 compatible = "renesas,ipmmu-r8a77980";
1287 reg = <0 0xe67b0000 0 0x1000>;
1288 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1289 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1290 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1291 #iommu-cells = <1>;
1292 };
1293
1294 ipmmu_rt: mmu@ffc80000 {
1295 compatible = "renesas,ipmmu-r8a77980";
1296 reg = <0 0xffc80000 0 0x1000>;
1297 renesas,ipmmu-main = <&ipmmu_mm 10>;
1298 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1299 #iommu-cells = <1>;
1300 };
1301
62a17029 1302 ipmmu_vc0: mmu@fe990000 {
f14bfabc 1303 compatible = "renesas,ipmmu-r8a77980";
62a17029 1304 reg = <0 0xfe990000 0 0x1000>;
f14bfabc
SS		 1305 renesas,ipmmu-main = <&ipmmu_mm 12>;
1306 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1307 #iommu-cells = <1>;
1308 };
1309
1310 ipmmu_vi0: mmu@febd0000 {
1311 compatible = "renesas,ipmmu-r8a77980";
1312 reg = <0 0xfebd0000 0 0x1000>;
1313 renesas,ipmmu-main = <&ipmmu_mm 14>;
1314 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1315 #iommu-cells = <1>;
1316 };
1317
1318 ipmmu_vip0: mmu@e7b00000 {
1319 compatible = "renesas,ipmmu-r8a77980";
1320 reg = <0 0xe7b00000 0 0x1000>;
f4d71c6e 1321 renesas,ipmmu-main = <&ipmmu_mm 4>;
f14bfabc
SS		 1322 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1323 #iommu-cells = <1>;
1324 };
1325
1326 ipmmu_vip1: mmu@e7960000 {
1327 compatible = "renesas,ipmmu-r8a77980";
1328 reg = <0 0xe7960000 0 0x1000>;
f4d71c6e 1329 renesas,ipmmu-main = <&ipmmu_mm 11>;
f14bfabc
SS		 1330 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1331 #iommu-cells = <1>;
1332 };
1333
63eb8ee5
SS		 1334 mmc0: mmc@ee140000 {
1335 compatible = "renesas,sdhi-r8a77980",
1336 "renesas,rcar-gen3-sdhi";
1337 reg = <0 0xee140000 0 0x2000>;
1338 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1339 clocks = <&cpg CPG_MOD 314>;
1184ea3f 1340 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
63eb8ee5
SS		 1341 resets = <&cpg 314>;
1342 max-frequency = <200000000>;
8292f5eb 1343 iommus = <&ipmmu_ds1 32>;
63eb8ee5
SS		 1344 status = "disabled";
1345 };
1346
f3a54d6c
SS		 1347 gic: interrupt-controller@f1010000 {
1348 compatible = "arm,gic-400";
1349 #interrupt-cells = <3>;
1350 #address-cells = <0>;
1351 interrupt-controller;
1352 reg = <0x0 0xf1010000 0 0x1000>,
1353 <0x0 0xf1020000 0 0x20000>,
1354 <0x0 0xf1040000 0 0x20000>,
1355 <0x0 0xf1060000 0 0x20000>;
2ec1e4b4 1356 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
f3a54d6c
SS		 1357 IRQ_TYPE_LEVEL_HIGH)>;
1358 clocks = <&cpg CPG_MOD 408>;
1359 clock-names = "clk";
1184ea3f 1360 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
f3a54d6c
SS		 1361 resets = <&cpg 408>;
1362 };
1363
ffa967e2
SS		 1364 pciec: pcie@fe000000 {
1365 compatible = "renesas,pcie-r8a77980",
1366 "renesas,pcie-rcar-gen3";
1367 reg = <0 0xfe000000 0 0x80000>;
1368 #address-cells = <3>;
1369 #size-cells = <2>;
1370 bus-range = <0x00 0xff>;
1371 device_type = "pci";
9504a9f2
GU		 1372 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000>,
1373 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>,
1374 <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,
1375 <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>;
1376 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
ffa967e2
SS		 1377 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1380 #interrupt-cells = <1>;
1381 interrupt-map-mask = <0 0 0 0>;
0aab5b91 1382 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
ffa967e2
SS		 1383 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1384 clock-names = "pcie", "pcie_bus";
1385 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1386 resets = <&cpg 319>;
1387 phys = <&pcie_phy>;
1388 phy-names = "pcie";
1389 status = "disabled";
1390 };
1391
a334e781
SS		 1392 vspd0: vsp@fea20000 {
1393 compatible = "renesas,vsp2";
1394 reg = <0 0xfea20000 0 0x5000>;
1395 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1396 clocks = <&cpg CPG_MOD 623>;
1397 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1398 resets = <&cpg 623>;
1399 renesas,fcp = <&fcpvd0>;
1400 };
1401
1402 fcpvd0: fcp@fea27000 {
1403 compatible = "renesas,fcpv";
1404 reg = <0 0xfea27000 0 0x200>;
1405 clocks = <&cpg CPG_MOD 603>;
1406 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1407 resets = <&cpg 603>;
1408 };
1409
3182aa4e
SS		 1410 csi40: csi2@feaa0000 {
1411 compatible = "renesas,r8a77980-csi2";
1412 reg = <0 0xfeaa0000 0 0x10000>;
1413 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1414 clocks = <&cpg CPG_MOD 716>;
1415 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1416 resets = <&cpg 716>;
1417 status = "disabled";
1418
1419 ports {
1420 #address-cells = <1>;
1421 #size-cells = <0>;
1422
1423 port@1 {
1424 #address-cells = <1>;
1425 #size-cells = <0>;
1426
1427 reg = <1>;
1428
1429 csi40vin0: endpoint@0 {
1430 reg = <0>;
1431 remote-endpoint = <&vin0csi40>;
1432 };
1433 csi40vin1: endpoint@1 {
1434 reg = <1>;
1435 remote-endpoint = <&vin1csi40>;
1436 };
1437 csi40vin2: endpoint@2 {
1438 reg = <2>;
1439 remote-endpoint = <&vin2csi40>;
1440 };
1441 csi40vin3: endpoint@3 {
1442 reg = <3>;
1443 remote-endpoint = <&vin3csi40>;
1444 };
1445 };
1446 };
1447 };
1448
1449 csi41: csi2@feab0000 {
1450 compatible = "renesas,r8a77980-csi2";
1451 reg = <0 0xfeab0000 0 0x10000>;
1452 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1453 clocks = <&cpg CPG_MOD 715>;
1454 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1455 resets = <&cpg 715>;
1456 status = "disabled";
1457
1458 ports {
1459 #address-cells = <1>;
1460 #size-cells = <0>;
1461
1462 port@1 {
1463 #address-cells = <1>;
1464 #size-cells = <0>;
1465
1466 reg = <1>;
1467
1468 csi41vin4: endpoint@0 {
1469 reg = <0>;
1470 remote-endpoint = <&vin4csi41>;
1471 };
1472 csi41vin5: endpoint@1 {
1473 reg = <1>;
1474 remote-endpoint = <&vin5csi41>;
1475 };
1476 csi41vin6: endpoint@2 {
1477 reg = <2>;
1478 remote-endpoint = <&vin6csi41>;
1479 };
1480 csi41vin7: endpoint@3 {
1481 reg = <3>;
1482 remote-endpoint = <&vin7csi41>;
1483 };
1484 };
1485 };
1486 };
1487
a334e781 1488 du: display@feb00000 {
8e66f522 1489 compatible = "renesas,du-r8a77980";
a334e781
SS		 1490 reg = <0 0xfeb00000 0 0x80000>;
1491 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1492 clocks = <&cpg CPG_MOD 724>;
1493 clock-names = "du.0";
1494 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1495 resets = <&cpg 724>;
d745c72d 1496 reset-names = "du.0";
03abfdd3
GU		 1497 renesas,vsps = <&vspd0 0>;
1498
a334e781
SS		 1499 status = "disabled";
1500
1501 ports {
1502 #address-cells = <1>;
1503 #size-cells = <0>;
1504
1505 port@0 {
1506 reg = <0>;
1507 du_out_rgb: endpoint {
1508 };
1509 };
1510
1511 port@1 {
1512 reg = <1>;
1513 du_out_lvds0: endpoint {
1514 remote-endpoint = <&lvds0_in>;
1515 };
1516 };
1517 };
1518 };
1519
1520 lvds0: lvds-encoder@feb90000 {
1521 compatible = "renesas,r8a77980-lvds";
1522 reg = <0 0xfeb90000 0 0x14>;
1523 clocks = <&cpg CPG_MOD 727>;
1524 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1525 resets = <&cpg 727>;
1526 status = "disabled";
1527
1528 ports {
1529 #address-cells = <1>;
1530 #size-cells = <0>;
1531
1532 port@0 {
1533 reg = <0>;
1534 lvds0_in: endpoint {
1535 remote-endpoint =
1536 <&du_out_lvds0>;
1537 };
1538 };
1539
1540 port@1 {
1541 reg = <1>;
1542 lvds0_out: endpoint {
1543 };
1544 };
1545 };
1546 };
1547
f3a54d6c
SS		 1548 prr: chipid@fff00044 {
1549 compatible = "renesas,prr";
1550 reg = <0 0xfff00044 0 4>;
1551 };
1552 };
1553
69c5e602
SS		 1554 thermal-zones {
1555 thermal-sensor-1 {
1556 polling-delay-passive = <250>;
1557 polling-delay = <1000>;
1558 thermal-sensors = <&tsc 0>;
1559
1560 trips {
1561 sensor1-passive {
1562 temperature = <95000>;
1563 hysteresis = <1000>;
1564 type = "passive";
1565 };
1566 sensor1-critical {
1567 temperature = <120000>;
1568 hysteresis = <1000>;
1569 type = "critical";
1570 };
1571 };
1572 };
1573
1574 thermal-sensor-2 {
1575 polling-delay-passive = <250>;
1576 polling-delay = <1000>;
1577 thermal-sensors = <&tsc 1>;
1578
1579 trips {
1580 sensor2-passive {
1581 temperature = <95000>;
1582 hysteresis = <1000>;
1583 type = "passive";
1584 };
1585 sensor2-critical {
1586 temperature = <120000>;
1587 hysteresis = <1000>;
1588 type = "critical";
1589 };
1590 };
1591 };
1592 };
1593
f3a54d6c
SS		 1594 timer {
1595 compatible = "arm,armv8-timer";
2ec1e4b4 1596 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
f3a54d6c 1597 IRQ_TYPE_LEVEL_LOW)>,
2ec1e4b4 1598 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
f3a54d6c 1599 IRQ_TYPE_LEVEL_LOW)>,
2ec1e4b4 1600 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
f3a54d6c 1601 IRQ_TYPE_LEVEL_LOW)>,
2ec1e4b4 1602 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
f3a54d6c
SS		 1603 IRQ_TYPE_LEVEL_LOW)>;
1604 };
1605};
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