[thirdparty/linux.git] / arch / arm64 / boot / dts / renesas / r8a77990-ebisu.dts

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the ebisu board
 *
 * Copyright (C) 2018 Renesas Electronics Corp.
 */

/dts-v1/;
#include "r8a77990.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Renesas Ebisu board based on r8a77990";
	compatible = "renesas,ebisu", "renesas,r8a77990";

	aliases {
		serial0 = &scif2;
		ethernet0 = &avb;
	};

	chosen {
		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
		stdout-path = "serial0:115200n8";
	};

	audio_clkout: audio-clkout {
		/*
		 * This is same as <&rcar_sound 0>
		 * but needed to avoid cs2000/rcar_sound probe dead-lock
		 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <11289600>;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm3 0 50000>;

		brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
		default-brightness-level = <10>;

		power-supply = <&reg_12p0v>;
	};

	cvbs-in {
		compatible = "composite-video-connector";
		label = "CVBS IN";

		port {
			cvbs_con: endpoint {
				remote-endpoint = <&adv7482_ain7>;
			};
		};
	};

	hdmi-in {
		compatible = "hdmi-connector";
		label = "HDMI IN";
		type = "a";

		port {
			hdmi_in_con: endpoint {
				remote-endpoint = <&adv7482_hdmi>;
			};
		};
	};

	hdmi-out {
		compatible = "hdmi-connector";
		type = "a";

		port {
			hdmi_con_out: endpoint {
				remote-endpoint = <&adv7511_out>;
			};
		};
	};

	lvds-decoder {
		compatible = "thine,thc63lvd1024";
		vcc-supply = <&reg_3p3v>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				thc63lvd1024_in: endpoint {
					remote-endpoint = <&lvds0_out>;
				};
			};

			port@2 {
				reg = <2>;
				thc63lvd1024_out: endpoint {
					remote-endpoint = <&adv7511_in>;
				};
			};
		};
	};

	memory@48000000 {
		device_type = "memory";
		/* first 128MB is reserved for secure area. */
		reg = <0x0 0x48000000 0x0 0x38000000>;
	};

	reg_1p8v: regulator0 {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_3p3v: regulator1 {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_12p0v: regulator2 {
		compatible = "regulator-fixed";
		regulator-name = "D12.0V";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-boot-on;
		regulator-always-on;
	};

	rsnd_ak4613: sound {
		compatible = "simple-audio-card";

		simple-audio-card,name = "rsnd-ak4613";
		simple-audio-card,format = "left_j";
		simple-audio-card,bitclock-master = <&sndcpu>;
		simple-audio-card,frame-master = <&sndcpu>;

		sndcodec: simple-audio-card,codec {
			sound-dai = <&ak4613>;
		};

		sndcpu: simple-audio-card,cpu {
			sound-dai = <&rcar_sound>;
		};
	};

	vbus0_usb2: regulator-vbus0-usb2 {
		compatible = "regulator-fixed";

		regulator-name = "USB20_VBUS_CN";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;

		gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	vcc_sdhi0: regulator-vcc-sdhi0 {
		compatible = "regulator-fixed";

		regulator-name = "SDHI0 Vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	vccq_sdhi0: regulator-vccq-sdhi0 {
		compatible = "regulator-gpio";

		regulator-name = "SDHI0 VccQ";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;

		gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
		gpios-states = <1>;
		states = <3300000 1>, <1800000 0>;
	};

	vcc_sdhi1: regulator-vcc-sdhi1 {
		compatible = "regulator-fixed";

		regulator-name = "SDHI1 Vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	vccq_sdhi1: regulator-vccq-sdhi1 {
		compatible = "regulator-gpio";

		regulator-name = "SDHI1 VccQ";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;

		gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
		gpios-states = <1>;
		states = <3300000 1>, <1800000 0>;
	};

	vga {
		compatible = "vga-connector";

		port {
			vga_in: endpoint {
				remote-endpoint = <&adv7123_out>;
			};
		};
	};

	vga-encoder {
		compatible = "adi,adv7123";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				adv7123_in: endpoint {
					remote-endpoint = <&du_out_rgb>;
				};
			};
			port@1 {
				reg = <1>;
				adv7123_out: endpoint {
					remote-endpoint = <&vga_in>;
				};
			};
		};
	};

	x12_clk: x12 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24576000>;
	};

	x13_clk: x13 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <74250000>;
	};
};

&audio_clk_a {
	clock-frequency = <22579200>;
};

&avb {
	pinctrl-0 = <&avb_pins>;
	pinctrl-names = "default";
	phy-handle = <&phy0>;
	status = "okay";

	phy0: ethernet-phy@0 {
		rxc-skew-ps = <1500>;
		reg = <0>;
		interrupt-parent = <&gpio2>;
		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
		/*
		 * TX clock internal delay mode is required for reliable
		 * 1Gbps communication using the KSZ9031RNX phy present on
		 * the Ebisu board, however, TX clock internal delay mode
		 * isn't supported on r8a77990.  Thus, limit speed to
		 * 100Mbps for reliable communication.
		 */
		max-speed = <100>;
	};
};

&canfd {
	pinctrl-0 = <&canfd0_pins>;
	pinctrl-names = "default";
	status = "okay";

	channel0 {
		status = "okay";
	};
};

&csi40 {
	status = "okay";

	ports {
		port@0 {
			reg = <0>;

			csi40_in: endpoint {
				clock-lanes = <0>;
				data-lanes = <1 2>;
				remote-endpoint = <&adv7482_txa>;
			};
		};
	};
};

&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";
	status = "okay";

	clocks = <&cpg CPG_MOD 724>,
		 <&cpg CPG_MOD 723>,
		 <&x13_clk>;
	clock-names = "du.0", "du.1", "dclkin.0";

	ports {
		port@0 {
			endpoint {
				remote-endpoint = <&adv7123_in>;
			};
		};
	};
};

&ehci0 {
	dr_mode = "otg";
	status = "okay";
};

&extal_clk {
	clock-frequency = <48000000>;
};

&hsusb {
	dr_mode = "otg";
	status = "okay";
};

&i2c0 {
	status = "okay";

	io_expander: gpio@20 {
		compatible = "onnn,pca9654";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gpio2>;
		interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
	};

	hdmi-encoder@39 {
		compatible = "adi,adv7511w";
		reg = <0x39>;
		interrupt-parent = <&gpio1>;
		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;

		adi,input-depth = <8>;
		adi,input-colorspace = "rgb";
		adi,input-clock = "1x";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				adv7511_in: endpoint {
					remote-endpoint = <&thc63lvd1024_out>;
				};
			};

			port@1 {
				reg = <1>;
				adv7511_out: endpoint {
					remote-endpoint = <&hdmi_con_out>;
				};
			};
		};
	};

	video-receiver@70 {
		compatible = "adi,adv7482";
		reg = <0x70>;

		#address-cells = <1>;
		#size-cells = <0>;

		interrupt-parent = <&gpio0>;
		interrupt-names = "intrq1", "intrq2";
		interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
			     <17 IRQ_TYPE_LEVEL_LOW>;

		port@7 {
			reg = <7>;

			adv7482_ain7: endpoint {
				remote-endpoint = <&cvbs_con>;
			};
		};

		port@8 {
			reg = <8>;

			adv7482_hdmi: endpoint {
				remote-endpoint = <&hdmi_in_con>;
			};
		};

		port@a {
			reg = <10>;

			adv7482_txa: endpoint {
				clock-lanes = <0>;
				data-lanes = <1 2>;
				remote-endpoint = <&csi40_in>;
			};
		};
	};
};

&i2c3 {
	status = "okay";

	ak4613: codec@10 {
		compatible = "asahi-kasei,ak4613";
		#sound-dai-cells = <0>;
		reg = <0x10>;
		clocks = <&rcar_sound 3>;

		asahi-kasei,in1-single-end;
		asahi-kasei,in2-single-end;
		asahi-kasei,out1-single-end;
		asahi-kasei,out2-single-end;
		asahi-kasei,out3-single-end;
		asahi-kasei,out4-single-end;
		asahi-kasei,out5-single-end;
		asahi-kasei,out6-single-end;
	};

	cs2000: clk-multiplier@4f {
		#clock-cells = <0>;
		compatible = "cirrus,cs2000-cp";
		reg = <0x4f>;
		clocks = <&audio_clkout>, <&x12_clk>;
		clock-names = "clk_in", "ref_clk";

		assigned-clocks = <&cs2000>;
		assigned-clock-rates = <24576000>; /* 1/1 divide */
	};
};

&i2c_dvfs {
	status = "okay";

	clock-frequency = <400000>;

	pmic: pmic@30 {
		pinctrl-0 = <&irq0_pins>;
		pinctrl-names = "default";

		compatible = "rohm,bd9571mwv";
		reg = <0x30>;
		interrupt-parent = <&intc_ex>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;
		#interrupt-cells = <2>;
		gpio-controller;
		#gpio-cells = <2>;
		rohm,ddr-backup-power = <0x1>;
		rohm,rstbmode-level;
	};
};

&lvds0 {
	status = "okay";

	clocks = <&cpg CPG_MOD 727>,
		 <&x13_clk>,
		 <&extal_clk>;
	clock-names = "fck", "dclkin.0", "extal";

	ports {
		port@1 {
			lvds0_out: endpoint {
				remote-endpoint = <&thc63lvd1024_in>;
			};
		};
	};
};

&lvds1 {
	/*
	 * Even though the LVDS1 output is not connected, the encoder must be
	 * enabled to supply a pixel clock to the DU for the DPAD output when
	 * LVDS0 is in use.
	 */
	status = "okay";

	clocks = <&cpg CPG_MOD 727>,
		 <&x13_clk>,
		 <&extal_clk>;
	clock-names = "fck", "dclkin.0", "extal";
};

&ohci0 {
	dr_mode = "otg";
	status = "okay";
};

&pcie_bus_clk {
	clock-frequency = <100000000>;
};

&pciec0 {
	status = "okay";
};

&pfc {
	avb_pins: avb {
		mux {
			groups = "avb_link", "avb_mii";
			function = "avb";
		};
	};

	canfd0_pins: canfd0 {
		groups = "canfd0_data";
		function = "canfd0";
	};

	du_pins: du {
		groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
		function = "du";
	};

	irq0_pins: irq0 {
		groups = "intc_ex_irq0";
		function = "intc_ex";
	};

	pwm3_pins: pwm3 {
		groups = "pwm3_b";
		function = "pwm3";
	};

	pwm5_pins: pwm5 {
		groups = "pwm5_a";
		function = "pwm5";
	};

	scif2_pins: scif2 {
		groups = "scif2_data_a";
		function = "scif2";
	};

	sdhi0_pins: sd0 {
		groups = "sdhi0_data4", "sdhi0_ctrl";
		function = "sdhi0";
		power-source = <3300>;
	};

	sdhi0_pins_uhs: sd0_uhs {
		groups = "sdhi0_data4", "sdhi0_ctrl";
		function = "sdhi0";
		power-source = <1800>;
	};

	sdhi1_pins: sd1 {
		groups = "sdhi1_data4", "sdhi1_ctrl";
		function = "sdhi1";
		power-source = <3300>;
	};

	sdhi1_pins_uhs: sd1_uhs {
		groups = "sdhi1_data4", "sdhi1_ctrl";
		function = "sdhi1";
		power-source = <1800>;
	};

	sdhi3_pins: sd3 {
		groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
		function = "sdhi3";
		power-source = <1800>;
	};

	sound_clk_pins: sound_clk {
		groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
			 "audio_clkout_a", "audio_clkout1_a";
		function = "audio_clk";
	};

	sound_pins: sound {
		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
		function = "ssi";
	};

	usb0_pins: usb {
		groups = "usb0_b", "usb0_id";
		function = "usb0";
	};

	usb30_pins: usb30 {
		groups = "usb30";
		function = "usb30";
	};
};

&pwm3 {
	pinctrl-0 = <&pwm3_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&pwm5 {
	pinctrl-0 = <&pwm5_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&rcar_sound {
	pinctrl-0 = <&sound_pins &sound_clk_pins>;
	pinctrl-names = "default";

	/* Single DAI */
	#sound-dai-cells = <0>;

	/* audio_clkout0/1/2/3 */
	#clock-cells = <1>;
	clock-frequency = <12288000 11289600>;

	status = "okay";

	/* update <audio_clk_b> to <cs2000> */
	clocks = <&cpg CPG_MOD 1005>,
		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
		 <&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
		 <&cpg CPG_CORE R8A77990_CLK_ZA2>;

	rcar_sound,dai {
		dai0 {
			playback = <&ssi0 &src0 &dvc0>;
			capture  = <&ssi1 &src1 &dvc1>;
		};
	};

};

&rwdt {
	timeout-sec = <60>;
	status = "okay";
};

&scif2 {
	pinctrl-0 = <&scif2_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-1 = <&sdhi0_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi0>;
	vqmmc-supply = <&vccq_sdhi0>;
	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
	bus-width = <4>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
};

&sdhi1 {
	pinctrl-0 = <&sdhi1_pins>;
	pinctrl-1 = <&sdhi1_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi1>;
	vqmmc-supply = <&vccq_sdhi1>;
	cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
};

&sdhi3 {
	/* used for on-board 8bit eMMC */
	pinctrl-0 = <&sdhi3_pins>;
	pinctrl-1 = <&sdhi3_pins>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_1p8v>;
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&ssi1 {
	shared-pin;
};

&usb2_phy0 {
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";

	vbus-supply = <&vbus0_usb2>;
	status = "okay";
};

&usb3_peri0 {
	companion = <&xhci0>;
	status = "okay";
};

&vin4 {
	status = "okay";
};

&vin5 {
	status = "okay";
};

&xhci0 {
	pinctrl-0 = <&usb30_pins>;
	pinctrl-names = "default";

	status = "okay";
};
Commit	Line	Data
b068ed6e	1	// SPDX-License-Identifier: GPL-2.0
77049191 TK	2	/*
	3	* Device Tree Source for the ebisu board
	4	*
	5	* Copyright (C) 2018 Renesas Electronics Corp.
	6	*/
	7
	8	/dts-v1/;
	9	#include "r8a77990.dtsi"
8441ef64	10	#include <dt-bindings/gpio/gpio.h>
77049191 TK	11
	12	/ {
	13	model = "Renesas Ebisu board based on r8a77990";
	14	compatible = "renesas,ebisu", "renesas,r8a77990";
	15
	16	aliases {
	17	serial0 = &scif2;
8441ef64	18	ethernet0 = &avb;
77049191 TK	19	};
	20
	21	chosen {
b31b43c9	22	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
77049191 TK	23	stdout-path = "serial0:115200n8";
	24	};
	25
56629fcb TK	26	audio_clkout: audio-clkout {
	27	/*
	28	* This is same as <&rcar_sound 0>
	29	* but needed to avoid cs2000/rcar_sound probe dead-lock
	30	*/
	31	compatible = "fixed-clock";
	32	#clock-cells = <0>;
	33	clock-frequency = <11289600>;
	34	};
	35
9d16c4a1 LP	36	backlight: backlight {
	37	compatible = "pwm-backlight";
	38	pwms = <&pwm3 0 50000>;
	39
	40	brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
	41	default-brightness-level = <10>;
	42
	43	power-supply = <&reg_12p0v>;
	44	};
	45
a1d354a7 JM	46	cvbs-in {
	47	compatible = "composite-video-connector";
	48	label = "CVBS IN";
	49
	50	port {
	51	cvbs_con: endpoint {
	52	remote-endpoint = <&adv7482_ain7>;
	53	};
	54	};
	55	};
	56
	57	hdmi-in {
	58	compatible = "hdmi-connector";
	59	label = "HDMI IN";
	60	type = "a";
	61
	62	port {
	63	hdmi_in_con: endpoint {
	64	remote-endpoint = <&adv7482_hdmi>;
	65	};
	66	};
	67	};
74fe39ab LP	68
	69	hdmi-out {
	70	compatible = "hdmi-connector";
	71	type = "a";
	72
	73	port {
	74	hdmi_con_out: endpoint {
	75	remote-endpoint = <&adv7511_out>;
	76	};
	77	};
	78	};
	79
	80	lvds-decoder {
	81	compatible = "thine,thc63lvd1024";
	82	vcc-supply = <&reg_3p3v>;
	83
	84	ports {
	85	#address-cells = <1>;
	86	#size-cells = <0>;
	87
	88	port@0 {
	89	reg = <0>;
	90	thc63lvd1024_in: endpoint {
	91	remote-endpoint = <&lvds0_out>;
	92	};
	93	};
	94
	95	port@2 {
	96	reg = <2>;
	97	thc63lvd1024_out: endpoint {
	98	remote-endpoint = <&adv7511_in>;
	99	};
	100	};
	101	};
	102	};
	103
880925e8 YK	104	memory@48000000 {
	105	device_type = "memory";
	106	/* first 128MB is reserved for secure area. */
	107	reg = <0x0 0x48000000 0x0 0x38000000>;
74fe39ab LP	108	};
74fe39ab LP	109
9aa3558a TK	110	reg_1p8v: regulator0 {
	111	compatible = "regulator-fixed";
	112	regulator-name = "fixed-1.8V";
	113	regulator-min-microvolt = <1800000>;
	114	regulator-max-microvolt = <1800000>;
	115	regulator-boot-on;
	116	regulator-always-on;
	117	};
	118
74fe39ab LP	119	reg_3p3v: regulator1 {
	120	compatible = "regulator-fixed";
	121	regulator-name = "fixed-3.3V";
	122	regulator-min-microvolt = <3300000>;
	123	regulator-max-microvolt = <3300000>;
	124	regulator-boot-on;
	125	regulator-always-on;
	126	};
	127
880925e8	128	reg_12p0v: regulator2 {
5c6479d9	129	compatible = "regulator-fixed";
880925e8 YK	130	regulator-name = "D12.0V";
	131	regulator-min-microvolt = <12000000>;
	132	regulator-max-microvolt = <12000000>;
	133	regulator-boot-on;
	134	regulator-always-on;
5c6479d9 YS	135	};
5c6479d9 YS	136
56629fcb	137	rsnd_ak4613: sound {
868a49d6	138	compatible = "simple-audio-card";
56629fcb TK	139
	140	simple-audio-card,name = "rsnd-ak4613";
	141	simple-audio-card,format = "left_j";
	142	simple-audio-card,bitclock-master = <&sndcpu>;
	143	simple-audio-card,frame-master = <&sndcpu>;
	144
56629fcb TK	145	sndcodec: simple-audio-card,codec {
	146	sound-dai = <&ak4613>;
	147	};
56629fcb	148
880925e8 YK	149	sndcpu: simple-audio-card,cpu {
	150	sound-dai = <&rcar_sound>;
	151	};
56629fcb TK	152	};
56629fcb TK	153
880925e8	154	vbus0_usb2: regulator-vbus0-usb2 {
9d16c4a1	155	compatible = "regulator-fixed";
9d16c4a1	156
880925e8 YK	157	regulator-name = "USB20_VBUS_CN";
	158	regulator-min-microvolt = <5000000>;
	159	regulator-max-microvolt = <5000000>;
	160
	161	gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
	162	enable-active-high;
74fe39ab	163	};
9aa3558a TK	164
	165	vcc_sdhi0: regulator-vcc-sdhi0 {
	166	compatible = "regulator-fixed";
	167
	168	regulator-name = "SDHI0 Vcc";
	169	regulator-min-microvolt = <3300000>;
	170	regulator-max-microvolt = <3300000>;
	171
	172	gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
	173	enable-active-high;
	174	};
	175
	176	vccq_sdhi0: regulator-vccq-sdhi0 {
	177	compatible = "regulator-gpio";
	178
	179	regulator-name = "SDHI0 VccQ";
	180	regulator-min-microvolt = <1800000>;
	181	regulator-max-microvolt = <3300000>;
	182
	183	gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
	184	gpios-states = <1>;
36f06212	185	states = <3300000 1>, <1800000 0>;
9aa3558a TK	186	};
	187
	188	vcc_sdhi1: regulator-vcc-sdhi1 {
	189	compatible = "regulator-fixed";
	190
	191	regulator-name = "SDHI1 Vcc";
	192	regulator-min-microvolt = <3300000>;
	193	regulator-max-microvolt = <3300000>;
	194
	195	gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
	196	enable-active-high;
	197	};
	198
	199	vccq_sdhi1: regulator-vccq-sdhi1 {
	200	compatible = "regulator-gpio";
	201
	202	regulator-name = "SDHI1 VccQ";
	203	regulator-min-microvolt = <1800000>;
	204	regulator-max-microvolt = <3300000>;
	205
	206	gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
	207	gpios-states = <1>;
36f06212	208	states = <3300000 1>, <1800000 0>;
9aa3558a	209	};
880925e8 YK	210
	211	vga {
	212	compatible = "vga-connector";
	213
	214	port {
	215	vga_in: endpoint {
	216	remote-endpoint = <&adv7123_out>;
	217	};
	218	};
	219	};
	220
	221	vga-encoder {
	222	compatible = "adi,adv7123";
	223
	224	ports {
	225	#address-cells = <1>;
	226	#size-cells = <0>;
	227
	228	port@0 {
	229	reg = <0>;
	230	adv7123_in: endpoint {
	231	remote-endpoint = <&du_out_rgb>;
	232	};
	233	};
	234	port@1 {
	235	reg = <1>;
	236	adv7123_out: endpoint {
	237	remote-endpoint = <&vga_in>;
	238	};
	239	};
	240	};
	241	};
	242
	243	x12_clk: x12 {
	244	compatible = "fixed-clock";
	245	#clock-cells = <0>;
	246	clock-frequency = <24576000>;
	247	};
	248
	249	x13_clk: x13 {
	250	compatible = "fixed-clock";
	251	#clock-cells = <0>;
	252	clock-frequency = <74250000>;
	253	};
77049191 TK	254	};
77049191 TK	255
56629fcb TK	256	&audio_clk_a {
	257	clock-frequency = <22579200>;
	258	};
	259
8441ef64 YS	260	&avb {
	261	pinctrl-0 = <&avb_pins>;
	262	pinctrl-names = "default";
8441ef64	263	phy-handle = <&phy0>;
8441ef64 YS	264	status = "okay";
	265
	266	phy0: ethernet-phy@0 {
	267	rxc-skew-ps = <1500>;
	268	reg = <0>;
	269	interrupt-parent = <&gpio2>;
	270	interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
	271	reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
8703ba77 SH	272	/*
	273	* TX clock internal delay mode is required for reliable
	274	* 1Gbps communication using the KSZ9031RNX phy present on
	275	* the Ebisu board, however, TX clock internal delay mode
	276	* isn't supported on r8a77990. Thus, limit speed to
	277	* 100Mbps for reliable communication.
	278	*/
	279	max-speed = <100>;
8441ef64 YS	280	};
	281	};
	282
327d1f32 MV	283	&canfd {
	284	pinctrl-0 = <&canfd0_pins>;
	285	pinctrl-names = "default";
	286	status = "okay";
	287
	288	channel0 {
	289	status = "okay";
	290	};
	291	};
	292
a1d354a7 JM	293	&csi40 {
	294	status = "okay";
	295
	296	ports {
	297	port@0 {
	298	reg = <0>;
	299
	300	csi40_in: endpoint {
	301	clock-lanes = <0>;
	302	data-lanes = <1 2>;
	303	remote-endpoint = <&adv7482_txa>;
	304	};
	305	};
	306	};
	307	};
	308
74fe39ab LP	309	&du {
	310	pinctrl-0 = <&du_pins>;
	311	pinctrl-names = "default";
	312	status = "okay";
	313
	314	clocks = <&cpg CPG_MOD 724>,
	315	<&cpg CPG_MOD 723>,
	316	<&x13_clk>;
	317	clock-names = "du.0", "du.1", "dclkin.0";
	318
	319	ports {
	320	port@0 {
	321	endpoint {
	322	remote-endpoint = <&adv7123_in>;
	323	};
	324	};
	325	};
	326	};
	327
6dd72b4d	328	&ehci0 {
5c6479d9	329	dr_mode = "otg";
6dd72b4d YS	330	status = "okay";
	331	};
	332
77049191 TK	333	&extal_clk {
	334	clock-frequency = <48000000>;
	335	};
	336
5c6479d9 YS	337	&hsusb {
	338	dr_mode = "otg";
	339	status = "okay";
	340	};
	341
a1d354a7 JM	342	&i2c0 {
	343	status = "okay";
	344
6fffb986 GU	345	io_expander: gpio@20 {
	346	compatible = "onnn,pca9654";
	347	reg = <0x20>;
	348	gpio-controller;
	349	#gpio-cells = <2>;
	350	interrupt-parent = <&gpio2>;
	351	interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
	352	};
	353
74fe39ab LP	354	hdmi-encoder@39 {
	355	compatible = "adi,adv7511w";
	356	reg = <0x39>;
	357	interrupt-parent = <&gpio1>;
	358	interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
	359
	360	adi,input-depth = <8>;
	361	adi,input-colorspace = "rgb";
	362	adi,input-clock = "1x";
74fe39ab LP	363
	364	ports {
	365	#address-cells = <1>;
	366	#size-cells = <0>;
	367
	368	port@0 {
	369	reg = <0>;
	370	adv7511_in: endpoint {
	371	remote-endpoint = <&thc63lvd1024_out>;
	372	};
	373	};
	374
	375	port@1 {
	376	reg = <1>;
	377	adv7511_out: endpoint {
	378	remote-endpoint = <&hdmi_con_out>;
	379	};
	380	};
	381	};
	382	};
	383
a1d354a7 JM	384	video-receiver@70 {
	385	compatible = "adi,adv7482";
	386	reg = <0x70>;
	387
	388	#address-cells = <1>;
	389	#size-cells = <0>;
	390
	391	interrupt-parent = <&gpio0>;
	392	interrupt-names = "intrq1", "intrq2";
	393	interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
	394	<17 IRQ_TYPE_LEVEL_LOW>;
	395
	396	port@7 {
	397	reg = <7>;
	398
	399	adv7482_ain7: endpoint {
	400	remote-endpoint = <&cvbs_con>;
	401	};
	402	};
	403
	404	port@8 {
	405	reg = <8>;
	406
	407	adv7482_hdmi: endpoint {
	408	remote-endpoint = <&hdmi_in_con>;
	409	};
	410	};
	411
	412	port@a {
9130c158	413	reg = <10>;
a1d354a7 JM	414
	415	adv7482_txa: endpoint {
	416	clock-lanes = <0>;
	417	data-lanes = <1 2>;
	418	remote-endpoint = <&csi40_in>;
	419	};
	420	};
	421	};
	422	};
	423
56629fcb TK	424	&i2c3 {
	425	status = "okay";
	426
	427	ak4613: codec@10 {
	428	compatible = "asahi-kasei,ak4613";
	429	#sound-dai-cells = <0>;
	430	reg = <0x10>;
	431	clocks = <&rcar_sound 3>;
	432
	433	asahi-kasei,in1-single-end;
	434	asahi-kasei,in2-single-end;
	435	asahi-kasei,out1-single-end;
	436	asahi-kasei,out2-single-end;
	437	asahi-kasei,out3-single-end;
	438	asahi-kasei,out4-single-end;
	439	asahi-kasei,out5-single-end;
	440	asahi-kasei,out6-single-end;
	441	};
	442
	443	cs2000: clk-multiplier@4f {
	444	#clock-cells = <0>;
	445	compatible = "cirrus,cs2000-cp";
	446	reg = <0x4f>;
	447	clocks = <&audio_clkout>, <&x12_clk>;
	448	clock-names = "clk_in", "ref_clk";
	449
	450	assigned-clocks = <&cs2000>;
	451	assigned-clock-rates = <24576000>; /* 1/1 divide */
	452	};
	453	};
	454
1f4c123a TK	455	&i2c_dvfs {
	456	status = "okay";
	457
	458	clock-frequency = <400000>;
	459
	460	pmic: pmic@30 {
	461	pinctrl-0 = <&irq0_pins>;
	462	pinctrl-names = "default";
	463
	464	compatible = "rohm,bd9571mwv";
	465	reg = <0x30>;
	466	interrupt-parent = <&intc_ex>;
	467	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	468	interrupt-controller;
	469	#interrupt-cells = <2>;
	470	gpio-controller;
	471	#gpio-cells = <2>;
47470611 SH	472	rohm,ddr-backup-power = <0x1>;
47470611 SH	473	rohm,rstbmode-level;
1f4c123a TK	474	};
	475	};
	476
74fe39ab LP	477	&lvds0 {
	478	status = "okay";
	479
	480	clocks = <&cpg CPG_MOD 727>,
	481	<&x13_clk>,
	482	<&extal_clk>;
	483	clock-names = "fck", "dclkin.0", "extal";
	484
	485	ports {
	486	port@1 {
	487	lvds0_out: endpoint {
	488	remote-endpoint = <&thc63lvd1024_in>;
	489	};
	490	};
	491	};
	492	};
	493
	494	&lvds1 {
71ac75df LP	495	/*
	496	* Even though the LVDS1 output is not connected, the encoder must be
	497	* enabled to supply a pixel clock to the DU for the DPAD output when
	498	* LVDS0 is in use.
	499	*/
	500	status = "okay";
	501
74fe39ab LP	502	clocks = <&cpg CPG_MOD 727>,
	503	<&x13_clk>,
	504	<&extal_clk>;
	505	clock-names = "fck", "dclkin.0", "extal";
	506	};
	507
6dd72b4d	508	&ohci0 {
5c6479d9	509	dr_mode = "otg";
6dd72b4d YS	510	status = "okay";
	511	};
	512
ba3ac35b TK	513	&pcie_bus_clk {
	514	clock-frequency = <100000000>;
	515	};
	516
	517	&pciec0 {
	518	status = "okay";
	519	};
	520
8441ef64 YS	521	&pfc {
	522	avb_pins: avb {
	523	mux {
	524	groups = "avb_link", "avb_mii";
	525	function = "avb";
	526	};
	527	};
6dd72b4d	528
327d1f32 MV	529	canfd0_pins: canfd0 {
	530	groups = "canfd0_data";
	531	function = "canfd0";
	532	};
	533
74fe39ab LP	534	du_pins: du {
	535	groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
	536	function = "du";
	537	};
	538
1f4c123a TK	539	irq0_pins: irq0 {
	540	groups = "intc_ex_irq0";
	541	function = "intc_ex";
	542	};
	543
18048556 YS	544	pwm3_pins: pwm3 {
	545	groups = "pwm3_b";
	546	function = "pwm3";
	547	};
	548
	549	pwm5_pins: pwm5 {
	550	groups = "pwm5_a";
	551	function = "pwm5";
	552	};
	553
880925e8 YK	554	scif2_pins: scif2 {
	555	groups = "scif2_data_a";
	556	function = "scif2";
	557	};
	558
9aa3558a TK	559	sdhi0_pins: sd0 {
	560	groups = "sdhi0_data4", "sdhi0_ctrl";
	561	function = "sdhi0";
	562	power-source = <3300>;
	563	};
	564
	565	sdhi0_pins_uhs: sd0_uhs {
	566	groups = "sdhi0_data4", "sdhi0_ctrl";
	567	function = "sdhi0";
	568	power-source = <1800>;
	569	};
	570
	571	sdhi1_pins: sd1 {
	572	groups = "sdhi1_data4", "sdhi1_ctrl";
	573	function = "sdhi1";
	574	power-source = <3300>;
	575	};
	576
	577	sdhi1_pins_uhs: sd1_uhs {
	578	groups = "sdhi1_data4", "sdhi1_ctrl";
	579	function = "sdhi1";
	580	power-source = <1800>;
	581	};
	582
	583	sdhi3_pins: sd3 {
	584	groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
	585	function = "sdhi3";
	586	power-source = <1800>;
	587	};
	588
56629fcb TK	589	sound_clk_pins: sound_clk {
	590	groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
	591	"audio_clkout_a", "audio_clkout1_a";
	592	function = "audio_clk";
	593	};
	594
880925e8 YK	595	sound_pins: sound {
	596	groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
	597	function = "ssi";
f3962b82 TK	598	};
f3962b82 TK	599
6dd72b4d	600	usb0_pins: usb {
5c6479d9	601	groups = "usb0_b", "usb0_id";
6dd72b4d YS	602	function = "usb0";
6dd72b4d YS	603	};
fe1bc94a YS	604
	605	usb30_pins: usb30 {
	606	groups = "usb30";
	607	function = "usb30";
	608	};
8441ef64 YS	609	};
8441ef64 YS	610
18048556 YS	611	&pwm3 {
	612	pinctrl-0 = <&pwm3_pins>;
	613	pinctrl-names = "default";
	614
	615	status = "okay";
	616	};
	617
	618	&pwm5 {
	619	pinctrl-0 = <&pwm5_pins>;
	620	pinctrl-names = "default";
	621
	622	status = "okay";
	623	};
	624
56629fcb TK	625	&rcar_sound {
	626	pinctrl-0 = <&sound_pins &sound_clk_pins>;
	627	pinctrl-names = "default";
	628
	629	/* Single DAI */
	630	#sound-dai-cells = <0>;
	631
	632	/* audio_clkout0/1/2/3 */
	633	#clock-cells = <1>;
	634	clock-frequency = <12288000 11289600>;
56629fcb TK	635
	636	status = "okay";
	637
	638	/* update <audio_clk_b> to <cs2000> */
	639	clocks = <&cpg CPG_MOD 1005>,
	640	<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
	641	<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
	642	<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
	643	<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
	644	<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
	645	<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
	646	<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
	647	<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
	648	<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
	649	<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
	650	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	651	<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
	652	<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
	653	<&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
	654	<&cpg CPG_CORE R8A77990_CLK_ZA2>;
	655
	656	rcar_sound,dai {
	657	dai0 {
	658	playback = <&ssi0 &src0 &dvc0>;
	659	capture = <&ssi1 &src1 &dvc1>;
	660	};
	661	};
	662
	663	};
	664
eb614d94 TK	665	&rwdt {
	666	timeout-sec = <60>;
	667	status = "okay";
	668	};
	669
77049191	670	&scif2 {
f3962b82 TK	671	pinctrl-0 = <&scif2_pins>;
	672	pinctrl-names = "default";
	673
77049191 TK	674	status = "okay";
77049191 TK	675	};
6dd72b4d	676
9aa3558a TK	677	&sdhi0 {
	678	pinctrl-0 = <&sdhi0_pins>;
	679	pinctrl-1 = <&sdhi0_pins_uhs>;
	680	pinctrl-names = "default", "state_uhs";
	681
	682	vmmc-supply = <&vcc_sdhi0>;
	683	vqmmc-supply = <&vccq_sdhi0>;
	684	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
	685	wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
	686	bus-width = <4>;
	687	sd-uhs-sdr50;
	688	sd-uhs-sdr104;
	689	status = "okay";
	690	};
	691
	692	&sdhi1 {
	693	pinctrl-0 = <&sdhi1_pins>;
	694	pinctrl-1 = <&sdhi1_pins_uhs>;
	695	pinctrl-names = "default", "state_uhs";
	696
	697	vmmc-supply = <&vcc_sdhi1>;
	698	vqmmc-supply = <&vccq_sdhi1>;
	699	cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
	700	bus-width = <4>;
	701	sd-uhs-sdr50;
	702	sd-uhs-sdr104;
	703	status = "okay";
	704	};
	705
	706	&sdhi3 {
	707	/* used for on-board 8bit eMMC */
	708	pinctrl-0 = <&sdhi3_pins>;
	709	pinctrl-1 = <&sdhi3_pins>;
	710	pinctrl-names = "default", "state_uhs";
	711
	712	vmmc-supply = <&reg_3p3v>;
	713	vqmmc-supply = <&reg_1p8v>;
	714	mmc-hs200-1_8v;
3e279a1d	715	mmc-hs400-1_8v;
9aa3558a TK	716	bus-width = <8>;
	717	non-removable;
	718	status = "okay";
	719	};
880925e8 YK	720
	721	&ssi1 {
	722	shared-pin;
	723	};
	724
	725	&usb2_phy0 {
	726	pinctrl-0 = <&usb0_pins>;
	727	pinctrl-names = "default";
	728
	729	vbus-supply = <&vbus0_usb2>;
	730	status = "okay";
	731	};
	732
	733	&usb3_peri0 {
	734	companion = <&xhci0>;
	735	status = "okay";
	736	};
	737
	738	&vin4 {
	739	status = "okay";
	740	};
	741
	742	&vin5 {
	743	status = "okay";
	744	};
	745
	746	&xhci0 {
	747	pinctrl-0 = <&usb30_pins>;
	748	pinctrl-names = "default";
	749
	750	status = "okay";
	751	};