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Commit | Line | Data |
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cba59c25 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c550443f GU |
2 | /* |
3 | * Device Tree Source for the Draak board | |
4 | * | |
bcf30034 | 5 | * Copyright (C) 2016-2018 Renesas Electronics Corp. |
c550443f | 6 | * Copyright (C) 2017 Glider bvba |
c550443f GU |
7 | */ |
8 | ||
9 | /dts-v1/; | |
10 | #include "r8a77995.dtsi" | |
4503b50e | 11 | #include <dt-bindings/gpio/gpio.h> |
c550443f GU |
12 | |
13 | / { | |
14 | model = "Renesas Draak board based on r8a77995"; | |
15 | compatible = "renesas,draak", "renesas,r8a77995"; | |
16 | ||
17 | aliases { | |
18 | serial0 = &scif2; | |
4503b50e | 19 | ethernet0 = &avb; |
c550443f GU |
20 | }; |
21 | ||
4fbd4158 LP |
22 | backlight: backlight { |
23 | compatible = "pwm-backlight"; | |
24 | pwms = <&pwm1 0 50000>; | |
25 | ||
a06ad438 LP |
26 | brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>; |
27 | default-brightness-level = <10>; | |
4fbd4158 LP |
28 | |
29 | power-supply = <®_12p0v>; | |
30 | enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; | |
31 | }; | |
32 | ||
1ab0a43a YK |
33 | chosen { |
34 | bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; | |
35 | stdout-path = "serial0:115200n8"; | |
36 | }; | |
37 | ||
6a0942c2 JM |
38 | composite-in { |
39 | compatible = "composite-video-connector"; | |
40 | ||
41 | port { | |
42 | composite_con_in: endpoint { | |
43 | remote-endpoint = <&adv7180_in>; | |
44 | }; | |
45 | }; | |
46 | }; | |
47 | ||
1b1b30a2 JM |
48 | hdmi-in { |
49 | compatible = "hdmi-connector"; | |
50 | type = "a"; | |
51 | ||
52 | port { | |
53 | hdmi_con_in: endpoint { | |
54 | remote-endpoint = <&adv7612_in>; | |
55 | }; | |
56 | }; | |
57 | }; | |
58 | ||
bcf30034 UH |
59 | hdmi-out { |
60 | compatible = "hdmi-connector"; | |
61 | type = "a"; | |
62 | ||
63 | port { | |
64 | hdmi_con_out: endpoint { | |
65 | remote-endpoint = <&adv7511_out>; | |
66 | }; | |
67 | }; | |
68 | }; | |
69 | ||
70 | lvds-decoder { | |
71 | compatible = "thine,thc63lvd1024"; | |
72 | vcc-supply = <®_3p3v>; | |
73 | ||
74 | ports { | |
75 | #address-cells = <1>; | |
76 | #size-cells = <0>; | |
77 | ||
78 | port@0 { | |
79 | reg = <0>; | |
80 | thc63lvd1024_in: endpoint { | |
81 | remote-endpoint = <&lvds0_out>; | |
82 | }; | |
83 | }; | |
84 | ||
85 | port@2 { | |
86 | reg = <2>; | |
87 | thc63lvd1024_out: endpoint { | |
88 | remote-endpoint = <&adv7511_in>; | |
89 | }; | |
90 | }; | |
91 | }; | |
92 | }; | |
93 | ||
c550443f GU |
94 | memory@48000000 { |
95 | device_type = "memory"; | |
96 | /* first 128MB is reserved for secure area. */ | |
97 | reg = <0x0 0x48000000 0x0 0x18000000>; | |
98 | }; | |
9d9505a2 | 99 | |
45f5d5a9 | 100 | reg_1p8v: regulator-1p8v { |
9d9505a2 UH |
101 | compatible = "regulator-fixed"; |
102 | regulator-name = "fixed-1.8V"; | |
103 | regulator-min-microvolt = <1800000>; | |
104 | regulator-max-microvolt = <1800000>; | |
105 | regulator-boot-on; | |
106 | regulator-always-on; | |
107 | }; | |
108 | ||
45f5d5a9 | 109 | reg_3p3v: regulator-3p3v { |
9d9505a2 UH |
110 | compatible = "regulator-fixed"; |
111 | regulator-name = "fixed-3.3V"; | |
112 | regulator-min-microvolt = <3300000>; | |
113 | regulator-max-microvolt = <3300000>; | |
114 | regulator-boot-on; | |
115 | regulator-always-on; | |
116 | }; | |
856e7e42 | 117 | |
45f5d5a9 | 118 | reg_12p0v: regulator-12p0v { |
4fbd4158 LP |
119 | compatible = "regulator-fixed"; |
120 | regulator-name = "D12.0V"; | |
121 | regulator-min-microvolt = <12000000>; | |
122 | regulator-max-microvolt = <12000000>; | |
123 | regulator-boot-on; | |
124 | regulator-always-on; | |
125 | }; | |
126 | ||
7acc17b1 GU |
127 | vga { |
128 | compatible = "vga-connector"; | |
c550443f | 129 | |
7acc17b1 GU |
130 | port { |
131 | vga_in: endpoint { | |
132 | remote-endpoint = <&adv7123_out>; | |
133 | }; | |
4503b50e YS |
134 | }; |
135 | }; | |
136 | ||
7acc17b1 GU |
137 | vga-encoder { |
138 | compatible = "adi,adv7123"; | |
cfdec2af | 139 | |
7acc17b1 GU |
140 | ports { |
141 | #address-cells = <1>; | |
142 | #size-cells = <0>; | |
86e7a972 | 143 | |
7acc17b1 GU |
144 | port@0 { |
145 | reg = <0>; | |
146 | adv7123_in: endpoint { | |
147 | remote-endpoint = <&du_out_rgb>; | |
148 | }; | |
149 | }; | |
150 | port@1 { | |
151 | reg = <1>; | |
152 | adv7123_out: endpoint { | |
153 | remote-endpoint = <&vga_in>; | |
154 | }; | |
155 | }; | |
156 | }; | |
41337aa1 UH |
157 | }; |
158 | ||
7acc17b1 GU |
159 | x12_clk: x12 { |
160 | compatible = "fixed-clock"; | |
161 | #clock-cells = <0>; | |
162 | clock-frequency = <74250000>; | |
b3533444 | 163 | }; |
7acc17b1 | 164 | }; |
b3533444 | 165 | |
7acc17b1 GU |
166 | &avb { |
167 | pinctrl-0 = <&avb0_pins>; | |
168 | pinctrl-names = "default"; | |
169 | renesas,no-ether-link; | |
170 | phy-handle = <&phy0>; | |
7acc17b1 | 171 | status = "okay"; |
b3533444 | 172 | |
7acc17b1 GU |
173 | phy0: ethernet-phy@0 { |
174 | rxc-skew-ps = <1500>; | |
175 | reg = <0>; | |
176 | interrupt-parent = <&gpio5>; | |
177 | interrupts = <19 IRQ_TYPE_LEVEL_LOW>; | |
8703ba77 SH |
178 | /* |
179 | * TX clock internal delay mode is required for reliable | |
180 | * 1Gbps communication using the KSZ9031RNX phy present on | |
181 | * the Draak board, however, TX clock internal delay mode | |
182 | * isn't supported on r8a77995. Thus, limit speed to | |
183 | * 100Mbps for reliable communication. | |
184 | */ | |
185 | max-speed = <100>; | |
ea203404 | 186 | }; |
7acc17b1 | 187 | }; |
ea203404 | 188 | |
4162aa9d MV |
189 | &can0 { |
190 | pinctrl-0 = <&can0_pins>; | |
191 | pinctrl-names = "default"; | |
192 | status = "okay"; | |
193 | }; | |
194 | ||
195 | &can1 { | |
196 | pinctrl-0 = <&can1_pins>; | |
197 | pinctrl-names = "default"; | |
198 | status = "okay"; | |
199 | }; | |
200 | ||
7acc17b1 GU |
201 | &du { |
202 | pinctrl-0 = <&du_pins>; | |
203 | pinctrl-names = "default"; | |
204 | status = "okay"; | |
9d9505a2 | 205 | |
7acc17b1 GU |
206 | clocks = <&cpg CPG_MOD 724>, |
207 | <&cpg CPG_MOD 723>, | |
208 | <&x12_clk>; | |
209 | clock-names = "du.0", "du.1", "dclkin.0"; | |
9d9505a2 | 210 | |
7acc17b1 GU |
211 | ports { |
212 | port@0 { | |
213 | endpoint { | |
214 | remote-endpoint = <&adv7123_in>; | |
215 | }; | |
216 | }; | |
34f058b2 | 217 | }; |
7acc17b1 | 218 | }; |
6a0942c2 | 219 | |
7acc17b1 | 220 | &ehci0 { |
5c6479d9 | 221 | dr_mode = "host"; |
7acc17b1 GU |
222 | status = "okay"; |
223 | }; | |
224 | ||
225 | &extal_clk { | |
226 | clock-frequency = <48000000>; | |
ea203404 GU |
227 | }; |
228 | ||
5c6479d9 YS |
229 | &hsusb { |
230 | dr_mode = "host"; | |
231 | status = "okay"; | |
232 | }; | |
233 | ||
86e7a972 UH |
234 | &i2c0 { |
235 | pinctrl-0 = <&i2c0_pins>; | |
236 | pinctrl-names = "default"; | |
237 | status = "okay"; | |
238 | ||
6a0942c2 JM |
239 | composite-in@20 { |
240 | compatible = "adi,adv7180cp"; | |
241 | reg = <0x20>; | |
242 | ||
6f61a2c8 | 243 | ports { |
6a0942c2 JM |
244 | #address-cells = <1>; |
245 | #size-cells = <0>; | |
246 | ||
247 | port@0 { | |
248 | reg = <0>; | |
249 | adv7180_in: endpoint { | |
250 | remote-endpoint = <&composite_con_in>; | |
251 | }; | |
252 | }; | |
253 | ||
254 | port@3 { | |
255 | reg = <3>; | |
256 | ||
257 | /* | |
258 | * The VIN4 video input path is shared between | |
259 | * CVBS and HDMI inputs through SW[49-53] | |
260 | * switches. | |
261 | * | |
262 | * CVBS is the default selection, link it to | |
263 | * VIN4 here. | |
264 | */ | |
265 | adv7180_out: endpoint { | |
266 | remote-endpoint = <&vin4_in>; | |
267 | }; | |
268 | }; | |
269 | }; | |
1b1b30a2 JM |
270 | |
271 | }; | |
272 | ||
bcf30034 UH |
273 | hdmi-encoder@39 { |
274 | compatible = "adi,adv7511w"; | |
72676ecf RC |
275 | reg = <0x39>, <0x3f>, <0x3c>, <0x38>; |
276 | reg-names = "main", "edid", "cec", "packet"; | |
bcf30034 UH |
277 | interrupt-parent = <&gpio1>; |
278 | interrupts = <28 IRQ_TYPE_LEVEL_LOW>; | |
279 | ||
280 | /* Depends on LVDS */ | |
281 | max-clock = <135000000>; | |
282 | min-vrefresh = <50>; | |
283 | ||
284 | adi,input-depth = <8>; | |
285 | adi,input-colorspace = "rgb"; | |
286 | adi,input-clock = "1x"; | |
bcf30034 UH |
287 | |
288 | ports { | |
289 | #address-cells = <1>; | |
290 | #size-cells = <0>; | |
291 | ||
292 | port@0 { | |
293 | reg = <0>; | |
294 | adv7511_in: endpoint { | |
295 | remote-endpoint = <&thc63lvd1024_out>; | |
296 | }; | |
297 | }; | |
298 | ||
299 | port@1 { | |
300 | reg = <1>; | |
301 | adv7511_out: endpoint { | |
302 | remote-endpoint = <&hdmi_con_out>; | |
303 | }; | |
304 | }; | |
305 | }; | |
306 | }; | |
307 | ||
1b1b30a2 JM |
308 | hdmi-decoder@4c { |
309 | compatible = "adi,adv7612"; | |
310 | reg = <0x4c>; | |
311 | default-input = <0>; | |
312 | ||
313 | ports { | |
314 | #address-cells = <1>; | |
315 | #size-cells = <0>; | |
316 | ||
317 | port@0 { | |
318 | reg = <0>; | |
319 | ||
320 | adv7612_in: endpoint { | |
321 | remote-endpoint = <&hdmi_con_in>; | |
322 | }; | |
323 | }; | |
324 | ||
325 | port@2 { | |
326 | reg = <2>; | |
327 | ||
328 | /* | |
329 | * The VIN4 video input path is shared between | |
330 | * CVBS and HDMI inputs through SW[49-53] | |
331 | * switches. | |
332 | * | |
333 | * CVBS is the default selection, leave HDMI | |
334 | * not connected here. | |
335 | */ | |
336 | adv7612_out: endpoint { | |
337 | pclk-sample = <0>; | |
338 | hsync-active = <0>; | |
339 | vsync-active = <0>; | |
340 | }; | |
341 | }; | |
342 | }; | |
6a0942c2 | 343 | }; |
7acc17b1 GU |
344 | |
345 | eeprom@50 { | |
346 | compatible = "rohm,br24t01", "atmel,24c01"; | |
347 | reg = <0x50>; | |
348 | pagesize = <8>; | |
349 | }; | |
86e7a972 UH |
350 | }; |
351 | ||
41337aa1 UH |
352 | &i2c1 { |
353 | pinctrl-0 = <&i2c1_pins>; | |
354 | pinctrl-names = "default"; | |
355 | status = "okay"; | |
356 | }; | |
357 | ||
bcf30034 UH |
358 | &lvds0 { |
359 | status = "okay"; | |
360 | ||
361 | clocks = <&cpg CPG_MOD 727>, | |
362 | <&x12_clk>, | |
363 | <&extal_clk>; | |
364 | clock-names = "fck", "dclkin.0", "extal"; | |
365 | ||
366 | ports { | |
367 | port@1 { | |
368 | lvds0_out: endpoint { | |
369 | remote-endpoint = <&thc63lvd1024_in>; | |
370 | }; | |
371 | }; | |
372 | }; | |
373 | }; | |
374 | ||
375 | &lvds1 { | |
9a0ff5c7 LP |
376 | /* |
377 | * Even though the LVDS1 output is not connected, the encoder must be | |
378 | * enabled to supply a pixel clock to the DU for the DPAD output when | |
379 | * LVDS0 is in use. | |
380 | */ | |
381 | status = "okay"; | |
382 | ||
bcf30034 UH |
383 | clocks = <&cpg CPG_MOD 727>, |
384 | <&x12_clk>, | |
385 | <&extal_clk>; | |
386 | clock-names = "fck", "dclkin.0", "extal"; | |
387 | }; | |
388 | ||
7acc17b1 | 389 | &ohci0 { |
5c6479d9 | 390 | dr_mode = "host"; |
cfdec2af | 391 | status = "okay"; |
7acc17b1 | 392 | }; |
cfdec2af | 393 | |
7acc17b1 GU |
394 | &pfc { |
395 | avb0_pins: avb { | |
396 | mux { | |
397 | groups = "avb0_link", "avb0_mdio", "avb0_mii"; | |
398 | function = "avb0"; | |
cfdec2af KB |
399 | }; |
400 | }; | |
cfdec2af | 401 | |
4162aa9d MV |
402 | can0_pins: can0 { |
403 | groups = "can0_data_a"; | |
404 | function = "can0"; | |
405 | }; | |
406 | ||
407 | can1_pins: can1 { | |
408 | groups = "can1_data_a"; | |
409 | function = "can1"; | |
410 | }; | |
411 | ||
7acc17b1 GU |
412 | du_pins: du { |
413 | groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; | |
414 | function = "du"; | |
415 | }; | |
416 | ||
417 | i2c0_pins: i2c0 { | |
418 | groups = "i2c0"; | |
419 | function = "i2c0"; | |
420 | }; | |
421 | ||
422 | i2c1_pins: i2c1 { | |
423 | groups = "i2c1"; | |
424 | function = "i2c1"; | |
425 | }; | |
426 | ||
427 | pwm0_pins: pwm0 { | |
428 | groups = "pwm0_c"; | |
429 | function = "pwm0"; | |
430 | }; | |
431 | ||
432 | pwm1_pins: pwm1 { | |
433 | groups = "pwm1_c"; | |
434 | function = "pwm1"; | |
435 | }; | |
436 | ||
437 | scif2_pins: scif2 { | |
438 | groups = "scif2_data"; | |
439 | function = "scif2"; | |
440 | }; | |
441 | ||
442 | sdhi2_pins: sd2 { | |
443 | groups = "mmc_data8", "mmc_ctrl"; | |
444 | function = "mmc"; | |
445 | power-source = <1800>; | |
446 | }; | |
447 | ||
448 | sdhi2_pins_uhs: sd2_uhs { | |
449 | groups = "mmc_data8", "mmc_ctrl"; | |
450 | function = "mmc"; | |
451 | power-source = <1800>; | |
452 | }; | |
453 | ||
454 | usb0_pins: usb0 { | |
455 | groups = "usb0"; | |
456 | function = "usb0"; | |
457 | }; | |
458 | ||
459 | vin4_pins_cvbs: vin4 { | |
460 | groups = "vin4_data8", "vin4_sync", "vin4_clk"; | |
461 | function = "vin4"; | |
462 | }; | |
607c73c3 YS |
463 | }; |
464 | ||
7acc17b1 GU |
465 | &pwm0 { |
466 | pinctrl-0 = <&pwm0_pins>; | |
467 | pinctrl-names = "default"; | |
468 | ||
607c73c3 YS |
469 | status = "okay"; |
470 | }; | |
471 | ||
7acc17b1 GU |
472 | &pwm1 { |
473 | pinctrl-0 = <&pwm1_pins>; | |
4503b50e | 474 | pinctrl-names = "default"; |
7acc17b1 | 475 | |
4503b50e | 476 | status = "okay"; |
7acc17b1 | 477 | }; |
4503b50e | 478 | |
7acc17b1 GU |
479 | &rwdt { |
480 | timeout-sec = <60>; | |
481 | status = "okay"; | |
4503b50e YS |
482 | }; |
483 | ||
c550443f | 484 | &scif2 { |
ea203404 GU |
485 | pinctrl-0 = <&scif2_pins>; |
486 | pinctrl-names = "default"; | |
487 | ||
c550443f GU |
488 | status = "okay"; |
489 | }; | |
490 | ||
9d9505a2 UH |
491 | &sdhi2 { |
492 | /* used for on-board eMMC */ | |
493 | pinctrl-0 = <&sdhi2_pins>; | |
494 | pinctrl-1 = <&sdhi2_pins_uhs>; | |
495 | pinctrl-names = "default", "state_uhs"; | |
496 | ||
497 | vmmc-supply = <®_3p3v>; | |
498 | vqmmc-supply = <®_1p8v>; | |
499 | bus-width = <8>; | |
500 | mmc-hs200-1_8v; | |
501 | non-removable; | |
502 | status = "okay"; | |
503 | }; | |
504 | ||
34f058b2 YS |
505 | &usb2_phy0 { |
506 | pinctrl-0 = <&usb0_pins>; | |
507 | pinctrl-names = "default"; | |
508 | ||
5c6479d9 | 509 | renesas,no-otg-pins; |
34f058b2 YS |
510 | status = "okay"; |
511 | }; | |
512 | ||
6a0942c2 JM |
513 | &vin4 { |
514 | pinctrl-0 = <&vin4_pins_cvbs>; | |
515 | pinctrl-names = "default"; | |
516 | ||
517 | status = "okay"; | |
518 | ||
519 | ports { | |
c7d4df30 | 520 | port { |
6a0942c2 JM |
521 | vin4_in: endpoint { |
522 | remote-endpoint = <&adv7180_out>; | |
523 | }; | |
524 | }; | |
525 | }; | |
526 | }; |