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6913c452 AY |
1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
2 | /* | |
3 | * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd | |
4 | * | |
5 | */ | |
6 | ||
7 | #include <dt-bindings/clock/rk3308-cru.h> | |
8 | #include <dt-bindings/gpio/gpio.h> | |
9 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
10 | #include <dt-bindings/interrupt-controller/irq.h> | |
11 | #include <dt-bindings/pinctrl/rockchip.h> | |
12 | #include <dt-bindings/soc/rockchip,boot-mode.h> | |
13 | #include <dt-bindings/thermal/thermal.h> | |
14 | ||
15 | / { | |
16 | compatible = "rockchip,rk3308"; | |
17 | ||
18 | interrupt-parent = <&gic>; | |
19 | #address-cells = <2>; | |
20 | #size-cells = <2>; | |
21 | ||
22 | aliases { | |
23 | i2c0 = &i2c0; | |
24 | i2c1 = &i2c1; | |
25 | i2c2 = &i2c2; | |
26 | i2c3 = &i2c3; | |
27 | serial0 = &uart0; | |
28 | serial1 = &uart1; | |
29 | serial2 = &uart2; | |
30 | serial3 = &uart3; | |
31 | serial4 = &uart4; | |
32 | spi0 = &spi0; | |
33 | spi1 = &spi1; | |
34 | spi2 = &spi2; | |
35 | }; | |
36 | ||
37 | cpus { | |
38 | #address-cells = <2>; | |
39 | #size-cells = <0>; | |
40 | ||
41 | cpu0: cpu@0 { | |
42 | device_type = "cpu"; | |
98faae2b | 43 | compatible = "arm,cortex-a35"; |
6913c452 AY |
44 | reg = <0x0 0x0>; |
45 | enable-method = "psci"; | |
46 | clocks = <&cru ARMCLK>; | |
47 | #cooling-cells = <2>; | |
48 | dynamic-power-coefficient = <90>; | |
49 | operating-points-v2 = <&cpu0_opp_table>; | |
50 | cpu-idle-states = <&CPU_SLEEP>; | |
51 | next-level-cache = <&l2>; | |
52 | }; | |
53 | ||
54 | cpu1: cpu@1 { | |
55 | device_type = "cpu"; | |
98faae2b | 56 | compatible = "arm,cortex-a35"; |
6913c452 AY |
57 | reg = <0x0 0x1>; |
58 | enable-method = "psci"; | |
59 | operating-points-v2 = <&cpu0_opp_table>; | |
60 | cpu-idle-states = <&CPU_SLEEP>; | |
61 | next-level-cache = <&l2>; | |
62 | }; | |
63 | ||
64 | cpu2: cpu@2 { | |
65 | device_type = "cpu"; | |
98faae2b | 66 | compatible = "arm,cortex-a35"; |
6913c452 AY |
67 | reg = <0x0 0x2>; |
68 | enable-method = "psci"; | |
69 | operating-points-v2 = <&cpu0_opp_table>; | |
70 | cpu-idle-states = <&CPU_SLEEP>; | |
71 | next-level-cache = <&l2>; | |
72 | }; | |
73 | ||
74 | cpu3: cpu@3 { | |
75 | device_type = "cpu"; | |
98faae2b | 76 | compatible = "arm,cortex-a35"; |
6913c452 AY |
77 | reg = <0x0 0x3>; |
78 | enable-method = "psci"; | |
79 | operating-points-v2 = <&cpu0_opp_table>; | |
80 | cpu-idle-states = <&CPU_SLEEP>; | |
81 | next-level-cache = <&l2>; | |
82 | }; | |
83 | ||
84 | idle-states { | |
85 | entry-method = "psci"; | |
86 | ||
87 | CPU_SLEEP: cpu-sleep { | |
88 | compatible = "arm,idle-state"; | |
89 | local-timer-stop; | |
90 | arm,psci-suspend-param = <0x0010000>; | |
91 | entry-latency-us = <120>; | |
92 | exit-latency-us = <250>; | |
93 | min-residency-us = <900>; | |
94 | }; | |
95 | }; | |
96 | ||
97 | l2: l2-cache { | |
98 | compatible = "cache"; | |
99 | }; | |
100 | }; | |
101 | ||
102 | cpu0_opp_table: cpu0-opp-table { | |
103 | compatible = "operating-points-v2"; | |
104 | opp-shared; | |
105 | ||
106 | opp-408000000 { | |
107 | opp-hz = /bits/ 64 <408000000>; | |
108 | opp-microvolt = <950000 950000 1340000>; | |
109 | clock-latency-ns = <40000>; | |
110 | opp-suspend; | |
111 | }; | |
112 | opp-600000000 { | |
113 | opp-hz = /bits/ 64 <600000000>; | |
114 | opp-microvolt = <950000 950000 1340000>; | |
115 | clock-latency-ns = <40000>; | |
116 | }; | |
117 | opp-816000000 { | |
118 | opp-hz = /bits/ 64 <816000000>; | |
119 | opp-microvolt = <1025000 1025000 1340000>; | |
120 | clock-latency-ns = <40000>; | |
121 | }; | |
122 | opp-1008000000 { | |
123 | opp-hz = /bits/ 64 <1008000000>; | |
124 | opp-microvolt = <1125000 1125000 1340000>; | |
125 | clock-latency-ns = <40000>; | |
126 | }; | |
127 | }; | |
128 | ||
129 | arm-pmu { | |
5944eb7a | 130 | compatible = "arm,cortex-a35-pmu"; |
6913c452 AY |
131 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, |
132 | <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, | |
133 | <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, | |
134 | <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
135 | interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; | |
136 | }; | |
137 | ||
138 | mac_clkin: external-mac-clock { | |
139 | compatible = "fixed-clock"; | |
140 | clock-frequency = <50000000>; | |
141 | clock-output-names = "mac_clkin"; | |
142 | #clock-cells = <0>; | |
143 | }; | |
144 | ||
145 | psci { | |
146 | compatible = "arm,psci-1.0"; | |
147 | method = "smc"; | |
148 | }; | |
149 | ||
150 | timer { | |
151 | compatible = "arm,armv8-timer"; | |
152 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
153 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
154 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
155 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
156 | }; | |
157 | ||
158 | xin24m: xin24m { | |
159 | compatible = "fixed-clock"; | |
160 | #clock-cells = <0>; | |
161 | clock-frequency = <24000000>; | |
162 | clock-output-names = "xin24m"; | |
163 | }; | |
164 | ||
165 | grf: grf@ff000000 { | |
166 | compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; | |
167 | reg = <0x0 0xff000000 0x0 0x10000>; | |
168 | ||
169 | reboot-mode { | |
170 | compatible = "syscon-reboot-mode"; | |
171 | offset = <0x500>; | |
172 | mode-bootloader = <BOOT_BL_DOWNLOAD>; | |
173 | mode-loader = <BOOT_BL_DOWNLOAD>; | |
174 | mode-normal = <BOOT_NORMAL>; | |
175 | mode-recovery = <BOOT_RECOVERY>; | |
176 | mode-fastboot = <BOOT_FASTBOOT>; | |
177 | }; | |
178 | }; | |
179 | ||
180 | detect_grf: syscon@ff00b000 { | |
181 | compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; | |
182 | reg = <0x0 0xff00b000 0x0 0x1000>; | |
183 | #address-cells = <1>; | |
184 | #size-cells = <1>; | |
185 | }; | |
186 | ||
187 | core_grf: syscon@ff00c000 { | |
188 | compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd"; | |
189 | reg = <0x0 0xff00c000 0x0 0x1000>; | |
190 | #address-cells = <1>; | |
191 | #size-cells = <1>; | |
192 | }; | |
193 | ||
194 | i2c0: i2c@ff040000 { | |
195 | compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; | |
196 | reg = <0x0 0xff040000 0x0 0x1000>; | |
197 | clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; | |
198 | clock-names = "i2c", "pclk"; | |
199 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
200 | pinctrl-names = "default"; | |
201 | pinctrl-0 = <&i2c0_xfer>; | |
202 | #address-cells = <1>; | |
203 | #size-cells = <0>; | |
204 | status = "disabled"; | |
205 | }; | |
206 | ||
207 | i2c1: i2c@ff050000 { | |
208 | compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; | |
209 | reg = <0x0 0xff050000 0x0 0x1000>; | |
210 | clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; | |
211 | clock-names = "i2c", "pclk"; | |
212 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
213 | pinctrl-names = "default"; | |
214 | pinctrl-0 = <&i2c1_xfer>; | |
215 | #address-cells = <1>; | |
216 | #size-cells = <0>; | |
217 | status = "disabled"; | |
218 | }; | |
219 | ||
220 | i2c2: i2c@ff060000 { | |
221 | compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; | |
222 | reg = <0x0 0xff060000 0x0 0x1000>; | |
223 | clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; | |
224 | clock-names = "i2c", "pclk"; | |
225 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
226 | pinctrl-names = "default"; | |
227 | pinctrl-0 = <&i2c2_xfer>; | |
228 | #address-cells = <1>; | |
229 | #size-cells = <0>; | |
230 | status = "disabled"; | |
231 | }; | |
232 | ||
233 | i2c3: i2c@ff070000 { | |
234 | compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; | |
235 | reg = <0x0 0xff070000 0x0 0x1000>; | |
236 | clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; | |
237 | clock-names = "i2c", "pclk"; | |
238 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
239 | pinctrl-names = "default"; | |
240 | pinctrl-0 = <&i2c3m0_xfer>; | |
241 | #address-cells = <1>; | |
242 | #size-cells = <0>; | |
243 | status = "disabled"; | |
244 | }; | |
245 | ||
246 | wdt: watchdog@ff080000 { | |
247 | compatible = "snps,dw-wdt"; | |
248 | reg = <0x0 0xff080000 0x0 0x100>; | |
249 | clocks = <&cru PCLK_WDT>; | |
250 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
251 | status = "disabled"; | |
252 | }; | |
253 | ||
254 | uart0: serial@ff0a0000 { | |
255 | compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; | |
256 | reg = <0x0 0xff0a0000 0x0 0x100>; | |
257 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; | |
258 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
259 | clock-names = "baudclk", "apb_pclk"; | |
260 | reg-shift = <2>; | |
261 | reg-io-width = <4>; | |
262 | pinctrl-names = "default"; | |
263 | pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; | |
264 | status = "disabled"; | |
265 | }; | |
266 | ||
267 | uart1: serial@ff0b0000 { | |
268 | compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; | |
269 | reg = <0x0 0xff0b0000 0x0 0x100>; | |
270 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
271 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
272 | clock-names = "baudclk", "apb_pclk"; | |
273 | reg-shift = <2>; | |
274 | reg-io-width = <4>; | |
275 | pinctrl-names = "default"; | |
276 | pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; | |
277 | status = "disabled"; | |
278 | }; | |
279 | ||
280 | uart2: serial@ff0c0000 { | |
281 | compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; | |
282 | reg = <0x0 0xff0c0000 0x0 0x100>; | |
283 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
284 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
285 | clock-names = "baudclk", "apb_pclk"; | |
286 | reg-shift = <2>; | |
287 | reg-io-width = <4>; | |
288 | pinctrl-names = "default"; | |
289 | pinctrl-0 = <&uart2m0_xfer>; | |
290 | status = "disabled"; | |
291 | }; | |
292 | ||
293 | uart3: serial@ff0d0000 { | |
294 | compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; | |
295 | reg = <0x0 0xff0d0000 0x0 0x100>; | |
296 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
297 | clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; | |
298 | clock-names = "baudclk", "apb_pclk"; | |
299 | reg-shift = <2>; | |
300 | reg-io-width = <4>; | |
301 | pinctrl-names = "default"; | |
302 | pinctrl-0 = <&uart3_xfer>; | |
303 | status = "disabled"; | |
304 | }; | |
305 | ||
306 | uart4: serial@ff0e0000 { | |
307 | compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; | |
308 | reg = <0x0 0xff0e0000 0x0 0x100>; | |
309 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
310 | clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; | |
311 | clock-names = "baudclk", "apb_pclk"; | |
312 | reg-shift = <2>; | |
313 | reg-io-width = <4>; | |
314 | pinctrl-names = "default"; | |
315 | pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; | |
316 | status = "disabled"; | |
317 | }; | |
318 | ||
319 | spi0: spi@ff120000 { | |
320 | compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; | |
321 | reg = <0x0 0xff120000 0x0 0x1000>; | |
322 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
323 | #address-cells = <1>; | |
324 | #size-cells = <0>; | |
325 | clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; | |
326 | clock-names = "spiclk", "apb_pclk"; | |
327 | dmas = <&dmac0 0>, <&dmac0 1>; | |
328 | dma-names = "tx", "rx"; | |
329 | pinctrl-names = "default"; | |
330 | pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; | |
331 | status = "disabled"; | |
332 | }; | |
333 | ||
334 | spi1: spi@ff130000 { | |
335 | compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; | |
336 | reg = <0x0 0xff130000 0x0 0x1000>; | |
337 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
338 | #address-cells = <1>; | |
339 | #size-cells = <0>; | |
340 | clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; | |
341 | clock-names = "spiclk", "apb_pclk"; | |
342 | dmas = <&dmac0 2>, <&dmac0 3>; | |
343 | dma-names = "tx", "rx"; | |
344 | pinctrl-names = "default"; | |
345 | pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; | |
346 | status = "disabled"; | |
347 | }; | |
348 | ||
349 | spi2: spi@ff140000 { | |
350 | compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; | |
351 | reg = <0x0 0xff140000 0x0 0x1000>; | |
352 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
353 | #address-cells = <1>; | |
354 | #size-cells = <0>; | |
355 | clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; | |
356 | clock-names = "spiclk", "apb_pclk"; | |
357 | dmas = <&dmac1 16>, <&dmac1 17>; | |
358 | dma-names = "tx", "rx"; | |
359 | pinctrl-names = "default"; | |
360 | pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; | |
361 | status = "disabled"; | |
362 | }; | |
363 | ||
364 | pwm8: pwm@ff160000 { | |
365 | compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; | |
366 | reg = <0x0 0xff160000 0x0 0x10>; | |
367 | clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; | |
368 | clock-names = "pwm", "pclk"; | |
369 | pinctrl-names = "default"; | |
370 | pinctrl-0 = <&pwm8_pin>; | |
371 | #pwm-cells = <3>; | |
372 | status = "disabled"; | |
373 | }; | |
374 | ||
375 | pwm9: pwm@ff160010 { | |
376 | compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; | |
377 | reg = <0x0 0xff160010 0x0 0x10>; | |
378 | clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; | |
379 | clock-names = "pwm", "pclk"; | |
380 | pinctrl-names = "default"; | |
381 | pinctrl-0 = <&pwm9_pin>; | |
382 | #pwm-cells = <3>; | |
383 | status = "disabled"; | |
384 | }; | |
385 | ||
386 | pwm10: pwm@ff160020 { | |
387 | compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; | |
388 | reg = <0x0 0xff160020 0x0 0x10>; | |
389 | clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; | |
390 | clock-names = "pwm", "pclk"; | |
391 | pinctrl-names = "default"; | |
392 | pinctrl-0 = <&pwm10_pin>; | |
393 | #pwm-cells = <3>; | |
394 | status = "disabled"; | |
395 | }; | |
396 | ||
397 | pwm11: pwm@ff160030 { | |
398 | compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; | |
399 | reg = <0x0 0xff160030 0x0 0x10>; | |
400 | clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; | |
401 | clock-names = "pwm", "pclk"; | |
402 | pinctrl-names = "default"; | |
403 | pinctrl-0 = <&pwm11_pin>; | |
404 | #pwm-cells = <3>; | |
405 | status = "disabled"; | |
406 | }; | |
407 | ||
408 | pwm4: pwm@ff170000 { | |
409 | compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; | |
410 | reg = <0x0 0xff170000 0x0 0x10>; | |
411 | clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; | |
412 | clock-names = "pwm", "pclk"; | |
413 | pinctrl-names = "default"; | |
414 | pinctrl-0 = <&pwm4_pin>; | |
415 | #pwm-cells = <3>; | |
416 | status = "disabled"; | |
417 | }; | |
418 | ||
419 | pwm5: pwm@ff170010 { | |
420 | compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; | |
421 | reg = <0x0 0xff170010 0x0 0x10>; | |
422 | clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; | |
423 | clock-names = "pwm", "pclk"; | |
424 | pinctrl-names = "default"; | |
425 | pinctrl-0 = <&pwm5_pin>; | |
426 | #pwm-cells = <3>; | |
427 | status = "disabled"; | |
428 | }; | |
429 | ||
430 | pwm6: pwm@ff170020 { | |
431 | compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; | |
432 | reg = <0x0 0xff170020 0x0 0x10>; | |
433 | clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; | |
434 | clock-names = "pwm", "pclk"; | |
435 | pinctrl-names = "default"; | |
436 | pinctrl-0 = <&pwm6_pin>; | |
437 | #pwm-cells = <3>; | |
438 | status = "disabled"; | |
439 | }; | |
440 | ||
441 | pwm7: pwm@ff170030 { | |
442 | compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; | |
443 | reg = <0x0 0xff170030 0x0 0x10>; | |
444 | clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; | |
445 | clock-names = "pwm", "pclk"; | |
446 | pinctrl-names = "default"; | |
447 | pinctrl-0 = <&pwm7_pin>; | |
448 | #pwm-cells = <3>; | |
449 | status = "disabled"; | |
450 | }; | |
451 | ||
452 | pwm0: pwm@ff180000 { | |
453 | compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; | |
454 | reg = <0x0 0xff180000 0x0 0x10>; | |
455 | clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; | |
456 | clock-names = "pwm", "pclk"; | |
457 | pinctrl-names = "default"; | |
458 | pinctrl-0 = <&pwm0_pin>; | |
459 | #pwm-cells = <3>; | |
460 | status = "disabled"; | |
461 | }; | |
462 | ||
463 | pwm1: pwm@ff180010 { | |
464 | compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; | |
465 | reg = <0x0 0xff180010 0x0 0x10>; | |
466 | clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; | |
467 | clock-names = "pwm", "pclk"; | |
468 | pinctrl-names = "default"; | |
469 | pinctrl-0 = <&pwm1_pin>; | |
470 | #pwm-cells = <3>; | |
471 | status = "disabled"; | |
472 | }; | |
473 | ||
474 | pwm2: pwm@ff180020 { | |
475 | compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; | |
476 | reg = <0x0 0xff180020 0x0 0x10>; | |
477 | clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; | |
478 | clock-names = "pwm", "pclk"; | |
479 | pinctrl-names = "default"; | |
480 | pinctrl-0 = <&pwm2_pin>; | |
481 | #pwm-cells = <3>; | |
482 | status = "disabled"; | |
483 | }; | |
484 | ||
485 | pwm3: pwm@ff180030 { | |
486 | compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; | |
487 | reg = <0x0 0xff180030 0x0 0x10>; | |
488 | clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; | |
489 | clock-names = "pwm", "pclk"; | |
490 | pinctrl-names = "default"; | |
491 | pinctrl-0 = <&pwm3_pin>; | |
492 | #pwm-cells = <3>; | |
493 | status = "disabled"; | |
494 | }; | |
495 | ||
496 | rktimer: rktimer@ff1a0000 { | |
497 | compatible = "rockchip,rk3288-timer"; | |
498 | reg = <0x0 0xff1a0000 0x0 0x20>; | |
499 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
500 | clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; | |
501 | clock-names = "pclk", "timer"; | |
502 | }; | |
503 | ||
504 | saradc: saradc@ff1e0000 { | |
505 | compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; | |
506 | reg = <0x0 0xff1e0000 0x0 0x100>; | |
507 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
508 | clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; | |
509 | clock-names = "saradc", "apb_pclk"; | |
510 | #io-channel-cells = <1>; | |
511 | resets = <&cru SRST_SARADC_P>; | |
512 | reset-names = "saradc-apb"; | |
513 | status = "disabled"; | |
514 | }; | |
515 | ||
b2411bef | 516 | amba: bus { |
6913c452 AY |
517 | compatible = "simple-bus"; |
518 | #address-cells = <2>; | |
519 | #size-cells = <2>; | |
520 | ranges; | |
521 | ||
522 | dmac0: dma-controller@ff2c0000 { | |
523 | compatible = "arm,pl330", "arm,primecell"; | |
524 | reg = <0x0 0xff2c0000 0x0 0x4000>; | |
525 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
526 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
527 | clocks = <&cru ACLK_DMAC0>; | |
528 | clock-names = "apb_pclk"; | |
529 | #dma-cells = <1>; | |
530 | }; | |
531 | ||
532 | dmac1: dma-controller@ff2d0000 { | |
533 | compatible = "arm,pl330", "arm,primecell"; | |
534 | reg = <0x0 0xff2d0000 0x0 0x4000>; | |
535 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | |
536 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
537 | clocks = <&cru ACLK_DMAC1>; | |
538 | clock-names = "apb_pclk"; | |
539 | #dma-cells = <1>; | |
540 | }; | |
541 | }; | |
542 | ||
543 | i2s_2ch_0: i2s@ff350000 { | |
544 | compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; | |
545 | reg = <0x0 0xff350000 0x0 0x1000>; | |
546 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
547 | clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>; | |
548 | clock-names = "i2s_clk", "i2s_hclk"; | |
549 | dmas = <&dmac1 8>, <&dmac1 9>; | |
550 | dma-names = "tx", "rx"; | |
551 | resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>; | |
552 | reset-names = "reset-m", "reset-h"; | |
553 | pinctrl-names = "default"; | |
554 | pinctrl-0 = <&i2s_2ch_0_sclk | |
555 | &i2s_2ch_0_lrck | |
556 | &i2s_2ch_0_sdi | |
557 | &i2s_2ch_0_sdo>; | |
558 | status = "disabled"; | |
559 | }; | |
560 | ||
561 | i2s_2ch_1: i2s@ff360000 { | |
562 | compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; | |
563 | reg = <0x0 0xff360000 0x0 0x1000>; | |
564 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; | |
565 | clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; | |
566 | clock-names = "i2s_clk", "i2s_hclk"; | |
567 | dmas = <&dmac1 11>; | |
568 | dma-names = "rx"; | |
569 | resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>; | |
570 | reset-names = "reset-m", "reset-h"; | |
571 | status = "disabled"; | |
572 | }; | |
573 | ||
574 | spdif_tx: spdif-tx@ff3a0000 { | |
575 | compatible = "rockchip,rk3308-spdif", "rockchip,rk3328-spdif"; | |
576 | reg = <0x0 0xff3a0000 0x0 0x1000>; | |
577 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
578 | clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; | |
579 | clock-names = "mclk", "hclk"; | |
580 | dmas = <&dmac1 13>; | |
581 | dma-names = "tx"; | |
582 | pinctrl-names = "default"; | |
583 | pinctrl-0 = <&spdif_out>; | |
584 | status = "disabled"; | |
585 | }; | |
586 | ||
3ef7c255 | 587 | sdmmc: mmc@ff480000 { |
6913c452 AY |
588 | compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; |
589 | reg = <0x0 0xff480000 0x0 0x4000>; | |
590 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | |
591 | bus-width = <4>; | |
592 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, | |
593 | <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; | |
2be6a280 | 594 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; |
6913c452 AY |
595 | fifo-depth = <0x100>; |
596 | max-frequency = <150000000>; | |
597 | pinctrl-names = "default"; | |
598 | pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; | |
599 | status = "disabled"; | |
600 | }; | |
601 | ||
3ef7c255 | 602 | emmc: mmc@ff490000 { |
6913c452 AY |
603 | compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; |
604 | reg = <0x0 0xff490000 0x0 0x4000>; | |
605 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
606 | bus-width = <8>; | |
607 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, | |
608 | <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; | |
2be6a280 | 609 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; |
6913c452 AY |
610 | fifo-depth = <0x100>; |
611 | max-frequency = <150000000>; | |
612 | status = "disabled"; | |
613 | }; | |
614 | ||
3ef7c255 | 615 | sdio: mmc@ff4a0000 { |
6913c452 AY |
616 | compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; |
617 | reg = <0x0 0xff4a0000 0x0 0x4000>; | |
618 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | |
619 | bus-width = <4>; | |
620 | clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, | |
621 | <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; | |
2be6a280 | 622 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; |
6913c452 AY |
623 | fifo-depth = <0x100>; |
624 | max-frequency = <150000000>; | |
625 | pinctrl-names = "default"; | |
626 | pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; | |
627 | status = "disabled"; | |
628 | }; | |
629 | ||
630 | cru: clock-controller@ff500000 { | |
631 | compatible = "rockchip,rk3308-cru"; | |
632 | reg = <0x0 0xff500000 0x0 0x1000>; | |
633 | #clock-cells = <1>; | |
634 | #reset-cells = <1>; | |
635 | rockchip,grf = <&grf>; | |
636 | ||
637 | assigned-clocks = <&cru SCLK_RTC32K>; | |
638 | assigned-clock-rates = <32768>; | |
639 | }; | |
640 | ||
641 | gic: interrupt-controller@ff580000 { | |
642 | compatible = "arm,gic-400"; | |
643 | reg = <0x0 0xff581000 0x0 0x1000>, | |
644 | <0x0 0xff582000 0x0 0x2000>, | |
645 | <0x0 0xff584000 0x0 0x2000>, | |
646 | <0x0 0xff586000 0x0 0x2000>; | |
647 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
648 | #interrupt-cells = <3>; | |
649 | interrupt-controller; | |
650 | #address-cells = <0>; | |
651 | }; | |
652 | ||
653 | sram: sram@fff80000 { | |
654 | compatible = "mmio-sram"; | |
655 | reg = <0x0 0xfff80000 0x0 0x40000>; | |
656 | ranges = <0 0x0 0xfff80000 0x40000>; | |
657 | #address-cells = <1>; | |
658 | #size-cells = <1>; | |
659 | ||
660 | /* reserved for ddr dvfs and system suspend/resume */ | |
661 | ddr-sram@0 { | |
662 | reg = <0x0 0x8000>; | |
663 | }; | |
664 | ||
665 | /* reserved for vad audio buffer */ | |
666 | vad_sram: vad-sram@8000 { | |
667 | reg = <0x8000 0x38000>; | |
668 | }; | |
669 | }; | |
670 | ||
671 | pinctrl: pinctrl { | |
672 | compatible = "rockchip,rk3308-pinctrl"; | |
673 | rockchip,grf = <&grf>; | |
674 | #address-cells = <2>; | |
675 | #size-cells = <2>; | |
676 | ranges; | |
677 | ||
678 | gpio0: gpio0@ff220000 { | |
679 | compatible = "rockchip,gpio-bank"; | |
680 | reg = <0x0 0xff220000 0x0 0x100>; | |
681 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
682 | clocks = <&cru PCLK_GPIO0>; | |
683 | gpio-controller; | |
684 | #gpio-cells = <2>; | |
685 | interrupt-controller; | |
686 | #interrupt-cells = <2>; | |
687 | }; | |
688 | ||
689 | gpio1: gpio1@ff230000 { | |
690 | compatible = "rockchip,gpio-bank"; | |
691 | reg = <0x0 0xff230000 0x0 0x100>; | |
692 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
693 | clocks = <&cru PCLK_GPIO1>; | |
694 | gpio-controller; | |
695 | #gpio-cells = <2>; | |
696 | interrupt-controller; | |
697 | #interrupt-cells = <2>; | |
698 | }; | |
699 | ||
700 | gpio2: gpio2@ff240000 { | |
701 | compatible = "rockchip,gpio-bank"; | |
702 | reg = <0x0 0xff240000 0x0 0x100>; | |
703 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
704 | clocks = <&cru PCLK_GPIO2>; | |
705 | gpio-controller; | |
706 | #gpio-cells = <2>; | |
707 | interrupt-controller; | |
708 | #interrupt-cells = <2>; | |
709 | }; | |
710 | ||
711 | gpio3: gpio3@ff250000 { | |
712 | compatible = "rockchip,gpio-bank"; | |
713 | reg = <0x0 0xff250000 0x0 0x100>; | |
714 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
715 | clocks = <&cru PCLK_GPIO3>; | |
716 | gpio-controller; | |
717 | #gpio-cells = <2>; | |
718 | interrupt-controller; | |
719 | #interrupt-cells = <2>; | |
720 | }; | |
721 | ||
722 | gpio4: gpio4@ff260000 { | |
723 | compatible = "rockchip,gpio-bank"; | |
724 | reg = <0x0 0xff260000 0x0 0x100>; | |
725 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; | |
726 | clocks = <&cru PCLK_GPIO4>; | |
727 | gpio-controller; | |
728 | #gpio-cells = <2>; | |
729 | interrupt-controller; | |
730 | #interrupt-cells = <2>; | |
731 | }; | |
732 | ||
733 | pcfg_pull_up: pcfg-pull-up { | |
734 | bias-pull-up; | |
735 | }; | |
736 | ||
737 | pcfg_pull_down: pcfg-pull-down { | |
738 | bias-pull-down; | |
739 | }; | |
740 | ||
741 | pcfg_pull_none: pcfg-pull-none { | |
742 | bias-disable; | |
743 | }; | |
744 | ||
745 | pcfg_pull_none_2ma: pcfg-pull-none-2ma { | |
746 | bias-disable; | |
747 | drive-strength = <2>; | |
748 | }; | |
749 | ||
750 | pcfg_pull_up_2ma: pcfg-pull-up-2ma { | |
751 | bias-pull-up; | |
752 | drive-strength = <2>; | |
753 | }; | |
754 | ||
755 | pcfg_pull_up_4ma: pcfg-pull-up-4ma { | |
756 | bias-pull-up; | |
757 | drive-strength = <4>; | |
758 | }; | |
759 | ||
760 | pcfg_pull_none_4ma: pcfg-pull-none-4ma { | |
761 | bias-disable; | |
762 | drive-strength = <4>; | |
763 | }; | |
764 | ||
765 | pcfg_pull_down_4ma: pcfg-pull-down-4ma { | |
766 | bias-pull-down; | |
767 | drive-strength = <4>; | |
768 | }; | |
769 | ||
770 | pcfg_pull_none_8ma: pcfg-pull-none-8ma { | |
771 | bias-disable; | |
772 | drive-strength = <8>; | |
773 | }; | |
774 | ||
775 | pcfg_pull_up_8ma: pcfg-pull-up-8ma { | |
776 | bias-pull-up; | |
777 | drive-strength = <8>; | |
778 | }; | |
779 | ||
780 | pcfg_pull_none_12ma: pcfg-pull-none-12ma { | |
781 | bias-disable; | |
782 | drive-strength = <12>; | |
783 | }; | |
784 | ||
785 | pcfg_pull_up_12ma: pcfg-pull-up-12ma { | |
786 | bias-pull-up; | |
787 | drive-strength = <12>; | |
788 | }; | |
789 | ||
790 | pcfg_pull_none_smt: pcfg-pull-none-smt { | |
791 | bias-disable; | |
792 | input-schmitt-enable; | |
793 | }; | |
794 | ||
795 | pcfg_output_high: pcfg-output-high { | |
796 | output-high; | |
797 | }; | |
798 | ||
799 | pcfg_output_low: pcfg-output-low { | |
800 | output-low; | |
801 | }; | |
802 | ||
803 | pcfg_input_high: pcfg-input-high { | |
804 | bias-pull-up; | |
805 | input-enable; | |
806 | }; | |
807 | ||
808 | pcfg_input: pcfg-input { | |
809 | input-enable; | |
810 | }; | |
811 | ||
812 | emmc { | |
813 | emmc_clk: emmc-clk { | |
814 | rockchip,pins = | |
815 | <3 RK_PB1 2 &pcfg_pull_none_8ma>; | |
816 | }; | |
817 | ||
818 | emmc_cmd: emmc-cmd { | |
819 | rockchip,pins = | |
820 | <3 RK_PB0 2 &pcfg_pull_up_8ma>; | |
821 | }; | |
822 | ||
823 | emmc_pwren: emmc-pwren { | |
824 | rockchip,pins = | |
825 | <3 RK_PB3 2 &pcfg_pull_none>; | |
826 | }; | |
827 | ||
828 | emmc_rstn: emmc-rstn { | |
829 | rockchip,pins = | |
830 | <3 RK_PB2 2 &pcfg_pull_none>; | |
831 | }; | |
832 | ||
833 | emmc_bus1: emmc-bus1 { | |
834 | rockchip,pins = | |
835 | <3 RK_PA0 2 &pcfg_pull_up_8ma>; | |
836 | }; | |
837 | ||
838 | emmc_bus4: emmc-bus4 { | |
839 | rockchip,pins = | |
840 | <3 RK_PA0 2 &pcfg_pull_up_8ma>, | |
841 | <3 RK_PA1 2 &pcfg_pull_up_8ma>, | |
842 | <3 RK_PA2 2 &pcfg_pull_up_8ma>, | |
843 | <3 RK_PA3 2 &pcfg_pull_up_8ma>; | |
844 | }; | |
845 | ||
846 | emmc_bus8: emmc-bus8 { | |
847 | rockchip,pins = | |
848 | <3 RK_PA0 2 &pcfg_pull_up_8ma>, | |
849 | <3 RK_PA1 2 &pcfg_pull_up_8ma>, | |
850 | <3 RK_PA2 2 &pcfg_pull_up_8ma>, | |
851 | <3 RK_PA3 2 &pcfg_pull_up_8ma>, | |
852 | <3 RK_PA4 2 &pcfg_pull_up_8ma>, | |
853 | <3 RK_PA5 2 &pcfg_pull_up_8ma>, | |
854 | <3 RK_PA6 2 &pcfg_pull_up_8ma>, | |
855 | <3 RK_PA7 2 &pcfg_pull_up_8ma>; | |
856 | }; | |
857 | }; | |
858 | ||
859 | flash { | |
860 | flash_csn0: flash-csn0 { | |
861 | rockchip,pins = | |
862 | <3 RK_PB5 1 &pcfg_pull_none>; | |
863 | }; | |
864 | ||
865 | flash_rdy: flash-rdy { | |
866 | rockchip,pins = | |
867 | <3 RK_PB4 1 &pcfg_pull_none>; | |
868 | }; | |
869 | ||
870 | flash_ale: flash-ale { | |
871 | rockchip,pins = | |
872 | <3 RK_PB3 1 &pcfg_pull_none>; | |
873 | }; | |
874 | ||
875 | flash_cle: flash-cle { | |
876 | rockchip,pins = | |
877 | <3 RK_PB1 1 &pcfg_pull_none>; | |
878 | }; | |
879 | ||
880 | flash_wrn: flash-wrn { | |
881 | rockchip,pins = | |
882 | <3 RK_PB0 1 &pcfg_pull_none>; | |
883 | }; | |
884 | ||
885 | flash_rdn: flash-rdn { | |
886 | rockchip,pins = | |
887 | <3 RK_PB2 1 &pcfg_pull_none>; | |
888 | }; | |
889 | ||
890 | flash_bus8: flash-bus8 { | |
891 | rockchip,pins = | |
892 | <3 RK_PA0 1 &pcfg_pull_up_12ma>, | |
893 | <3 RK_PA1 1 &pcfg_pull_up_12ma>, | |
894 | <3 RK_PA2 1 &pcfg_pull_up_12ma>, | |
895 | <3 RK_PA3 1 &pcfg_pull_up_12ma>, | |
896 | <3 RK_PA4 1 &pcfg_pull_up_12ma>, | |
897 | <3 RK_PA5 1 &pcfg_pull_up_12ma>, | |
898 | <3 RK_PA6 1 &pcfg_pull_up_12ma>, | |
899 | <3 RK_PA7 1 &pcfg_pull_up_12ma>; | |
900 | }; | |
901 | }; | |
902 | ||
903 | gmac { | |
904 | rmii_pins: rmii-pins { | |
905 | rockchip,pins = | |
906 | /* mac_txen */ | |
907 | <1 RK_PC1 3 &pcfg_pull_none_12ma>, | |
908 | /* mac_txd1 */ | |
909 | <1 RK_PC3 3 &pcfg_pull_none_12ma>, | |
910 | /* mac_txd0 */ | |
911 | <1 RK_PC2 3 &pcfg_pull_none_12ma>, | |
912 | /* mac_rxd0 */ | |
913 | <1 RK_PC4 3 &pcfg_pull_none>, | |
914 | /* mac_rxd1 */ | |
915 | <1 RK_PC5 3 &pcfg_pull_none>, | |
916 | /* mac_rxer */ | |
917 | <1 RK_PB7 3 &pcfg_pull_none>, | |
918 | /* mac_rxdv */ | |
919 | <1 RK_PC0 3 &pcfg_pull_none>, | |
920 | /* mac_mdio */ | |
921 | <1 RK_PB6 3 &pcfg_pull_none>, | |
922 | /* mac_mdc */ | |
923 | <1 RK_PB5 3 &pcfg_pull_none>; | |
924 | }; | |
925 | ||
926 | mac_refclk_12ma: mac-refclk-12ma { | |
927 | rockchip,pins = | |
928 | <1 RK_PB4 3 &pcfg_pull_none_12ma>; | |
929 | }; | |
930 | ||
931 | mac_refclk: mac-refclk { | |
932 | rockchip,pins = | |
933 | <1 RK_PB4 3 &pcfg_pull_none>; | |
934 | }; | |
935 | }; | |
936 | ||
937 | gmac-m1 { | |
938 | rmiim1_pins: rmiim1-pins { | |
939 | rockchip,pins = | |
940 | /* mac_txen */ | |
941 | <4 RK_PB7 2 &pcfg_pull_none_12ma>, | |
942 | /* mac_txd1 */ | |
943 | <4 RK_PA5 2 &pcfg_pull_none_12ma>, | |
944 | /* mac_txd0 */ | |
945 | <4 RK_PA4 2 &pcfg_pull_none_12ma>, | |
946 | /* mac_rxd0 */ | |
947 | <4 RK_PA2 2 &pcfg_pull_none>, | |
948 | /* mac_rxd1 */ | |
949 | <4 RK_PA3 2 &pcfg_pull_none>, | |
950 | /* mac_rxer */ | |
951 | <4 RK_PA0 2 &pcfg_pull_none>, | |
952 | /* mac_rxdv */ | |
953 | <4 RK_PA1 2 &pcfg_pull_none>, | |
954 | /* mac_mdio */ | |
955 | <4 RK_PB6 2 &pcfg_pull_none>, | |
956 | /* mac_mdc */ | |
957 | <4 RK_PB5 2 &pcfg_pull_none>; | |
958 | }; | |
959 | ||
960 | macm1_refclk_12ma: macm1-refclk-12ma { | |
961 | rockchip,pins = | |
962 | <4 RK_PB4 2 &pcfg_pull_none_12ma>; | |
963 | }; | |
964 | ||
965 | macm1_refclk: macm1-refclk { | |
966 | rockchip,pins = | |
967 | <4 RK_PB4 2 &pcfg_pull_none>; | |
968 | }; | |
969 | }; | |
970 | ||
971 | i2c0 { | |
972 | i2c0_xfer: i2c0-xfer { | |
973 | rockchip,pins = | |
974 | <1 RK_PD0 2 &pcfg_pull_none_smt>, | |
975 | <1 RK_PD1 2 &pcfg_pull_none_smt>; | |
976 | }; | |
977 | }; | |
978 | ||
979 | i2c1 { | |
980 | i2c1_xfer: i2c1-xfer { | |
981 | rockchip,pins = | |
982 | <0 RK_PB3 1 &pcfg_pull_none_smt>, | |
983 | <0 RK_PB4 1 &pcfg_pull_none_smt>; | |
984 | }; | |
985 | }; | |
986 | ||
987 | i2c2 { | |
988 | i2c2_xfer: i2c2-xfer { | |
989 | rockchip,pins = | |
990 | <2 RK_PA2 3 &pcfg_pull_none_smt>, | |
991 | <2 RK_PA3 3 &pcfg_pull_none_smt>; | |
992 | }; | |
993 | }; | |
994 | ||
995 | i2c3-m0 { | |
996 | i2c3m0_xfer: i2c3m0-xfer { | |
997 | rockchip,pins = | |
998 | <0 RK_PB7 2 &pcfg_pull_none_smt>, | |
999 | <0 RK_PC0 2 &pcfg_pull_none_smt>; | |
1000 | }; | |
1001 | }; | |
1002 | ||
1003 | i2c3-m1 { | |
1004 | i2c3m1_xfer: i2c3m1-xfer { | |
1005 | rockchip,pins = | |
1006 | <3 RK_PB4 2 &pcfg_pull_none_smt>, | |
1007 | <3 RK_PB5 2 &pcfg_pull_none_smt>; | |
1008 | }; | |
1009 | }; | |
1010 | ||
1011 | i2c3-m2 { | |
1012 | i2c3m2_xfer: i2c3m2-xfer { | |
1013 | rockchip,pins = | |
1014 | <2 RK_PA1 3 &pcfg_pull_none_smt>, | |
1015 | <2 RK_PA0 3 &pcfg_pull_none_smt>; | |
1016 | }; | |
1017 | }; | |
1018 | ||
1019 | i2s_2ch_0 { | |
1020 | i2s_2ch_0_mclk: i2s-2ch-0-mclk { | |
1021 | rockchip,pins = | |
1022 | <4 RK_PB4 1 &pcfg_pull_none>; | |
1023 | }; | |
1024 | ||
1025 | i2s_2ch_0_sclk: i2s-2ch-0-sclk { | |
1026 | rockchip,pins = | |
1027 | <4 RK_PB5 1 &pcfg_pull_none>; | |
1028 | }; | |
1029 | ||
1030 | i2s_2ch_0_lrck: i2s-2ch-0-lrck { | |
1031 | rockchip,pins = | |
1032 | <4 RK_PB6 1 &pcfg_pull_none>; | |
1033 | }; | |
1034 | ||
1035 | i2s_2ch_0_sdo: i2s-2ch-0-sdo { | |
1036 | rockchip,pins = | |
1037 | <4 RK_PB7 1 &pcfg_pull_none>; | |
1038 | }; | |
1039 | ||
1040 | i2s_2ch_0_sdi: i2s-2ch-0-sdi { | |
1041 | rockchip,pins = | |
1042 | <4 RK_PC0 1 &pcfg_pull_none>; | |
1043 | }; | |
1044 | }; | |
1045 | ||
1046 | i2s_8ch_0 { | |
1047 | i2s_8ch_0_mclk: i2s-8ch-0-mclk { | |
1048 | rockchip,pins = | |
1049 | <2 RK_PA4 1 &pcfg_pull_none>; | |
1050 | }; | |
1051 | ||
1052 | i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { | |
1053 | rockchip,pins = | |
1054 | <2 RK_PA5 1 &pcfg_pull_none>; | |
1055 | }; | |
1056 | ||
1057 | i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { | |
1058 | rockchip,pins = | |
1059 | <2 RK_PA6 1 &pcfg_pull_none>; | |
1060 | }; | |
1061 | ||
1062 | i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { | |
1063 | rockchip,pins = | |
1064 | <2 RK_PA7 1 &pcfg_pull_none>; | |
1065 | }; | |
1066 | ||
1067 | i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { | |
1068 | rockchip,pins = | |
1069 | <2 RK_PB0 1 &pcfg_pull_none>; | |
1070 | }; | |
1071 | ||
1072 | i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { | |
1073 | rockchip,pins = | |
1074 | <2 RK_PB1 1 &pcfg_pull_none>; | |
1075 | }; | |
1076 | ||
1077 | i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { | |
1078 | rockchip,pins = | |
1079 | <2 RK_PB2 1 &pcfg_pull_none>; | |
1080 | }; | |
1081 | ||
1082 | i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { | |
1083 | rockchip,pins = | |
1084 | <2 RK_PB3 1 &pcfg_pull_none>; | |
1085 | }; | |
1086 | ||
1087 | i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { | |
1088 | rockchip,pins = | |
1089 | <2 RK_PB4 1 &pcfg_pull_none>; | |
1090 | }; | |
1091 | ||
1092 | i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { | |
1093 | rockchip,pins = | |
1094 | <2 RK_PB5 1 &pcfg_pull_none>; | |
1095 | }; | |
1096 | ||
1097 | i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 { | |
1098 | rockchip,pins = | |
1099 | <2 RK_PB6 1 &pcfg_pull_none>; | |
1100 | }; | |
1101 | ||
1102 | i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 { | |
1103 | rockchip,pins = | |
1104 | <2 RK_PB7 1 &pcfg_pull_none>; | |
1105 | }; | |
1106 | ||
1107 | i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 { | |
1108 | rockchip,pins = | |
1109 | <2 RK_PC0 1 &pcfg_pull_none>; | |
1110 | }; | |
1111 | }; | |
1112 | ||
1113 | i2s_8ch_1_m0 { | |
1114 | i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { | |
1115 | rockchip,pins = | |
1116 | <1 RK_PA2 2 &pcfg_pull_none>; | |
1117 | }; | |
1118 | ||
1119 | i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { | |
1120 | rockchip,pins = | |
1121 | <1 RK_PA3 2 &pcfg_pull_none>; | |
1122 | }; | |
1123 | ||
1124 | i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { | |
1125 | rockchip,pins = | |
1126 | <1 RK_PA4 2 &pcfg_pull_none>; | |
1127 | }; | |
1128 | ||
1129 | i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { | |
1130 | rockchip,pins = | |
1131 | <1 RK_PA5 2 &pcfg_pull_none>; | |
1132 | }; | |
1133 | ||
1134 | i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { | |
1135 | rockchip,pins = | |
1136 | <1 RK_PA6 2 &pcfg_pull_none>; | |
1137 | }; | |
1138 | ||
1139 | i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { | |
1140 | rockchip,pins = | |
1141 | <1 RK_PA7 2 &pcfg_pull_none>; | |
1142 | }; | |
1143 | ||
1144 | i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 { | |
1145 | rockchip,pins = | |
1146 | <1 RK_PB0 2 &pcfg_pull_none>; | |
1147 | }; | |
1148 | ||
1149 | i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 { | |
1150 | rockchip,pins = | |
1151 | <1 RK_PB1 2 &pcfg_pull_none>; | |
1152 | }; | |
1153 | ||
1154 | i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 { | |
1155 | rockchip,pins = | |
1156 | <1 RK_PB2 2 &pcfg_pull_none>; | |
1157 | }; | |
1158 | ||
1159 | i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 { | |
1160 | rockchip,pins = | |
1161 | <1 RK_PB3 2 &pcfg_pull_none>; | |
1162 | }; | |
1163 | }; | |
1164 | ||
1165 | i2s_8ch_1_m1 { | |
1166 | i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { | |
1167 | rockchip,pins = | |
1168 | <1 RK_PB4 2 &pcfg_pull_none>; | |
1169 | }; | |
1170 | ||
1171 | i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { | |
1172 | rockchip,pins = | |
1173 | <1 RK_PB5 2 &pcfg_pull_none>; | |
1174 | }; | |
1175 | ||
1176 | i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { | |
1177 | rockchip,pins = | |
1178 | <1 RK_PB6 2 &pcfg_pull_none>; | |
1179 | }; | |
1180 | ||
1181 | i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { | |
1182 | rockchip,pins = | |
1183 | <1 RK_PB7 2 &pcfg_pull_none>; | |
1184 | }; | |
1185 | ||
1186 | i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { | |
1187 | rockchip,pins = | |
1188 | <1 RK_PC0 2 &pcfg_pull_none>; | |
1189 | }; | |
1190 | ||
1191 | i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { | |
1192 | rockchip,pins = | |
1193 | <1 RK_PC1 2 &pcfg_pull_none>; | |
1194 | }; | |
1195 | ||
1196 | i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 { | |
1197 | rockchip,pins = | |
1198 | <1 RK_PC2 2 &pcfg_pull_none>; | |
1199 | }; | |
1200 | ||
1201 | i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 { | |
1202 | rockchip,pins = | |
1203 | <1 RK_PC3 2 &pcfg_pull_none>; | |
1204 | }; | |
1205 | ||
1206 | i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 { | |
1207 | rockchip,pins = | |
1208 | <1 RK_PC4 2 &pcfg_pull_none>; | |
1209 | }; | |
1210 | ||
1211 | i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 { | |
1212 | rockchip,pins = | |
1213 | <1 RK_PC5 2 &pcfg_pull_none>; | |
1214 | }; | |
1215 | }; | |
1216 | ||
1217 | pdm_m0 { | |
1218 | pdm_m0_clk: pdm-m0-clk { | |
1219 | rockchip,pins = | |
1220 | <1 RK_PA4 3 &pcfg_pull_none>; | |
1221 | }; | |
1222 | ||
1223 | pdm_m0_sdi0: pdm-m0-sdi0 { | |
1224 | rockchip,pins = | |
1225 | <1 RK_PB3 3 &pcfg_pull_none>; | |
1226 | }; | |
1227 | ||
1228 | pdm_m0_sdi1: pdm-m0-sdi1 { | |
1229 | rockchip,pins = | |
1230 | <1 RK_PB2 3 &pcfg_pull_none>; | |
1231 | }; | |
1232 | ||
1233 | pdm_m0_sdi2: pdm-m0-sdi2 { | |
1234 | rockchip,pins = | |
1235 | <1 RK_PB1 3 &pcfg_pull_none>; | |
1236 | }; | |
1237 | ||
1238 | pdm_m0_sdi3: pdm-m0-sdi3 { | |
1239 | rockchip,pins = | |
1240 | <1 RK_PB0 3 &pcfg_pull_none>; | |
1241 | }; | |
1242 | }; | |
1243 | ||
1244 | pdm_m1 { | |
1245 | pdm_m1_clk: pdm-m1-clk { | |
1246 | rockchip,pins = | |
1247 | <1 RK_PB6 4 &pcfg_pull_none>; | |
1248 | }; | |
1249 | ||
1250 | pdm_m1_sdi0: pdm-m1-sdi0 { | |
1251 | rockchip,pins = | |
1252 | <1 RK_PC5 4 &pcfg_pull_none>; | |
1253 | }; | |
1254 | ||
1255 | pdm_m1_sdi1: pdm-m1-sdi1 { | |
1256 | rockchip,pins = | |
1257 | <1 RK_PC4 4 &pcfg_pull_none>; | |
1258 | }; | |
1259 | ||
1260 | pdm_m1_sdi2: pdm-m1-sdi2 { | |
1261 | rockchip,pins = | |
1262 | <1 RK_PC3 4 &pcfg_pull_none>; | |
1263 | }; | |
1264 | ||
1265 | pdm_m1_sdi3: pdm-m1-sdi3 { | |
1266 | rockchip,pins = | |
1267 | <1 RK_PC2 4 &pcfg_pull_none>; | |
1268 | }; | |
1269 | }; | |
1270 | ||
1271 | pdm_m2 { | |
1272 | pdm_m2_clkm: pdm-m2-clkm { | |
1273 | rockchip,pins = | |
1274 | <2 RK_PA4 3 &pcfg_pull_none>; | |
1275 | }; | |
1276 | ||
1277 | pdm_m2_clk: pdm-m2-clk { | |
1278 | rockchip,pins = | |
1279 | <2 RK_PA6 2 &pcfg_pull_none>; | |
1280 | }; | |
1281 | ||
1282 | pdm_m2_sdi0: pdm-m2-sdi0 { | |
1283 | rockchip,pins = | |
1284 | <2 RK_PB5 2 &pcfg_pull_none>; | |
1285 | }; | |
1286 | ||
1287 | pdm_m2_sdi1: pdm-m2-sdi1 { | |
1288 | rockchip,pins = | |
1289 | <2 RK_PB6 2 &pcfg_pull_none>; | |
1290 | }; | |
1291 | ||
1292 | pdm_m2_sdi2: pdm-m2-sdi2 { | |
1293 | rockchip,pins = | |
1294 | <2 RK_PB7 2 &pcfg_pull_none>; | |
1295 | }; | |
1296 | ||
1297 | pdm_m2_sdi3: pdm-m2-sdi3 { | |
1298 | rockchip,pins = | |
1299 | <2 RK_PC0 2 &pcfg_pull_none>; | |
1300 | }; | |
1301 | }; | |
1302 | ||
1303 | pwm0 { | |
1304 | pwm0_pin: pwm0-pin { | |
1305 | rockchip,pins = | |
1306 | <0 RK_PB5 1 &pcfg_pull_none>; | |
1307 | }; | |
1308 | ||
1309 | pwm0_pin_pull_down: pwm0-pin-pull-down { | |
1310 | rockchip,pins = | |
1311 | <0 RK_PB5 1 &pcfg_pull_down>; | |
1312 | }; | |
1313 | }; | |
1314 | ||
1315 | pwm1 { | |
1316 | pwm1_pin: pwm1-pin { | |
1317 | rockchip,pins = | |
1318 | <0 RK_PB6 1 &pcfg_pull_none>; | |
1319 | }; | |
1320 | ||
1321 | pwm1_pin_pull_down: pwm1-pin-pull-down { | |
1322 | rockchip,pins = | |
1323 | <0 RK_PB6 1 &pcfg_pull_down>; | |
1324 | }; | |
1325 | }; | |
1326 | ||
1327 | pwm2 { | |
1328 | pwm2_pin: pwm2-pin { | |
1329 | rockchip,pins = | |
1330 | <0 RK_PB7 1 &pcfg_pull_none>; | |
1331 | }; | |
1332 | ||
1333 | pwm2_pin_pull_down: pwm2-pin-pull-down { | |
1334 | rockchip,pins = | |
1335 | <0 RK_PB7 1 &pcfg_pull_down>; | |
1336 | }; | |
1337 | }; | |
1338 | ||
1339 | pwm3 { | |
1340 | pwm3_pin: pwm3-pin { | |
1341 | rockchip,pins = | |
1342 | <0 RK_PC0 1 &pcfg_pull_none>; | |
1343 | }; | |
1344 | ||
1345 | pwm3_pin_pull_down: pwm3-pin-pull-down { | |
1346 | rockchip,pins = | |
1347 | <0 RK_PC0 1 &pcfg_pull_down>; | |
1348 | }; | |
1349 | }; | |
1350 | ||
1351 | pwm4 { | |
1352 | pwm4_pin: pwm4-pin { | |
1353 | rockchip,pins = | |
1354 | <0 RK_PA1 2 &pcfg_pull_none>; | |
1355 | }; | |
1356 | ||
1357 | pwm4_pin_pull_down: pwm4-pin-pull-down { | |
1358 | rockchip,pins = | |
1359 | <0 RK_PA1 2 &pcfg_pull_down>; | |
1360 | }; | |
1361 | }; | |
1362 | ||
1363 | pwm5 { | |
1364 | pwm5_pin: pwm5-pin { | |
1365 | rockchip,pins = | |
1366 | <0 RK_PC1 2 &pcfg_pull_none>; | |
1367 | }; | |
1368 | ||
1369 | pwm5_pin_pull_down: pwm5-pin-pull-down { | |
1370 | rockchip,pins = | |
1371 | <0 RK_PC1 2 &pcfg_pull_down>; | |
1372 | }; | |
1373 | }; | |
1374 | ||
1375 | pwm6 { | |
1376 | pwm6_pin: pwm6-pin { | |
1377 | rockchip,pins = | |
1378 | <0 RK_PC2 2 &pcfg_pull_none>; | |
1379 | }; | |
1380 | ||
1381 | pwm6_pin_pull_down: pwm6-pin-pull-down { | |
1382 | rockchip,pins = | |
1383 | <0 RK_PC2 2 &pcfg_pull_down>; | |
1384 | }; | |
1385 | }; | |
1386 | ||
1387 | pwm7 { | |
1388 | pwm7_pin: pwm7-pin { | |
1389 | rockchip,pins = | |
1390 | <2 RK_PB0 2 &pcfg_pull_none>; | |
1391 | }; | |
1392 | ||
1393 | pwm7_pin_pull_down: pwm7-pin-pull-down { | |
1394 | rockchip,pins = | |
1395 | <2 RK_PB0 2 &pcfg_pull_down>; | |
1396 | }; | |
1397 | }; | |
1398 | ||
1399 | pwm8 { | |
1400 | pwm8_pin: pwm8-pin { | |
1401 | rockchip,pins = | |
1402 | <2 RK_PB2 2 &pcfg_pull_none>; | |
1403 | }; | |
1404 | ||
1405 | pwm8_pin_pull_down: pwm8-pin-pull-down { | |
1406 | rockchip,pins = | |
1407 | <2 RK_PB2 2 &pcfg_pull_down>; | |
1408 | }; | |
1409 | }; | |
1410 | ||
1411 | pwm9 { | |
1412 | pwm9_pin: pwm9-pin { | |
1413 | rockchip,pins = | |
1414 | <2 RK_PB3 2 &pcfg_pull_none>; | |
1415 | }; | |
1416 | ||
1417 | pwm9_pin_pull_down: pwm9-pin-pull-down { | |
1418 | rockchip,pins = | |
1419 | <2 RK_PB3 2 &pcfg_pull_down>; | |
1420 | }; | |
1421 | }; | |
1422 | ||
1423 | pwm10 { | |
1424 | pwm10_pin: pwm10-pin { | |
1425 | rockchip,pins = | |
1426 | <2 RK_PB4 2 &pcfg_pull_none>; | |
1427 | }; | |
1428 | ||
1429 | pwm10_pin_pull_down: pwm10-pin-pull-down { | |
1430 | rockchip,pins = | |
1431 | <2 RK_PB4 2 &pcfg_pull_down>; | |
1432 | }; | |
1433 | }; | |
1434 | ||
1435 | pwm11 { | |
1436 | pwm11_pin: pwm11-pin { | |
1437 | rockchip,pins = | |
1438 | <2 RK_PC0 4 &pcfg_pull_none>; | |
1439 | }; | |
1440 | ||
1441 | pwm11_pin_pull_down: pwm11-pin-pull-down { | |
1442 | rockchip,pins = | |
1443 | <2 RK_PC0 4 &pcfg_pull_down>; | |
1444 | }; | |
1445 | }; | |
1446 | ||
1447 | rtc { | |
1448 | rtc_32k: rtc-32k { | |
1449 | rockchip,pins = | |
1450 | <0 RK_PC3 1 &pcfg_pull_none>; | |
1451 | }; | |
1452 | }; | |
1453 | ||
1454 | sdmmc { | |
1455 | sdmmc_clk: sdmmc-clk { | |
1456 | rockchip,pins = | |
1457 | <4 RK_PD5 1 &pcfg_pull_none_4ma>; | |
1458 | }; | |
1459 | ||
1460 | sdmmc_cmd: sdmmc-cmd { | |
1461 | rockchip,pins = | |
1462 | <4 RK_PD4 1 &pcfg_pull_up_4ma>; | |
1463 | }; | |
1464 | ||
1465 | sdmmc_det: sdmmc-det { | |
1466 | rockchip,pins = | |
1467 | <0 RK_PA3 1 &pcfg_pull_up_4ma>; | |
1468 | }; | |
1469 | ||
1470 | sdmmc_pwren: sdmmc-pwren { | |
1471 | rockchip,pins = | |
1472 | <4 RK_PD6 1 &pcfg_pull_none_4ma>; | |
1473 | }; | |
1474 | ||
1475 | sdmmc_bus1: sdmmc-bus1 { | |
1476 | rockchip,pins = | |
1477 | <4 RK_PD0 1 &pcfg_pull_up_4ma>; | |
1478 | }; | |
1479 | ||
1480 | sdmmc_bus4: sdmmc-bus4 { | |
1481 | rockchip,pins = | |
1482 | <4 RK_PD0 1 &pcfg_pull_up_4ma>, | |
1483 | <4 RK_PD1 1 &pcfg_pull_up_4ma>, | |
1484 | <4 RK_PD2 1 &pcfg_pull_up_4ma>, | |
1485 | <4 RK_PD3 1 &pcfg_pull_up_4ma>; | |
1486 | }; | |
1487 | }; | |
1488 | ||
1489 | sdio { | |
1490 | sdio_clk: sdio-clk { | |
1491 | rockchip,pins = | |
1492 | <4 RK_PA5 1 &pcfg_pull_none_8ma>; | |
1493 | }; | |
1494 | ||
1495 | sdio_cmd: sdio-cmd { | |
1496 | rockchip,pins = | |
1497 | <4 RK_PA4 1 &pcfg_pull_up_8ma>; | |
1498 | }; | |
1499 | ||
1500 | sdio_pwren: sdio-pwren { | |
1501 | rockchip,pins = | |
1502 | <0 RK_PA2 1 &pcfg_pull_none_8ma>; | |
1503 | }; | |
1504 | ||
1505 | sdio_wrpt: sdio-wrpt { | |
1506 | rockchip,pins = | |
1507 | <0 RK_PA1 1 &pcfg_pull_none_8ma>; | |
1508 | }; | |
1509 | ||
1510 | sdio_intn: sdio-intn { | |
1511 | rockchip,pins = | |
1512 | <0 RK_PA0 1 &pcfg_pull_none_8ma>; | |
1513 | }; | |
1514 | ||
1515 | sdio_bus1: sdio-bus1 { | |
1516 | rockchip,pins = | |
1517 | <4 RK_PA0 1 &pcfg_pull_up_8ma>; | |
1518 | }; | |
1519 | ||
1520 | sdio_bus4: sdio-bus4 { | |
1521 | rockchip,pins = | |
1522 | <4 RK_PA0 1 &pcfg_pull_up_8ma>, | |
1523 | <4 RK_PA1 1 &pcfg_pull_up_8ma>, | |
1524 | <4 RK_PA2 1 &pcfg_pull_up_8ma>, | |
1525 | <4 RK_PA3 1 &pcfg_pull_up_8ma>; | |
1526 | }; | |
1527 | }; | |
1528 | ||
1529 | spdif_in { | |
1530 | spdif_in: spdif-in { | |
1531 | rockchip,pins = | |
1532 | <0 RK_PC2 1 &pcfg_pull_none>; | |
1533 | }; | |
1534 | }; | |
1535 | ||
1536 | spdif_out { | |
1537 | spdif_out: spdif-out { | |
1538 | rockchip,pins = | |
1539 | <0 RK_PC1 1 &pcfg_pull_none>; | |
1540 | }; | |
1541 | }; | |
1542 | ||
1543 | spi0 { | |
1544 | spi0_clk: spi0-clk { | |
1545 | rockchip,pins = | |
1546 | <2 RK_PA2 2 &pcfg_pull_up_4ma>; | |
1547 | }; | |
1548 | ||
1549 | spi0_csn0: spi0-csn0 { | |
1550 | rockchip,pins = | |
1551 | <2 RK_PA3 2 &pcfg_pull_up_4ma>; | |
1552 | }; | |
1553 | ||
1554 | spi0_miso: spi0-miso { | |
1555 | rockchip,pins = | |
1556 | <2 RK_PA0 2 &pcfg_pull_up_4ma>; | |
1557 | }; | |
1558 | ||
1559 | spi0_mosi: spi0-mosi { | |
1560 | rockchip,pins = | |
1561 | <2 RK_PA1 2 &pcfg_pull_up_4ma>; | |
1562 | }; | |
1563 | }; | |
1564 | ||
1565 | spi1 { | |
1566 | spi1_clk: spi1-clk { | |
1567 | rockchip,pins = | |
1568 | <3 RK_PB3 3 &pcfg_pull_up_4ma>; | |
1569 | }; | |
1570 | ||
1571 | spi1_csn0: spi1-csn0 { | |
1572 | rockchip,pins = | |
1573 | <3 RK_PB5 3 &pcfg_pull_up_4ma>; | |
1574 | }; | |
1575 | ||
1576 | spi1_miso: spi1-miso { | |
1577 | rockchip,pins = | |
1578 | <3 RK_PB2 3 &pcfg_pull_up_4ma>; | |
1579 | }; | |
1580 | ||
1581 | spi1_mosi: spi1-mosi { | |
1582 | rockchip,pins = | |
1583 | <3 RK_PB4 3 &pcfg_pull_up_4ma>; | |
1584 | }; | |
1585 | }; | |
1586 | ||
1587 | spi1-m1 { | |
1588 | spi1m1_miso: spi1m1-miso { | |
1589 | rockchip,pins = | |
1590 | <2 RK_PA4 2 &pcfg_pull_up_4ma>; | |
1591 | }; | |
1592 | ||
1593 | spi1m1_mosi: spi1m1-mosi { | |
1594 | rockchip,pins = | |
1595 | <2 RK_PA5 2 &pcfg_pull_up_4ma>; | |
1596 | }; | |
1597 | ||
1598 | spi1m1_clk: spi1m1-clk { | |
1599 | rockchip,pins = | |
1600 | <2 RK_PA7 2 &pcfg_pull_up_4ma>; | |
1601 | }; | |
1602 | ||
1603 | spi1m1_csn0: spi1m1-csn0 { | |
1604 | rockchip,pins = | |
1605 | <2 RK_PB1 2 &pcfg_pull_up_4ma>; | |
1606 | }; | |
1607 | }; | |
1608 | ||
1609 | spi2 { | |
1610 | spi2_clk: spi2-clk { | |
1611 | rockchip,pins = | |
1612 | <1 RK_PD0 3 &pcfg_pull_up_4ma>; | |
1613 | }; | |
1614 | ||
1615 | spi2_csn0: spi2-csn0 { | |
1616 | rockchip,pins = | |
1617 | <1 RK_PD1 3 &pcfg_pull_up_4ma>; | |
1618 | }; | |
1619 | ||
1620 | spi2_miso: spi2-miso { | |
1621 | rockchip,pins = | |
1622 | <1 RK_PC6 3 &pcfg_pull_up_4ma>; | |
1623 | }; | |
1624 | ||
1625 | spi2_mosi: spi2-mosi { | |
1626 | rockchip,pins = | |
1627 | <1 RK_PC7 3 &pcfg_pull_up_4ma>; | |
1628 | }; | |
1629 | }; | |
1630 | ||
1631 | tsadc { | |
1632 | tsadc_otp_gpio: tsadc-otp-gpio { | |
1633 | rockchip,pins = | |
1634 | <0 RK_PB2 0 &pcfg_pull_none>; | |
1635 | }; | |
1636 | ||
1637 | tsadc_otp_out: tsadc-otp-out { | |
1638 | rockchip,pins = | |
1639 | <0 RK_PB2 1 &pcfg_pull_none>; | |
1640 | }; | |
1641 | }; | |
1642 | ||
1643 | uart0 { | |
1644 | uart0_xfer: uart0-xfer { | |
1645 | rockchip,pins = | |
1646 | <2 RK_PA1 1 &pcfg_pull_up>, | |
1647 | <2 RK_PA0 1 &pcfg_pull_up>; | |
1648 | }; | |
1649 | ||
1650 | uart0_cts: uart0-cts { | |
1651 | rockchip,pins = | |
1652 | <2 RK_PA2 1 &pcfg_pull_none>; | |
1653 | }; | |
1654 | ||
1655 | uart0_rts: uart0-rts { | |
1656 | rockchip,pins = | |
1657 | <2 RK_PA3 1 &pcfg_pull_none>; | |
1658 | }; | |
1659 | ||
1660 | uart0_rts_gpio: uart0-rts-gpio { | |
1661 | rockchip,pins = | |
1662 | <2 RK_PA3 0 &pcfg_pull_none>; | |
1663 | }; | |
1664 | }; | |
1665 | ||
1666 | uart1 { | |
1667 | uart1_xfer: uart1-xfer { | |
1668 | rockchip,pins = | |
1669 | <1 RK_PD1 1 &pcfg_pull_up>, | |
1670 | <1 RK_PD0 1 &pcfg_pull_up>; | |
1671 | }; | |
1672 | ||
1673 | uart1_cts: uart1-cts { | |
1674 | rockchip,pins = | |
1675 | <1 RK_PC6 1 &pcfg_pull_none>; | |
1676 | }; | |
1677 | ||
1678 | uart1_rts: uart1-rts { | |
1679 | rockchip,pins = | |
1680 | <1 RK_PC7 1 &pcfg_pull_none>; | |
1681 | }; | |
1682 | }; | |
1683 | ||
1684 | uart2-m0 { | |
1685 | uart2m0_xfer: uart2m0-xfer { | |
1686 | rockchip,pins = | |
1687 | <1 RK_PC7 2 &pcfg_pull_up>, | |
1688 | <1 RK_PC6 2 &pcfg_pull_up>; | |
1689 | }; | |
1690 | }; | |
1691 | ||
1692 | uart2-m1 { | |
1693 | uart2m1_xfer: uart2m1-xfer { | |
1694 | rockchip,pins = | |
1695 | <4 RK_PD3 2 &pcfg_pull_up>, | |
1696 | <4 RK_PD2 2 &pcfg_pull_up>; | |
1697 | }; | |
1698 | }; | |
1699 | ||
1700 | uart3 { | |
1701 | uart3_xfer: uart3-xfer { | |
1702 | rockchip,pins = | |
1703 | <3 RK_PB5 4 &pcfg_pull_up>, | |
1704 | <3 RK_PB4 4 &pcfg_pull_up>; | |
1705 | }; | |
1706 | }; | |
1707 | ||
1708 | uart3-m1 { | |
1709 | uart3m1_xfer: uart3m1-xfer { | |
1710 | rockchip,pins = | |
1711 | <0 RK_PC2 3 &pcfg_pull_up>, | |
1712 | <0 RK_PC1 3 &pcfg_pull_up>; | |
1713 | }; | |
1714 | }; | |
1715 | ||
1716 | uart4 { | |
1717 | uart4_xfer: uart4-xfer { | |
1718 | rockchip,pins = | |
1719 | <4 RK_PB1 1 &pcfg_pull_up>, | |
1720 | <4 RK_PB0 1 &pcfg_pull_up>; | |
1721 | }; | |
1722 | ||
1723 | uart4_cts: uart4-cts { | |
1724 | rockchip,pins = | |
1725 | <4 RK_PA6 1 &pcfg_pull_none>; | |
1726 | }; | |
1727 | ||
1728 | uart4_rts: uart4-rts { | |
1729 | rockchip,pins = | |
1730 | <4 RK_PA7 1 &pcfg_pull_none>; | |
1731 | }; | |
1732 | ||
1733 | uart4_rts_gpio: uart4-rts-gpio { | |
1734 | rockchip,pins = | |
1735 | <4 RK_PA7 0 &pcfg_pull_none>; | |
1736 | }; | |
1737 | }; | |
1738 | }; | |
1739 | }; |