[people/arne_f/kernel.git] / arch / arm64 / include / asm / assembler.h

/*
 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
 *
 * Copyright (C) 1996-2000 Russell King
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASSEMBLY__
#error "Only include this from assembly code"
#endif

#ifndef __ASM_ASSEMBLER_H
#define __ASM_ASSEMBLER_H

#include <asm/asm-offsets.h>
#include <asm/cpufeature.h>
#include <asm/mmu_context.h>
#include <asm/page.h>
#include <asm/pgtable-hwdef.h>
#include <asm/ptrace.h>
#include <asm/thread_info.h>

/*
 * Enable and disable interrupts.
 */
	.macro	disable_irq
	msr	daifset, #2
	.endm

	.macro	enable_irq
	msr	daifclr, #2
	.endm

	.macro	save_and_disable_irq, flags
	mrs	\flags, daif
	msr	daifset, #2
	.endm

	.macro	restore_irq, flags
	msr	daif, \flags
	.endm

/*
 * Enable and disable debug exceptions.
 */
	.macro	disable_dbg
	msr	daifset, #8
	.endm

	.macro	enable_dbg
	msr	daifclr, #8
	.endm

	.macro	disable_step_tsk, flgs, tmp
	tbz	\flgs, #TIF_SINGLESTEP, 9990f
	mrs	\tmp, mdscr_el1
	bic	\tmp, \tmp, #1
	msr	mdscr_el1, \tmp
	isb	// Synchronise with enable_dbg
9990:
	.endm

	.macro	enable_step_tsk, flgs, tmp
	tbz	\flgs, #TIF_SINGLESTEP, 9990f
	disable_dbg
	mrs	\tmp, mdscr_el1
	orr	\tmp, \tmp, #1
	msr	mdscr_el1, \tmp
9990:
	.endm

/*
 * Enable both debug exceptions and interrupts. This is likely to be
 * faster than two daifclr operations, since writes to this register
 * are self-synchronising.
 */
	.macro	enable_dbg_and_irq
	msr	daifclr, #(8 | 2)
	.endm

/*
 * SMP data memory barrier
 */
	.macro	smp_dmb, opt
	dmb	\opt
	.endm

/*
 * NOP sequence
 */
	.macro	nops, num
	.rept	\num
	nop
	.endr
	.endm

/*
 * Emit an entry into the exception table
 */
	.macro		_asm_extable, from, to
	.pushsection	__ex_table, "a"
	.align		3
	.long		(\from - .), (\to - .)
	.popsection
	.endm

#define USER(l, x...)				\
9999:	x;					\
	_asm_extable	9999b, l

/*
 * Register aliases.
 */
lr	.req	x30		// link register

/*
 * Vector entry
 */
	 .macro	ventry	label
	.align	7
	b	\label
	.endm

/*
 * Select code when configured for BE.
 */
#ifdef CONFIG_CPU_BIG_ENDIAN
#define CPU_BE(code...) code
#else
#define CPU_BE(code...)
#endif

/*
 * Select code when configured for LE.
 */
#ifdef CONFIG_CPU_BIG_ENDIAN
#define CPU_LE(code...)
#else
#define CPU_LE(code...) code
#endif

/*
 * Define a macro that constructs a 64-bit value by concatenating two
 * 32-bit registers. Note that on big endian systems the order of the
 * registers is swapped.
 */
#ifndef CONFIG_CPU_BIG_ENDIAN
	.macro	regs_to_64, rd, lbits, hbits
#else
	.macro	regs_to_64, rd, hbits, lbits
#endif
	orr	\rd, \lbits, \hbits, lsl #32
	.endm

/*
 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
 * <symbol> is within the range +/- 4 GB of the PC when running
 * in core kernel context. In module context, a movz/movk sequence
 * is used, since modules may be loaded far away from the kernel
 * when KASLR is in effect.
 */
	/*
	 * @dst: destination register (64 bit wide)
	 * @sym: name of the symbol
	 */
	.macro	adr_l, dst, sym
#ifndef MODULE
	adrp	\dst, \sym
	add	\dst, \dst, :lo12:\sym
#else
	movz	\dst, #:abs_g3:\sym
	movk	\dst, #:abs_g2_nc:\sym
	movk	\dst, #:abs_g1_nc:\sym
	movk	\dst, #:abs_g0_nc:\sym
#endif
	.endm

	/*
	 * @dst: destination register (32 or 64 bit wide)
	 * @sym: name of the symbol
	 * @tmp: optional 64-bit scratch register to be used if <dst> is a
	 *       32-bit wide register, in which case it cannot be used to hold
	 *       the address
	 */
	.macro	ldr_l, dst, sym, tmp=
#ifndef MODULE
	.ifb	\tmp
	adrp	\dst, \sym
	ldr	\dst, [\dst, :lo12:\sym]
	.else
	adrp	\tmp, \sym
	ldr	\dst, [\tmp, :lo12:\sym]
	.endif
#else
	.ifb	\tmp
	adr_l	\dst, \sym
	ldr	\dst, [\dst]
	.else
	adr_l	\tmp, \sym
	ldr	\dst, [\tmp]
	.endif
#endif
	.endm

	/*
	 * @src: source register (32 or 64 bit wide)
	 * @sym: name of the symbol
	 * @tmp: mandatory 64-bit scratch register to calculate the address
	 *       while <src> needs to be preserved.
	 */
	.macro	str_l, src, sym, tmp
#ifndef MODULE
	adrp	\tmp, \sym
	str	\src, [\tmp, :lo12:\sym]
#else
	adr_l	\tmp, \sym
	str	\src, [\tmp]
#endif
	.endm

	/*
	 * @dst: Result of per_cpu(sym, smp_processor_id())
	 * @sym: The name of the per-cpu variable
	 * @tmp: scratch register
	 */
	.macro adr_this_cpu, dst, sym, tmp
	adr_l	\dst, \sym
	mrs	\tmp, tpidr_el1
	add	\dst, \dst, \tmp
	.endm

	/*
	 * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
	 * @sym: The name of the per-cpu variable
	 * @tmp: scratch register
	 */
	.macro ldr_this_cpu dst, sym, tmp
	adr_l	\dst, \sym
	mrs	\tmp, tpidr_el1
	ldr	\dst, [\dst, \tmp]
	.endm

/*
 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
 */
	.macro	vma_vm_mm, rd, rn
	ldr	\rd, [\rn, #VMA_VM_MM]
	.endm

/*
 * mmid - get context id from mm pointer (mm->context.id)
 */
	.macro	mmid, rd, rn
	ldr	\rd, [\rn, #MM_CONTEXT_ID]
	.endm
/*
 * read_ctr - read CTR_EL0. If the system has mismatched
 * cache line sizes, provide the system wide safe value
 * from arm64_ftr_reg_ctrel0.sys_val
 */
	.macro	read_ctr, reg
alternative_if_not ARM64_MISMATCHED_CACHE_LINE_SIZE
	mrs	\reg, ctr_el0			// read CTR
	nop
alternative_else
	ldr_l	\reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
alternative_endif
	.endm


/*
 * raw_dcache_line_size - get the minimum D-cache line size on this CPU
 * from the CTR register.
 */
	.macro	raw_dcache_line_size, reg, tmp
	mrs	\tmp, ctr_el0			// read CTR
	ubfm	\tmp, \tmp, #16, #19		// cache line size encoding
	mov	\reg, #4			// bytes per word
	lsl	\reg, \reg, \tmp		// actual cache line size
	.endm

/*
 * dcache_line_size - get the safe D-cache line size across all CPUs
 */
	.macro	dcache_line_size, reg, tmp
	read_ctr	\tmp
	ubfm		\tmp, \tmp, #16, #19	// cache line size encoding
	mov		\reg, #4		// bytes per word
	lsl		\reg, \reg, \tmp	// actual cache line size
	.endm

/*
 * raw_icache_line_size - get the minimum I-cache line size on this CPU
 * from the CTR register.
 */
	.macro	raw_icache_line_size, reg, tmp
	mrs	\tmp, ctr_el0			// read CTR
	and	\tmp, \tmp, #0xf		// cache line size encoding
	mov	\reg, #4			// bytes per word
	lsl	\reg, \reg, \tmp		// actual cache line size
	.endm

/*
 * icache_line_size - get the safe I-cache line size across all CPUs
 */
	.macro	icache_line_size, reg, tmp
	read_ctr	\tmp
	and		\tmp, \tmp, #0xf	// cache line size encoding
	mov		\reg, #4		// bytes per word
	lsl		\reg, \reg, \tmp	// actual cache line size
	.endm

/*
 * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
 */
	.macro	tcr_set_idmap_t0sz, valreg, tmpreg
#ifndef CONFIG_ARM64_VA_BITS_48
	ldr_l	\tmpreg, idmap_t0sz
	bfi	\valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
#endif
	.endm

/*
 * Macro to perform a data cache maintenance for the interval
 * [kaddr, kaddr + size)
 *
 * 	op:		operation passed to dc instruction
 * 	domain:		domain used in dsb instruciton
 * 	kaddr:		starting virtual address of the region
 * 	size:		size of the region
 * 	Corrupts:	kaddr, size, tmp1, tmp2
 */
	.macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
	dcache_line_size \tmp1, \tmp2
	add	\size, \kaddr, \size
	sub	\tmp2, \tmp1, #1
	bic	\kaddr, \kaddr, \tmp2
9998:
	.if	(\op == cvau || \op == cvac)
alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
	dc	\op, \kaddr
alternative_else
	dc	civac, \kaddr
alternative_endif
	.elseif	(\op == cvap)
alternative_if ARM64_HAS_DCPOP
	sys 3, c7, c12, 1, \kaddr	// dc cvap
alternative_else
	dc	cvac, \kaddr
alternative_endif
	.else
	dc	\op, \kaddr
	.endif
	add	\kaddr, \kaddr, \tmp1
	cmp	\kaddr, \size
	b.lo	9998b
	dsb	\domain
	.endm

/*
 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
 */
	.macro	reset_pmuserenr_el0, tmpreg
	mrs	\tmpreg, id_aa64dfr0_el1	// Check ID_AA64DFR0_EL1 PMUVer
	sbfx	\tmpreg, \tmpreg, #8, #4
	cmp	\tmpreg, #1			// Skip if no PMU present
	b.lt	9000f
	msr	pmuserenr_el0, xzr		// Disable PMU access from EL0
9000:
	.endm

/*
 * copy_page - copy src to dest using temp registers t1-t8
 */
	.macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
9998:	ldp	\t1, \t2, [\src]
	ldp	\t3, \t4, [\src, #16]
	ldp	\t5, \t6, [\src, #32]
	ldp	\t7, \t8, [\src, #48]
	add	\src, \src, #64
	stnp	\t1, \t2, [\dest]
	stnp	\t3, \t4, [\dest, #16]
	stnp	\t5, \t6, [\dest, #32]
	stnp	\t7, \t8, [\dest, #48]
	add	\dest, \dest, #64
	tst	\src, #(PAGE_SIZE - 1)
	b.ne	9998b
	.endm

/*
 * Annotate a function as position independent, i.e., safe to be called before
 * the kernel virtual mapping is activated.
 */
#define ENDPIPROC(x)			\
	.globl	__pi_##x;		\
	.type 	__pi_##x, %function;	\
	.set	__pi_##x, x;		\
	.size	__pi_##x, . - x;	\
	ENDPROC(x)

	/*
	 * Emit a 64-bit absolute little endian symbol reference in a way that
	 * ensures that it will be resolved at build time, even when building a
	 * PIE binary. This requires cooperation from the linker script, which
	 * must emit the lo32/hi32 halves individually.
	 */
	.macro	le64sym, sym
	.long	\sym\()_lo32
	.long	\sym\()_hi32
	.endm

	/*
	 * mov_q - move an immediate constant into a 64-bit register using
	 *         between 2 and 4 movz/movk instructions (depending on the
	 *         magnitude and sign of the operand)
	 */
	.macro	mov_q, reg, val
	.if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
	movz	\reg, :abs_g1_s:\val
	.else
	.if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
	movz	\reg, :abs_g2_s:\val
	.else
	movz	\reg, :abs_g3:\val
	movk	\reg, :abs_g2_nc:\val
	.endif
	movk	\reg, :abs_g1_nc:\val
	.endif
	movk	\reg, :abs_g0_nc:\val
	.endm

/*
 * Return the current thread_info.
 */
	.macro	get_thread_info, rd
	mrs	\rd, sp_el0
	.endm

/*
 * Errata workaround prior to TTBR0_EL1 update
 *
 * 	val:	TTBR value with new BADDR, preserved
 * 	tmp0:	temporary register, clobbered
 * 	tmp1:	other temporary register, clobbered
 */
	.macro	pre_ttbr0_update_workaround, val, tmp0, tmp1
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
	mrs	\tmp0, ttbr0_el1
	mov	\tmp1, #FALKOR_RESERVED_ASID
	bfi	\tmp0, \tmp1, #48, #16		// reserved ASID + old BADDR
	msr	ttbr0_el1, \tmp0
	isb
	bfi	\tmp0, \val, #0, #48		// reserved ASID + new BADDR
	msr	ttbr0_el1, \tmp0
	isb
alternative_else_nop_endif
#endif
	.endm

/*
 * Errata workaround post TTBR0_EL1 update.
 */
	.macro	post_ttbr0_update_workaround
#ifdef CONFIG_CAVIUM_ERRATUM_27456
alternative_if ARM64_WORKAROUND_CAVIUM_27456
	ic	iallu
	dsb	nsh
	isb
alternative_else_nop_endif
#endif
	.endm

#endif	/* __ASM_ASSEMBLER_H */
Commit	Line	Data
0be7320a	1	/*
7b7293ae	2	* Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
0be7320a CM	3	*
	4	* Copyright (C) 1996-2000 Russell King
	5	* Copyright (C) 2012 ARM Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#ifndef __ASSEMBLY__
	20	#error "Only include this from assembly code"
	21	#endif
	22
f3e39273 MZ	23	#ifndef __ASM_ASSEMBLER_H
	24	#define __ASM_ASSEMBLER_H
	25
7b7293ae	26	#include <asm/asm-offsets.h>
823066d9	27	#include <asm/cpufeature.h>
38fd94b0	28	#include <asm/mmu_context.h>
5003dbde	29	#include <asm/page.h>
7b7293ae	30	#include <asm/pgtable-hwdef.h>
0be7320a	31	#include <asm/ptrace.h>
2a283070	32	#include <asm/thread_info.h>
0be7320a	33
0be7320a CM	34	/*
	35	* Enable and disable interrupts.
	36	*/
	37	.macro disable_irq
	38	msr daifset, #2
	39	.endm
	40
	41	.macro enable_irq
	42	msr daifclr, #2
	43	.endm
	44
4b65a5db CM	45	.macro save_and_disable_irq, flags
	46	mrs \flags, daif
	47	msr daifset, #2
	48	.endm
	49
	50	.macro restore_irq, flags
	51	msr daif, \flags
	52	.endm
	53
0be7320a CM	54	/*
	55	* Enable and disable debug exceptions.
	56	*/
	57	.macro disable_dbg
	58	msr daifset, #8
	59	.endm
	60
	61	.macro enable_dbg
	62	msr daifclr, #8
	63	.endm
	64
2a283070 WD	65	.macro disable_step_tsk, flgs, tmp
2a283070 WD	66	tbz \flgs, #TIF_SINGLESTEP, 9990f
0be7320a CM	67	mrs \tmp, mdscr_el1
	68	bic \tmp, \tmp, #1
	69	msr mdscr_el1, \tmp
2a283070 WD	70	isb // Synchronise with enable_dbg
2a283070 WD	71	9990:
0be7320a CM	72	.endm
0be7320a CM	73
2a283070 WD	74	.macro enable_step_tsk, flgs, tmp
	75	tbz \flgs, #TIF_SINGLESTEP, 9990f
	76	disable_dbg
0be7320a CM	77	mrs \tmp, mdscr_el1
	78	orr \tmp, \tmp, #1
	79	msr mdscr_el1, \tmp
2a283070	80	9990:
0be7320a CM	81	.endm
0be7320a CM	82
2a283070 WD	83	/*
	84	* Enable both debug exceptions and interrupts. This is likely to be
	85	* faster than two daifclr operations, since writes to this register
	86	* are self-synchronising.
	87	*/
	88	.macro enable_dbg_and_irq
	89	msr daifclr, #(8 \| 2)
0be7320a CM	90	.endm
	91
	92	/*
	93	* SMP data memory barrier
	94	*/
	95	.macro smp_dmb, opt
0be7320a	96	dmb \opt
0be7320a CM	97	.endm
0be7320a CM	98
f99a250c WD	99	/*
	100	* NOP sequence
	101	*/
	102	.macro nops, num
	103	.rept \num
	104	nop
	105	.endr
	106	.endm
	107
6c94f27a AB	108	/*
	109	* Emit an entry into the exception table
	110	*/
	111	.macro _asm_extable, from, to
	112	.pushsection __ex_table, "a"
	113	.align 3
	114	.long (\from - .), (\to - .)
	115	.popsection
	116	.endm
	117
0be7320a CM	118	#define USER(l, x...) \
0be7320a CM	119	9999: x; \
6c94f27a	120	_asm_extable 9999b, l
0be7320a CM	121
	122	/*
	123	* Register aliases.
	124	*/
	125	lr .req x30 // link register
dc637f1f MZ	126
	127	/*
	128	* Vector entry
	129	*/
	130	.macro ventry label
	131	.align 7
	132	b \label
	133	.endm
e68bedaa ML	134
	135	/*
	136	* Select code when configured for BE.
	137	*/
	138	#ifdef CONFIG_CPU_BIG_ENDIAN
	139	#define CPU_BE(code...) code
	140	#else
	141	#define CPU_BE(code...)
	142	#endif
	143
	144	/*
	145	* Select code when configured for LE.
	146	*/
	147	#ifdef CONFIG_CPU_BIG_ENDIAN
	148	#define CPU_LE(code...)
	149	#else
	150	#define CPU_LE(code...) code
	151	#endif
	152
55b89540 ML	153	/*
	154	* Define a macro that constructs a 64-bit value by concatenating two
	155	* 32-bit registers. Note that on big endian systems the order of the
	156	* registers is swapped.
	157	*/
	158	#ifndef CONFIG_CPU_BIG_ENDIAN
	159	.macro regs_to_64, rd, lbits, hbits
	160	#else
	161	.macro regs_to_64, rd, hbits, lbits
	162	#endif
	163	orr \rd, \lbits, \hbits, lsl #32
	164	.endm
f3e39273	165
b784a5d9 AB	166	/*
b784a5d9 AB	167	* Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
41c066f2 AB	168	* <symbol> is within the range +/- 4 GB of the PC when running
	169	* in core kernel context. In module context, a movz/movk sequence
	170	* is used, since modules may be loaded far away from the kernel
	171	* when KASLR is in effect.
b784a5d9 AB	172	*/
	173	/*
	174	* @dst: destination register (64 bit wide)
	175	* @sym: name of the symbol
b784a5d9	176	*/
41c066f2 AB	177	.macro adr_l, dst, sym
41c066f2 AB	178	#ifndef MODULE
b784a5d9 AB	179	adrp \dst, \sym
b784a5d9 AB	180	add \dst, \dst, :lo12:\sym
41c066f2 AB	181	#else
	182	movz \dst, #:abs_g3:\sym
	183	movk \dst, #:abs_g2_nc:\sym
	184	movk \dst, #:abs_g1_nc:\sym
	185	movk \dst, #:abs_g0_nc:\sym
	186	#endif
b784a5d9 AB	187	.endm
	188
	189	/*
	190	* @dst: destination register (32 or 64 bit wide)
	191	* @sym: name of the symbol
	192	* @tmp: optional 64-bit scratch register to be used if <dst> is a
	193	* 32-bit wide register, in which case it cannot be used to hold
	194	* the address
	195	*/
	196	.macro ldr_l, dst, sym, tmp=
41c066f2	197	#ifndef MODULE
b784a5d9 AB	198	.ifb \tmp
	199	adrp \dst, \sym
	200	ldr \dst, [\dst, :lo12:\sym]
	201	.else
	202	adrp \tmp, \sym
	203	ldr \dst, [\tmp, :lo12:\sym]
	204	.endif
41c066f2 AB	205	#else
	206	.ifb \tmp
	207	adr_l \dst, \sym
	208	ldr \dst, [\dst]
	209	.else
	210	adr_l \tmp, \sym
	211	ldr \dst, [\tmp]
	212	.endif
	213	#endif
b784a5d9 AB	214	.endm
	215
	216	/*
	217	* @src: source register (32 or 64 bit wide)
	218	* @sym: name of the symbol
	219	* @tmp: mandatory 64-bit scratch register to calculate the address
	220	* while <src> needs to be preserved.
	221	*/
	222	.macro str_l, src, sym, tmp
41c066f2	223	#ifndef MODULE
b784a5d9 AB	224	adrp \tmp, \sym
b784a5d9 AB	225	str \src, [\tmp, :lo12:\sym]
41c066f2 AB	226	#else
	227	adr_l \tmp, \sym
	228	str \src, [\tmp]
	229	#endif
b784a5d9 AB	230	.endm
b784a5d9 AB	231
aa4d5d3c	232	/*
1b7e2296	233	* @dst: Result of per_cpu(sym, smp_processor_id())
aa4d5d3c	234	* @sym: The name of the per-cpu variable
aa4d5d3c JM	235	* @tmp: scratch register
aa4d5d3c JM	236	*/
1b7e2296 MR	237	.macro adr_this_cpu, dst, sym, tmp
1b7e2296 MR	238	adr_l \dst, \sym
aa4d5d3c	239	mrs \tmp, tpidr_el1
1b7e2296 MR	240	add \dst, \dst, \tmp
	241	.endm
	242
	243	/*
	244	* @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
	245	* @sym: The name of the per-cpu variable
	246	* @tmp: scratch register
	247	*/
	248	.macro ldr_this_cpu dst, sym, tmp
	249	adr_l \dst, \sym
	250	mrs \tmp, tpidr_el1
	251	ldr \dst, [\dst, \tmp]
aa4d5d3c JM	252	.endm
aa4d5d3c JM	253
7b7293ae GL	254	/*
	255	* vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
	256	*/
	257	.macro vma_vm_mm, rd, rn
	258	ldr \rd, [\rn, #VMA_VM_MM]
	259	.endm
	260
	261	/*
	262	* mmid - get context id from mm pointer (mm->context.id)
	263	*/
	264	.macro mmid, rd, rn
	265	ldr \rd, [\rn, #MM_CONTEXT_ID]
	266	.endm
116c81f4 SP	267	/*
	268	* read_ctr - read CTR_EL0. If the system has mismatched
	269	* cache line sizes, provide the system wide safe value
	270	* from arm64_ftr_reg_ctrel0.sys_val
	271	*/
	272	.macro read_ctr, reg
	273	alternative_if_not ARM64_MISMATCHED_CACHE_LINE_SIZE
	274	mrs \reg, ctr_el0 // read CTR
	275	nop
	276	alternative_else
	277	ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
	278	alternative_endif
	279	.endm
	280
7b7293ae GL	281
7b7293ae GL	282	/*
072f0a63 SP	283	* raw_dcache_line_size - get the minimum D-cache line size on this CPU
072f0a63 SP	284	* from the CTR register.
7b7293ae	285	*/
072f0a63	286	.macro raw_dcache_line_size, reg, tmp
7b7293ae GL	287	mrs \tmp, ctr_el0 // read CTR
	288	ubfm \tmp, \tmp, #16, #19 // cache line size encoding
	289	mov \reg, #4 // bytes per word
	290	lsl \reg, \reg, \tmp // actual cache line size
	291	.endm
	292
	293	/*
072f0a63	294	* dcache_line_size - get the safe D-cache line size across all CPUs
7b7293ae	295	*/
072f0a63	296	.macro dcache_line_size, reg, tmp
116c81f4 SP	297	read_ctr \tmp
	298	ubfm \tmp, \tmp, #16, #19 // cache line size encoding
	299	mov \reg, #4 // bytes per word
	300	lsl \reg, \reg, \tmp // actual cache line size
072f0a63 SP	301	.endm
	302
	303	/*
	304	* raw_icache_line_size - get the minimum I-cache line size on this CPU
	305	* from the CTR register.
	306	*/
	307	.macro raw_icache_line_size, reg, tmp
7b7293ae GL	308	mrs \tmp, ctr_el0 // read CTR
	309	and \tmp, \tmp, #0xf // cache line size encoding
	310	mov \reg, #4 // bytes per word
	311	lsl \reg, \reg, \tmp // actual cache line size
	312	.endm
	313
072f0a63 SP	314	/*
	315	* icache_line_size - get the safe I-cache line size across all CPUs
	316	*/
	317	.macro icache_line_size, reg, tmp
116c81f4 SP	318	read_ctr \tmp
	319	and \tmp, \tmp, #0xf // cache line size encoding
	320	mov \reg, #4 // bytes per word
	321	lsl \reg, \reg, \tmp // actual cache line size
072f0a63 SP	322	.endm
072f0a63 SP	323
7b7293ae GL	324	/*
	325	* tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
	326	*/
	327	.macro tcr_set_idmap_t0sz, valreg, tmpreg
	328	#ifndef CONFIG_ARM64_VA_BITS_48
	329	ldr_l \tmpreg, idmap_t0sz
	330	bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
	331	#endif
	332	.endm
	333
	334	/*
	335	* Macro to perform a data cache maintenance for the interval
	336	* [kaddr, kaddr + size)
	337	*
	338	* op: operation passed to dc instruction
	339	* domain: domain used in dsb instruciton
	340	* kaddr: starting virtual address of the region
	341	* size: size of the region
	342	* Corrupts: kaddr, size, tmp1, tmp2
	343	*/
	344	.macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
	345	dcache_line_size \tmp1, \tmp2
	346	add \size, \kaddr, \size
	347	sub \tmp2, \tmp1, #1
	348	bic \kaddr, \kaddr, \tmp2
823066d9 AP	349	9998:
	350	.if (\op == cvau \|\| \op == cvac)
	351	alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
	352	dc \op, \kaddr
	353	alternative_else
	354	dc civac, \kaddr
d50e071f RM	355	alternative_endif
	356	.elseif (\op == cvap)
	357	alternative_if ARM64_HAS_DCPOP
	358	sys 3, c7, c12, 1, \kaddr // dc cvap
	359	alternative_else
	360	dc cvac, \kaddr
823066d9 AP	361	alternative_endif
	362	.else
	363	dc \op, \kaddr
	364	.endif
7b7293ae GL	365	add \kaddr, \kaddr, \tmp1
	366	cmp \kaddr, \size
	367	b.lo 9998b
	368	dsb \domain
	369	.endm
	370
	371	/*
	372	* reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
	373	*/
	374	.macro reset_pmuserenr_el0, tmpreg
	375	mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
	376	sbfx \tmpreg, \tmpreg, #8, #4
	377	cmp \tmpreg, #1 // Skip if no PMU present
	378	b.lt 9000f
	379	msr pmuserenr_el0, xzr // Disable PMU access from EL0
	380	9000:
	381	.endm
	382
5003dbde GL	383	/*
	384	* copy_page - copy src to dest using temp registers t1-t8
	385	*/
	386	.macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
	387	9998: ldp \t1, \t2, [\src]
	388	ldp \t3, \t4, [\src, #16]
	389	ldp \t5, \t6, [\src, #32]
	390	ldp \t7, \t8, [\src, #48]
	391	add \src, \src, #64
	392	stnp \t1, \t2, [\dest]
	393	stnp \t3, \t4, [\dest, #16]
	394	stnp \t5, \t6, [\dest, #32]
	395	stnp \t7, \t8, [\dest, #48]
	396	add \dest, \dest, #64
	397	tst \src, #(PAGE_SIZE - 1)
	398	b.ne 9998b
	399	.endm
	400
20791846 AB	401	/*
	402	* Annotate a function as position independent, i.e., safe to be called before
	403	* the kernel virtual mapping is activated.
	404	*/
	405	#define ENDPIPROC(x) \
	406	.globl __pi_##x; \
	407	.type __pi_##x, %function; \
	408	.set __pi_##x, x; \
	409	.size __pi_##x, . - x; \
	410	ENDPROC(x)
	411
6ad1fe5d AB	412	/*
	413	* Emit a 64-bit absolute little endian symbol reference in a way that
	414	* ensures that it will be resolved at build time, even when building a
	415	* PIE binary. This requires cooperation from the linker script, which
	416	* must emit the lo32/hi32 halves individually.
	417	*/
	418	.macro le64sym, sym
	419	.long \sym\()_lo32
	420	.long \sym\()_hi32
	421	.endm
	422
30b5ba5c AB	423	/*
	424	* mov_q - move an immediate constant into a 64-bit register using
	425	* between 2 and 4 movz/movk instructions (depending on the
	426	* magnitude and sign of the operand)
	427	*/
	428	.macro mov_q, reg, val
	429	.if (((\val) >> 31) == 0 \|\| ((\val) >> 31) == 0x1ffffffff)
	430	movz \reg, :abs_g1_s:\val
	431	.else
	432	.if (((\val) >> 47) == 0 \|\| ((\val) >> 47) == 0x1ffff)
	433	movz \reg, :abs_g2_s:\val
	434	.else
	435	movz \reg, :abs_g3:\val
	436	movk \reg, :abs_g2_nc:\val
	437	.endif
	438	movk \reg, :abs_g1_nc:\val
	439	.endif
	440	movk \reg, :abs_g0_nc:\val
	441	.endm
	442
4b65a5db CM	443	/*
	444	* Return the current thread_info.
	445	*/
	446	.macro get_thread_info, rd
	447	mrs \rd, sp_el0
	448	.endm
	449
38fd94b0 CC	450	/*
	451	* Errata workaround prior to TTBR0_EL1 update
	452	*
	453	* val: TTBR value with new BADDR, preserved
	454	* tmp0: temporary register, clobbered
	455	* tmp1: other temporary register, clobbered
	456	*/
	457	.macro pre_ttbr0_update_workaround, val, tmp0, tmp1
	458	#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
	459	alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
	460	mrs \tmp0, ttbr0_el1
	461	mov \tmp1, #FALKOR_RESERVED_ASID
	462	bfi \tmp0, \tmp1, #48, #16 // reserved ASID + old BADDR
	463	msr ttbr0_el1, \tmp0
	464	isb
	465	bfi \tmp0, \val, #0, #48 // reserved ASID + new BADDR
	466	msr ttbr0_el1, \tmp0
	467	isb
	468	alternative_else_nop_endif
	469	#endif
	470	.endm
	471
f33bcf03 CM	472	/*
	473	* Errata workaround post TTBR0_EL1 update.
	474	*/
	475	.macro post_ttbr0_update_workaround
	476	#ifdef CONFIG_CAVIUM_ERRATUM_27456
	477	alternative_if ARM64_WORKAROUND_CAVIUM_27456
	478	ic iallu
	479	dsb nsh
	480	isb
	481	alternative_else_nop_endif
	482	#endif
	483	.endm
	484
f3e39273	485	#endif /* __ASM_ASSEMBLER_H */