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caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
08e875c1 CM |
2 | /* |
3 | * Copyright (C) 2012 ARM Ltd. | |
08e875c1 CM |
4 | */ |
5 | #ifndef __ASM_SMP_H | |
6 | #define __ASM_SMP_H | |
7 | ||
1236cd2b SZ |
8 | #include <linux/const.h> |
9 | ||
bb905274 | 10 | /* Values for secondary_data.status */ |
66f16a24 | 11 | #define CPU_STUCK_REASON_SHIFT (8) |
1236cd2b | 12 | #define CPU_BOOT_STATUS_MASK ((UL(1) << CPU_STUCK_REASON_SHIFT) - 1) |
bb905274 | 13 | |
66f16a24 WD |
14 | #define CPU_MMU_OFF (-1) |
15 | #define CPU_BOOT_SUCCESS (0) | |
bb905274 | 16 | /* The cpu invoked ops->cpu_die, synchronise it with cpu_kill */ |
66f16a24 | 17 | #define CPU_KILL_ME (1) |
bb905274 | 18 | /* The cpu couldn't die gracefully and is looping in the kernel */ |
66f16a24 | 19 | #define CPU_STUCK_IN_KERNEL (2) |
bb905274 | 20 | /* Fatal system error detected by secondary CPU, crash the system */ |
66f16a24 WD |
21 | #define CPU_PANIC_KERNEL (3) |
22 | ||
1236cd2b SZ |
23 | #define CPU_STUCK_REASON_52_BIT_VA (UL(1) << CPU_STUCK_REASON_SHIFT) |
24 | #define CPU_STUCK_REASON_NO_GRAN (UL(2) << CPU_STUCK_REASON_SHIFT) | |
bb905274 SP |
25 | |
26 | #ifndef __ASSEMBLY__ | |
27 | ||
57c82954 MR |
28 | #include <asm/percpu.h> |
29 | ||
08e875c1 CM |
30 | #include <linux/threads.h> |
31 | #include <linux/cpumask.h> | |
32 | #include <linux/thread_info.h> | |
33 | ||
57c82954 MR |
34 | DECLARE_PER_CPU_READ_MOSTLY(int, cpu_number); |
35 | ||
36 | /* | |
37 | * We don't use this_cpu_read(cpu_number) as that has implicit writes to | |
38 | * preempt_count, and associated (compiler) barriers, that we'd like to avoid | |
39 | * the expense of. If we're preemptible, the value can be stale at use anyway. | |
34a6980c RM |
40 | * And we can't use this_cpu_ptr() either, as that winds up recursing back |
41 | * here under CONFIG_DEBUG_PREEMPT=y. | |
57c82954 | 42 | */ |
34a6980c | 43 | #define raw_smp_processor_id() (*raw_cpu_ptr(&cpu_number)) |
08e875c1 | 44 | |
262afe92 FF |
45 | /* |
46 | * Logical CPU mapping. | |
47 | */ | |
48 | extern u64 __cpu_logical_map[NR_CPUS]; | |
49 | #define cpu_logical_map(cpu) __cpu_logical_map[cpu] | |
50 | ||
08e875c1 CM |
51 | struct seq_file; |
52 | ||
53 | /* | |
54 | * generate IPI list text | |
55 | */ | |
56 | extern void show_ipi_list(struct seq_file *p, int prec); | |
57 | ||
58 | /* | |
59 | * Called from C code, this handles an IPI. | |
60 | */ | |
61 | extern void handle_IPI(int ipinr, struct pt_regs *regs); | |
62 | ||
63 | /* | |
fccb9a81 HG |
64 | * Discover the set of possible CPUs and determine their |
65 | * SMP operations. | |
08e875c1 | 66 | */ |
0f078336 | 67 | extern void smp_init_cpus(void); |
08e875c1 CM |
68 | |
69 | /* | |
70 | * Provide a function to raise an IPI cross call on CPUs in callmap. | |
71 | */ | |
72 | extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int)); | |
73 | ||
36310736 FW |
74 | extern void (*__smp_cross_call)(const struct cpumask *, unsigned int); |
75 | ||
08e875c1 CM |
76 | /* |
77 | * Called from the secondary holding pen, this is the secondary CPU entry point. | |
78 | */ | |
79 | asmlinkage void secondary_start_kernel(void); | |
80 | ||
81 | /* | |
82 | * Initial data for bringing up a secondary CPU. | |
bb905274 SP |
83 | * @stack - sp for the secondary CPU |
84 | * @status - Result passed back from the secondary CPU to | |
85 | * indicate failure. | |
08e875c1 CM |
86 | */ |
87 | struct secondary_data { | |
88 | void *stack; | |
c02433dd | 89 | struct task_struct *task; |
bb905274 | 90 | long status; |
08e875c1 | 91 | }; |
bb905274 | 92 | |
08e875c1 | 93 | extern struct secondary_data secondary_data; |
bb905274 | 94 | extern long __early_cpu_boot_status; |
652af899 | 95 | extern void secondary_entry(void); |
08e875c1 CM |
96 | |
97 | extern void arch_send_call_function_single_ipi(int cpu); | |
98 | extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); | |
99 | ||
5e89c55e LP |
100 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
101 | extern void arch_send_wakeup_ipi_mask(const struct cpumask *mask); | |
102 | #else | |
103 | static inline void arch_send_wakeup_ipi_mask(const struct cpumask *mask) | |
104 | { | |
105 | BUILD_BUG(); | |
106 | } | |
107 | #endif | |
108 | ||
9327e2c6 MR |
109 | extern int __cpu_disable(void); |
110 | ||
111 | extern void __cpu_die(unsigned int cpu); | |
112 | extern void cpu_die(void); | |
fce6361f | 113 | extern void cpu_die_early(void); |
9327e2c6 | 114 | |
c4bc34d2 SP |
115 | static inline void cpu_park_loop(void) |
116 | { | |
117 | for (;;) { | |
118 | wfe(); | |
119 | wfi(); | |
120 | } | |
121 | } | |
122 | ||
bb905274 SP |
123 | static inline void update_cpu_boot_status(int val) |
124 | { | |
125 | WRITE_ONCE(secondary_data.status, val); | |
126 | /* Ensure the visibility of the status update */ | |
127 | dsb(ishst); | |
128 | } | |
129 | ||
17eebd1a SP |
130 | /* |
131 | * The calling secondary CPU has detected serious configuration mismatch, | |
132 | * which calls for a kernel panic. Update the boot status and park the calling | |
133 | * CPU. | |
134 | */ | |
135 | static inline void cpu_panic_kernel(void) | |
136 | { | |
137 | update_cpu_boot_status(CPU_PANIC_KERNEL); | |
138 | cpu_park_loop(); | |
139 | } | |
140 | ||
5c492c3f JM |
141 | /* |
142 | * If a secondary CPU enters the kernel but fails to come online, | |
143 | * (e.g. due to mismatched features), and cannot exit the kernel, | |
144 | * we increment cpus_stuck_in_kernel and leave the CPU in a | |
145 | * quiesecent loop within the kernel text. The memory containing | |
146 | * this loop must not be re-used for anything else as the 'stuck' | |
147 | * core is executing it. | |
148 | * | |
149 | * This function is used to inhibit features like kexec and hibernate. | |
150 | */ | |
151 | bool cpus_are_stuck_in_kernel(void); | |
152 | ||
a88ce63b | 153 | extern void crash_smp_send_stop(void); |
78fd584c AT |
154 | extern bool smp_crash_stop_failed(void); |
155 | ||
bb905274 SP |
156 | #endif /* ifndef __ASSEMBLY__ */ |
157 | ||
08e875c1 | 158 | #endif /* ifndef __ASM_SMP_H */ |