[thirdparty/kernel/stable.git] / arch / arm64 / include / uapi / asm / kvm.h

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
 * Copyright (C) 2012,2013 - ARM Ltd
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * Derived from arch/arm/include/uapi/asm/kvm.h:
 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __ARM_KVM_H__
#define __ARM_KVM_H__

#define KVM_SPSR_EL1	0
#define KVM_SPSR_SVC	KVM_SPSR_EL1
#define KVM_SPSR_ABT	1
#define KVM_SPSR_UND	2
#define KVM_SPSR_IRQ	3
#define KVM_SPSR_FIQ	4
#define KVM_NR_SPSR	5

#ifndef __ASSEMBLY__
#include <linux/psci.h>
#include <linux/types.h>
#include <asm/ptrace.h>
#include <asm/sve_context.h>

#define __KVM_HAVE_GUEST_DEBUG
#define __KVM_HAVE_IRQ_LINE
#define __KVM_HAVE_READONLY_MEM
#define __KVM_HAVE_VCPU_EVENTS

#define KVM_COALESCED_MMIO_PAGE_OFFSET 1

#define KVM_REG_SIZE(id)						\
	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))

struct kvm_regs {
	struct user_pt_regs regs;	/* sp = sp_el0 */

	__u64	sp_el1;
	__u64	elr_el1;

	__u64	spsr[KVM_NR_SPSR];

	struct user_fpsimd_state fp_regs;
};

/*
 * Supported CPU Targets - Adding a new target type is not recommended,
 * unless there are some special registers not supported by the
 * genericv8 syreg table.
 */
#define KVM_ARM_TARGET_AEM_V8		0
#define KVM_ARM_TARGET_FOUNDATION_V8	1
#define KVM_ARM_TARGET_CORTEX_A57	2
#define KVM_ARM_TARGET_XGENE_POTENZA	3
#define KVM_ARM_TARGET_CORTEX_A53	4
/* Generic ARM v8 target */
#define KVM_ARM_TARGET_GENERIC_V8	5

#define KVM_ARM_NUM_TARGETS		6

/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
#define KVM_ARM_DEVICE_TYPE_SHIFT	0
#define KVM_ARM_DEVICE_TYPE_MASK	(0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
#define KVM_ARM_DEVICE_ID_SHIFT		16
#define KVM_ARM_DEVICE_ID_MASK		(0xffff << KVM_ARM_DEVICE_ID_SHIFT)

/* Supported device IDs */
#define KVM_ARM_DEVICE_VGIC_V2		0

/* Supported VGIC address types  */
#define KVM_VGIC_V2_ADDR_TYPE_DIST	0
#define KVM_VGIC_V2_ADDR_TYPE_CPU	1

#define KVM_VGIC_V2_DIST_SIZE		0x1000
#define KVM_VGIC_V2_CPU_SIZE		0x2000

/* Supported VGICv3 address types  */
#define KVM_VGIC_V3_ADDR_TYPE_DIST	2
#define KVM_VGIC_V3_ADDR_TYPE_REDIST	3
#define KVM_VGIC_ITS_ADDR_TYPE		4
#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION	5

#define KVM_VGIC_V3_DIST_SIZE		SZ_64K
#define KVM_VGIC_V3_REDIST_SIZE		(2 * SZ_64K)
#define KVM_VGIC_V3_ITS_SIZE		(2 * SZ_64K)

#define KVM_ARM_VCPU_POWER_OFF		0 /* CPU is started in OFF state */
#define KVM_ARM_VCPU_EL1_32BIT		1 /* CPU running a 32bit VM */
#define KVM_ARM_VCPU_PSCI_0_2		2 /* CPU uses PSCI v0.2 */
#define KVM_ARM_VCPU_PMU_V3		3 /* Support guest PMUv3 */
#define KVM_ARM_VCPU_SVE		4 /* enable SVE for this CPU */
#define KVM_ARM_VCPU_PTRAUTH_ADDRESS	5 /* VCPU uses address authentication */
#define KVM_ARM_VCPU_PTRAUTH_GENERIC	6 /* VCPU uses generic authentication */

struct kvm_vcpu_init {
	__u32 target;
	__u32 features[7];
};

struct kvm_sregs {
};

struct kvm_fpu {
};

/*
 * See v8 ARM ARM D7.3: Debug Registers
 *
 * The architectural limit is 16 debug registers of each type although
 * in practice there are usually less (see ID_AA64DFR0_EL1).
 *
 * Although the control registers are architecturally defined as 32
 * bits wide we use a 64 bit structure here to keep parity with
 * KVM_GET/SET_ONE_REG behaviour which treats all system registers as
 * 64 bit values. It also allows for the possibility of the
 * architecture expanding the control registers without having to
 * change the userspace ABI.
 */
#define KVM_ARM_MAX_DBG_REGS 16
struct kvm_guest_debug_arch {
	__u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];
	__u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];
	__u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];
	__u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
};

struct kvm_debug_exit_arch {
	__u32 hsr;
	__u64 far;	/* used for watchpoints */
};

/*
 * Architecture specific defines for kvm_guest_debug->control
 */

#define KVM_GUESTDBG_USE_SW_BP		(1 << 16)
#define KVM_GUESTDBG_USE_HW		(1 << 17)

struct kvm_sync_regs {
	/* Used with KVM_CAP_ARM_USER_IRQ */
	__u64 device_irq_level;
};

struct kvm_arch_memory_slot {
};

/* for KVM_GET/SET_VCPU_EVENTS */
struct kvm_vcpu_events {
	struct {
		__u8 serror_pending;
		__u8 serror_has_esr;
		__u8 ext_dabt_pending;
		/* Align it to 8 bytes */
		__u8 pad[5];
		__u64 serror_esr;
	} exception;
	__u32 reserved[12];
};

/* If you need to interpret the index values, here is the key: */
#define KVM_REG_ARM_COPROC_MASK		0x000000000FFF0000
#define KVM_REG_ARM_COPROC_SHIFT	16

/* Normal registers are mapped as coprocessor 16. */
#define KVM_REG_ARM_CORE		(0x0010 << KVM_REG_ARM_COPROC_SHIFT)
#define KVM_REG_ARM_CORE_REG(name)	(offsetof(struct kvm_regs, name) / sizeof(__u32))

/* Some registers need more space to represent values. */
#define KVM_REG_ARM_DEMUX		(0x0011 << KVM_REG_ARM_COPROC_SHIFT)
#define KVM_REG_ARM_DEMUX_ID_MASK	0x000000000000FF00
#define KVM_REG_ARM_DEMUX_ID_SHIFT	8
#define KVM_REG_ARM_DEMUX_ID_CCSIDR	(0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
#define KVM_REG_ARM_DEMUX_VAL_MASK	0x00000000000000FF
#define KVM_REG_ARM_DEMUX_VAL_SHIFT	0

/* AArch64 system registers */
#define KVM_REG_ARM64_SYSREG		(0x0013 << KVM_REG_ARM_COPROC_SHIFT)
#define KVM_REG_ARM64_SYSREG_OP0_MASK	0x000000000000c000
#define KVM_REG_ARM64_SYSREG_OP0_SHIFT	14
#define KVM_REG_ARM64_SYSREG_OP1_MASK	0x0000000000003800
#define KVM_REG_ARM64_SYSREG_OP1_SHIFT	11
#define KVM_REG_ARM64_SYSREG_CRN_MASK	0x0000000000000780
#define KVM_REG_ARM64_SYSREG_CRN_SHIFT	7
#define KVM_REG_ARM64_SYSREG_CRM_MASK	0x0000000000000078
#define KVM_REG_ARM64_SYSREG_CRM_SHIFT	3
#define KVM_REG_ARM64_SYSREG_OP2_MASK	0x0000000000000007
#define KVM_REG_ARM64_SYSREG_OP2_SHIFT	0

#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
	(((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
	KVM_REG_ARM64_SYSREG_ ## n ## _MASK)

#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
	(KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
	ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
	ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
	ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
	ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
	ARM64_SYS_REG_SHIFT_MASK(op2, OP2))

#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)

/* Physical Timer EL0 Registers */
#define KVM_REG_ARM_PTIMER_CTL		ARM64_SYS_REG(3, 3, 14, 2, 1)
#define KVM_REG_ARM_PTIMER_CVAL		ARM64_SYS_REG(3, 3, 14, 2, 2)
#define KVM_REG_ARM_PTIMER_CNT		ARM64_SYS_REG(3, 3, 14, 0, 1)

/* EL0 Virtual Timer Registers */
#define KVM_REG_ARM_TIMER_CTL		ARM64_SYS_REG(3, 3, 14, 3, 1)
#define KVM_REG_ARM_TIMER_CNT		ARM64_SYS_REG(3, 3, 14, 3, 2)
#define KVM_REG_ARM_TIMER_CVAL		ARM64_SYS_REG(3, 3, 14, 0, 2)

/* KVM-as-firmware specific pseudo-registers */
#define KVM_REG_ARM_FW			(0x0014 << KVM_REG_ARM_COPROC_SHIFT)
#define KVM_REG_ARM_FW_REG(r)		(KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
					 KVM_REG_ARM_FW | ((r) & 0xffff))
#define KVM_REG_ARM_PSCI_VERSION	KVM_REG_ARM_FW_REG(0)
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1	KVM_REG_ARM_FW_REG(1)
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL		0
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL		1
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED	2
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2	KVM_REG_ARM_FW_REG(2)
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL		0
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN		1
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL		2
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED	3
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED     	(1U << 4)

/* SVE registers */
#define KVM_REG_ARM64_SVE		(0x15 << KVM_REG_ARM_COPROC_SHIFT)

/* Z- and P-regs occupy blocks at the following offsets within this range: */
#define KVM_REG_ARM64_SVE_ZREG_BASE	0
#define KVM_REG_ARM64_SVE_PREG_BASE	0x400
#define KVM_REG_ARM64_SVE_FFR_BASE	0x600

#define KVM_ARM64_SVE_NUM_ZREGS		__SVE_NUM_ZREGS
#define KVM_ARM64_SVE_NUM_PREGS		__SVE_NUM_PREGS

#define KVM_ARM64_SVE_MAX_SLICES	32

#define KVM_REG_ARM64_SVE_ZREG(n, i)					\
	(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \
	 KVM_REG_SIZE_U2048 |						\
	 (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) |			\
	 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))

#define KVM_REG_ARM64_SVE_PREG(n, i)					\
	(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \
	 KVM_REG_SIZE_U256 |						\
	 (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) |			\
	 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))

#define KVM_REG_ARM64_SVE_FFR(i)					\
	(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \
	 KVM_REG_SIZE_U256 |						\
	 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))

/*
 * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and
 * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness-
 * invariant layout which differs from the layout used for the FPSIMD
 * V-registers on big-endian systems: see sigcontext.h for more explanation.
 */

#define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN
#define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX

/* Vector lengths pseudo-register: */
#define KVM_REG_ARM64_SVE_VLS		(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \
					 KVM_REG_SIZE_U512 | 0xffff)
#define KVM_ARM64_SVE_VLS_WORDS	\
	((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)

/* Device Control API: ARM VGIC */
#define KVM_DEV_ARM_VGIC_GRP_ADDR	0
#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS	1
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS	2
#define   KVM_DEV_ARM_VGIC_CPUID_SHIFT	32
#define   KVM_DEV_ARM_VGIC_CPUID_MASK	(0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
#define   KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
#define   KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
			(0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
#define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT	0
#define   KVM_DEV_ARM_VGIC_OFFSET_MASK	(0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
#define   KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS	3
#define KVM_DEV_ARM_VGIC_GRP_CTRL	4
#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO  7
#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT	10
#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
			(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK	0x3ff
#define VGIC_LEVEL_INFO_LINE_LEVEL	0

#define   KVM_DEV_ARM_VGIC_CTRL_INIT		0
#define   KVM_DEV_ARM_ITS_SAVE_TABLES           1
#define   KVM_DEV_ARM_ITS_RESTORE_TABLES        2
#define   KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES	3
#define   KVM_DEV_ARM_ITS_CTRL_RESET		4

/* Device Control API on vcpu fd */
#define KVM_ARM_VCPU_PMU_V3_CTRL	0
#define   KVM_ARM_VCPU_PMU_V3_IRQ	0
#define   KVM_ARM_VCPU_PMU_V3_INIT	1
#define KVM_ARM_VCPU_TIMER_CTRL		1
#define   KVM_ARM_VCPU_TIMER_IRQ_VTIMER		0
#define   KVM_ARM_VCPU_TIMER_IRQ_PTIMER		1
#define KVM_ARM_VCPU_PVTIME_CTRL	2
#define   KVM_ARM_VCPU_PVTIME_IPA	0

/* KVM_IRQ_LINE irq field index values */
#define KVM_ARM_IRQ_VCPU2_SHIFT		28
#define KVM_ARM_IRQ_VCPU2_MASK		0xf
#define KVM_ARM_IRQ_TYPE_SHIFT		24
#define KVM_ARM_IRQ_TYPE_MASK		0xf
#define KVM_ARM_IRQ_VCPU_SHIFT		16
#define KVM_ARM_IRQ_VCPU_MASK		0xff
#define KVM_ARM_IRQ_NUM_SHIFT		0
#define KVM_ARM_IRQ_NUM_MASK		0xffff

/* irq_type field */
#define KVM_ARM_IRQ_TYPE_CPU		0
#define KVM_ARM_IRQ_TYPE_SPI		1
#define KVM_ARM_IRQ_TYPE_PPI		2

/* out-of-kernel GIC cpu interrupt injection irq_number field */
#define KVM_ARM_IRQ_CPU_IRQ		0
#define KVM_ARM_IRQ_CPU_FIQ		1

/*
 * This used to hold the highest supported SPI, but it is now obsolete
 * and only here to provide source code level compatibility with older
 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
 */
#ifndef __KERNEL__
#define KVM_ARM_IRQ_GIC_MAX		127
#endif

/* One single KVM irqchip, ie. the VGIC */
#define KVM_NR_IRQCHIPS          1

/* PSCI interface */
#define KVM_PSCI_FN_BASE		0x95c1ba5e
#define KVM_PSCI_FN(n)			(KVM_PSCI_FN_BASE + (n))

#define KVM_PSCI_FN_CPU_SUSPEND		KVM_PSCI_FN(0)
#define KVM_PSCI_FN_CPU_OFF		KVM_PSCI_FN(1)
#define KVM_PSCI_FN_CPU_ON		KVM_PSCI_FN(2)
#define KVM_PSCI_FN_MIGRATE		KVM_PSCI_FN(3)

#define KVM_PSCI_RET_SUCCESS		PSCI_RET_SUCCESS
#define KVM_PSCI_RET_NI			PSCI_RET_NOT_SUPPORTED
#define KVM_PSCI_RET_INVAL		PSCI_RET_INVALID_PARAMS
#define KVM_PSCI_RET_DENIED		PSCI_RET_DENIED

#endif

#endif /* __ARM_KVM_H__ */
Commit	Line	Data
e2be04c7	1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
54f81d0e MZ	2	/*
	3	* Copyright (C) 2012,2013 - ARM Ltd
	4	* Author: Marc Zyngier <marc.zyngier@arm.com>
	5	*
	6	* Derived from arch/arm/include/uapi/asm/kvm.h:
	7	* Copyright (C) 2012 - Virtual Open Systems and Columbia University
	8	* Author: Christoffer Dall <c.dall@virtualopensystems.com>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	21	*/
	22
	23	#ifndef __ARM_KVM_H__
	24	#define __ARM_KVM_H__
	25
	26	#define KVM_SPSR_EL1 0
40033a61 MZ	27	#define KVM_SPSR_SVC KVM_SPSR_EL1
	28	#define KVM_SPSR_ABT 1
	29	#define KVM_SPSR_UND 2
	30	#define KVM_SPSR_IRQ 3
	31	#define KVM_SPSR_FIQ 4
	32	#define KVM_NR_SPSR 5
54f81d0e MZ	33
54f81d0e MZ	34	#ifndef __ASSEMBLY__
7d0f84aa	35	#include <linux/psci.h>
d1927915	36	#include <linux/types.h>
54f81d0e	37	#include <asm/ptrace.h>
8ae6efdd	38	#include <asm/sve_context.h>
54f81d0e MZ	39
	40	#define __KVM_HAVE_GUEST_DEBUG
	41	#define __KVM_HAVE_IRQ_LINE
98047888	42	#define __KVM_HAVE_READONLY_MEM
b7b27fac	43	#define __KVM_HAVE_VCPU_EVENTS
54f81d0e	44
4b4357e0 PB	45	#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
4b4357e0 PB	46
54f81d0e MZ	47	#define KVM_REG_SIZE(id) \
	48	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
	49
	50	struct kvm_regs {
	51	struct user_pt_regs regs; /* sp = sp_el0 */
	52
	53	__u64 sp_el1;
	54	__u64 elr_el1;
	55
	56	__u64 spsr[KVM_NR_SPSR];
	57
	58	struct user_fpsimd_state fp_regs;
	59	};
	60
bca556ac SP	61	/*
	62	* Supported CPU Targets - Adding a new target type is not recommended,
	63	* unless there are some special registers not supported by the
	64	* genericv8 syreg table.
	65	*/
54f81d0e MZ	66	#define KVM_ARM_TARGET_AEM_V8 0
	67	#define KVM_ARM_TARGET_FOUNDATION_V8 1
	68	#define KVM_ARM_TARGET_CORTEX_A57 2
e28100bd	69	#define KVM_ARM_TARGET_XGENE_POTENZA 3
1252b331	70	#define KVM_ARM_TARGET_CORTEX_A53 4
bca556ac SP	71	/* Generic ARM v8 target */
bca556ac SP	72	#define KVM_ARM_TARGET_GENERIC_V8 5
54f81d0e	73
bca556ac	74	#define KVM_ARM_NUM_TARGETS 6
54f81d0e MZ	75
	76	/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
	77	#define KVM_ARM_DEVICE_TYPE_SHIFT 0
	78	#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
	79	#define KVM_ARM_DEVICE_ID_SHIFT 16
	80	#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
	81
	82	/* Supported device IDs */
	83	#define KVM_ARM_DEVICE_VGIC_V2 0
	84
	85	/* Supported VGIC address types */
	86	#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
	87	#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
	88
	89	#define KVM_VGIC_V2_DIST_SIZE 0x1000
	90	#define KVM_VGIC_V2_CPU_SIZE 0x2000
	91
ac3d3735 AP	92	/* Supported VGICv3 address types */
	93	#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
	94	#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
1085fdc6	95	#define KVM_VGIC_ITS_ADDR_TYPE 4
6e407673	96	#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5
ac3d3735 AP	97
	98	#define KVM_VGIC_V3_DIST_SIZE SZ_64K
	99	#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
1085fdc6	100	#define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)
ac3d3735	101
dcd2e40c	102	#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
0d854a60	103	#define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */
7d0f84aa	104	#define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */
808e7381	105	#define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */
9033bba4	106	#define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */
a22fa321 ADK	107	#define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */
a22fa321 ADK	108	#define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */
dcd2e40c	109
54f81d0e MZ	110	struct kvm_vcpu_init {
	111	__u32 target;
	112	__u32 features[7];
	113	};
	114
	115	struct kvm_sregs {
	116	};
	117
	118	struct kvm_fpu {
	119	};
	120
21b6f32f AB	121	/*
	122	* See v8 ARM ARM D7.3: Debug Registers
	123	*
	124	* The architectural limit is 16 debug registers of each type although
	125	* in practice there are usually less (see ID_AA64DFR0_EL1).
	126	*
	127	* Although the control registers are architecturally defined as 32
	128	* bits wide we use a 64 bit structure here to keep parity with
	129	* KVM_GET/SET_ONE_REG behaviour which treats all system registers as
	130	* 64 bit values. It also allows for the possibility of the
	131	* architecture expanding the control registers without having to
	132	* change the userspace ABI.
	133	*/
	134	#define KVM_ARM_MAX_DBG_REGS 16
54f81d0e	135	struct kvm_guest_debug_arch {
21b6f32f AB	136	__u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];
	137	__u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];
	138	__u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];
	139	__u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
54f81d0e MZ	140	};
	141
	142	struct kvm_debug_exit_arch {
21b6f32f AB	143	__u32 hsr;
21b6f32f AB	144	__u64 far; /* used for watchpoints */
54f81d0e MZ	145	};
54f81d0e MZ	146
21b6f32f AB	147	/*
	148	* Architecture specific defines for kvm_guest_debug->control
	149	*/
	150
	151	#define KVM_GUESTDBG_USE_SW_BP (1 << 16)
	152	#define KVM_GUESTDBG_USE_HW (1 << 17)
	153
54f81d0e	154	struct kvm_sync_regs {
3fe17e68 AG	155	/* Used with KVM_CAP_ARM_USER_IRQ */
3fe17e68 AG	156	__u64 device_irq_level;
54f81d0e MZ	157	};
	158
	159	struct kvm_arch_memory_slot {
	160	};
	161
b7b27fac DG	162	/* for KVM_GET/SET_VCPU_EVENTS */
	163	struct kvm_vcpu_events {
	164	struct {
	165	__u8 serror_pending;
	166	__u8 serror_has_esr;
da345174	167	__u8 ext_dabt_pending;
b7b27fac	168	/* Align it to 8 bytes */
da345174	169	__u8 pad[5];
b7b27fac DG	170	__u64 serror_esr;
	171	} exception;
	172	__u32 reserved[12];
	173	};
	174
7c8c5e6a MZ	175	/* If you need to interpret the index values, here is the key: */
	176	#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
	177	#define KVM_REG_ARM_COPROC_SHIFT 16
	178
	179	/* Normal registers are mapped as coprocessor 16. */
	180	#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
	181	#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32))
	182
	183	/* Some registers need more space to represent values. */
	184	#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
	185	#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
	186	#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
	187	#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
	188	#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
	189	#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
	190
	191	/* AArch64 system registers */
	192	#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
	193	#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
	194	#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14
	195	#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
	196	#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11
	197	#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
	198	#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7
	199	#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
	200	#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3
	201	#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
	202	#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
	203
39735a3a AP	204	#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
	205	(((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
	206	KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
	207
	208	#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
	209	(KVM_REG_ARM64 \| KVM_REG_ARM64_SYSREG \| \
	210	ARM64_SYS_REG_SHIFT_MASK(op0, OP0) \| \
	211	ARM64_SYS_REG_SHIFT_MASK(op1, OP1) \| \
	212	ARM64_SYS_REG_SHIFT_MASK(crn, CRN) \| \
	213	ARM64_SYS_REG_SHIFT_MASK(crm, CRM) \| \
	214	ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
	215
	216	#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) \| KVM_REG_SIZE_U64)
	217
5c5196da CD	218	/* Physical Timer EL0 Registers */
	219	#define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1)
	220	#define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2)
	221	#define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1)
	222
	223	/* EL0 Virtual Timer Registers */
39735a3a AP	224	#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
	225	#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
	226	#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
	227
85bd0ba1 MZ	228	/* KVM-as-firmware specific pseudo-registers */
	229	#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
	230	#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 \| KVM_REG_SIZE_U64 \| \
	231	KVM_REG_ARM_FW \| ((r) & 0xffff))
	232	#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)
99adb567 AP	233	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1)
	234	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0
	235	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1
	236	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2
	237	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2)
	238	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0
	239	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1
	240	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2
	241	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3
	242	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4)
85bd0ba1	243
e1c9c983 DM	244	/* SVE registers */
	245	#define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT)
	246
	247	/* Z- and P-regs occupy blocks at the following offsets within this range: */
	248	#define KVM_REG_ARM64_SVE_ZREG_BASE 0
	249	#define KVM_REG_ARM64_SVE_PREG_BASE 0x400
8ae6efdd	250	#define KVM_REG_ARM64_SVE_FFR_BASE 0x600
e1c9c983	251
8ae6efdd DM	252	#define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS
	253	#define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS
	254
	255	#define KVM_ARM64_SVE_MAX_SLICES 32
	256
	257	#define KVM_REG_ARM64_SVE_ZREG(n, i) \
	258	(KVM_REG_ARM64 \| KVM_REG_ARM64_SVE \| KVM_REG_ARM64_SVE_ZREG_BASE \| \
	259	KVM_REG_SIZE_U2048 \| \
	260	(((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) \| \
	261	((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
	262
	263	#define KVM_REG_ARM64_SVE_PREG(n, i) \
	264	(KVM_REG_ARM64 \| KVM_REG_ARM64_SVE \| KVM_REG_ARM64_SVE_PREG_BASE \| \
	265	KVM_REG_SIZE_U256 \| \
	266	(((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) \| \
	267	((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
	268
	269	#define KVM_REG_ARM64_SVE_FFR(i) \
	270	(KVM_REG_ARM64 \| KVM_REG_ARM64_SVE \| KVM_REG_ARM64_SVE_FFR_BASE \| \
	271	KVM_REG_SIZE_U256 \| \
	272	((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
e1c9c983	273
41040cf7 DM	274	/*
	275	* Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and
	276	* KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness-
	277	* invariant layout which differs from the layout used for the FPSIMD
	278	* V-registers on big-endian systems: see sigcontext.h for more explanation.
	279	*/
	280
4bd774e5 DM	281	#define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN
	282	#define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX
	283
9033bba4 DM	284	/* Vector lengths pseudo-register: */
	285	#define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 \| KVM_REG_ARM64_SVE \| \
	286	KVM_REG_SIZE_U512 \| 0xffff)
4bd774e5 DM	287	#define KVM_ARM64_SVE_VLS_WORDS \
4bd774e5 DM	288	((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)
9033bba4	289
2a2f3e26 CD	290	/* Device Control API: ARM VGIC */
	291	#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
	292	#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
	293	#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
	294	#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
	295	#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
94574c94 VK	296	#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
	297	#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
	298	(0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
2a2f3e26 CD	299	#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
2a2f3e26 CD	300	#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
d017d7b0	301	#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
a98f26f1	302	#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
065c0034	303	#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
94574c94	304	#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
d017d7b0	305	#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
e96a006c	306	#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
876ae234	307	#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
e96a006c VK	308	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
	309	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
	310	(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
	311	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
	312	#define VGIC_LEVEL_INFO_LINE_LEVEL 0
d017d7b0	313
3b65808f EA	314	#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
	315	#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
	316	#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
28077125	317	#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
3eb4271b	318	#define KVM_DEV_ARM_ITS_CTRL_RESET 4
2a2f3e26	319
bb0c70bc SZ	320	/* Device Control API on vcpu fd */
	321	#define KVM_ARM_VCPU_PMU_V3_CTRL 0
	322	#define KVM_ARM_VCPU_PMU_V3_IRQ 0
	323	#define KVM_ARM_VCPU_PMU_V3_INIT 1
99a1db7a CD	324	#define KVM_ARM_VCPU_TIMER_CTRL 1
	325	#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0
	326	#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1
58772e9a SP	327	#define KVM_ARM_VCPU_PVTIME_CTRL 2
58772e9a SP	328	#define KVM_ARM_VCPU_PVTIME_IPA 0
bb0c70bc	329
54f81d0e	330	/* KVM_IRQ_LINE irq field index values */
92f35b75 MZ	331	#define KVM_ARM_IRQ_VCPU2_SHIFT 28
92f35b75 MZ	332	#define KVM_ARM_IRQ_VCPU2_MASK 0xf
54f81d0e	333	#define KVM_ARM_IRQ_TYPE_SHIFT 24
92f35b75	334	#define KVM_ARM_IRQ_TYPE_MASK 0xf
54f81d0e MZ	335	#define KVM_ARM_IRQ_VCPU_SHIFT 16
	336	#define KVM_ARM_IRQ_VCPU_MASK 0xff
	337	#define KVM_ARM_IRQ_NUM_SHIFT 0
	338	#define KVM_ARM_IRQ_NUM_MASK 0xffff
	339
	340	/* irq_type field */
	341	#define KVM_ARM_IRQ_TYPE_CPU 0
	342	#define KVM_ARM_IRQ_TYPE_SPI 1
	343	#define KVM_ARM_IRQ_TYPE_PPI 2
	344
	345	/* out-of-kernel GIC cpu interrupt injection irq_number field */
	346	#define KVM_ARM_IRQ_CPU_IRQ 0
	347	#define KVM_ARM_IRQ_CPU_FIQ 1
	348
fd1d0ddf AP	349	/*
	350	* This used to hold the highest supported SPI, but it is now obsolete
	351	* and only here to provide source code level compatibility with older
	352	* userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
	353	*/
	354	#ifndef __KERNEL__
54f81d0e	355	#define KVM_ARM_IRQ_GIC_MAX 127
fd1d0ddf	356	#endif
54f81d0e	357
174178fe EA	358	/* One single KVM irqchip, ie. the VGIC */
	359	#define KVM_NR_IRQCHIPS 1
	360
dcd2e40c MZ	361	/* PSCI interface */
	362	#define KVM_PSCI_FN_BASE 0x95c1ba5e
	363	#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
	364
	365	#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
	366	#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
	367	#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
	368	#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
	369
7d0f84aa AP	370	#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
	371	#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
	372	#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
	373	#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
dcd2e40c	374
54f81d0e MZ	375	#endif
	376
	377	#endif /* __ARM_KVM_H__ */