[thirdparty/linux.git] / arch / arm64 / kernel / alternative.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * alternative runtime patching
 * inspired by the x86 version
 *
 * Copyright (C) 2014 ARM Ltd.
 */

#define pr_fmt(fmt) "alternatives: " fmt

#include <linux/init.h>
#include <linux/cpu.h>
#include <asm/cacheflush.h>
#include <asm/alternative.h>
#include <asm/cpufeature.h>
#include <asm/insn.h>
#include <asm/sections.h>
#include <linux/stop_machine.h>

#define __ALT_PTR(a,f)		((void *)&(a)->f + (a)->f)
#define ALT_ORIG_PTR(a)		__ALT_PTR(a, orig_offset)
#define ALT_REPL_PTR(a)		__ALT_PTR(a, alt_offset)

static int all_alternatives_applied;

static DECLARE_BITMAP(applied_alternatives, ARM64_NCAPS);

struct alt_region {
	struct alt_instr *begin;
	struct alt_instr *end;
};

bool alternative_is_applied(u16 cpufeature)
{
	if (WARN_ON(cpufeature >= ARM64_NCAPS))
		return false;

	return test_bit(cpufeature, applied_alternatives);
}

/*
 * Check if the target PC is within an alternative block.
 */
static bool branch_insn_requires_update(struct alt_instr *alt, unsigned long pc)
{
	unsigned long replptr;

	if (kernel_text_address(pc))
		return true;

	replptr = (unsigned long)ALT_REPL_PTR(alt);
	if (pc >= replptr && pc <= (replptr + alt->alt_len))
		return false;

	/*
	 * Branching into *another* alternate sequence is doomed, and
	 * we're not even trying to fix it up.
	 */
	BUG();
}

#define align_down(x, a)	((unsigned long)(x) & ~(((unsigned long)(a)) - 1))

static u32 get_alt_insn(struct alt_instr *alt, __le32 *insnptr, __le32 *altinsnptr)
{
	u32 insn;

	insn = le32_to_cpu(*altinsnptr);

	if (aarch64_insn_is_branch_imm(insn)) {
		s32 offset = aarch64_get_branch_offset(insn);
		unsigned long target;

		target = (unsigned long)altinsnptr + offset;

		/*
		 * If we're branching inside the alternate sequence,
		 * do not rewrite the instruction, as it is already
		 * correct. Otherwise, generate the new instruction.
		 */
		if (branch_insn_requires_update(alt, target)) {
			offset = target - (unsigned long)insnptr;
			insn = aarch64_set_branch_offset(insn, offset);
		}
	} else if (aarch64_insn_is_adrp(insn)) {
		s32 orig_offset, new_offset;
		unsigned long target;

		/*
		 * If we're replacing an adrp instruction, which uses PC-relative
		 * immediate addressing, adjust the offset to reflect the new
		 * PC. adrp operates on 4K aligned addresses.
		 */
		orig_offset  = aarch64_insn_adrp_get_offset(insn);
		target = align_down(altinsnptr, SZ_4K) + orig_offset;
		new_offset = target - align_down(insnptr, SZ_4K);
		insn = aarch64_insn_adrp_set_offset(insn, new_offset);
	} else if (aarch64_insn_uses_literal(insn)) {
		/*
		 * Disallow patching unhandled instructions using PC relative
		 * literal addresses
		 */
		BUG();
	}

	return insn;
}

static void patch_alternative(struct alt_instr *alt,
			      __le32 *origptr, __le32 *updptr, int nr_inst)
{
	__le32 *replptr;
	int i;

	replptr = ALT_REPL_PTR(alt);
	for (i = 0; i < nr_inst; i++) {
		u32 insn;

		insn = get_alt_insn(alt, origptr + i, replptr + i);
		updptr[i] = cpu_to_le32(insn);
	}
}

/*
 * We provide our own, private D-cache cleaning function so that we don't
 * accidentally call into the cache.S code, which is patched by us at
 * runtime.
 */
static void clean_dcache_range_nopatch(u64 start, u64 end)
{
	u64 cur, d_size, ctr_el0;

	ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
	d_size = 4 << cpuid_feature_extract_unsigned_field(ctr_el0,
							   CTR_DMINLINE_SHIFT);
	cur = start & ~(d_size - 1);
	do {
		/*
		 * We must clean+invalidate to the PoC in order to avoid
		 * Cortex-A53 errata 826319, 827319, 824069 and 819472
		 * (this corresponds to ARM64_WORKAROUND_CLEAN_CACHE)
		 */
		asm volatile("dc civac, %0" : : "r" (cur) : "memory");
	} while (cur += d_size, cur < end);
}

static void __apply_alternatives(void *alt_region,  bool is_module,
				 unsigned long *feature_mask)
{
	struct alt_instr *alt;
	struct alt_region *region = alt_region;
	__le32 *origptr, *updptr;
	alternative_cb_t alt_cb;

	for (alt = region->begin; alt < region->end; alt++) {
		int nr_inst;

		if (!test_bit(alt->cpufeature, feature_mask))
			continue;

		/* Use ARM64_CB_PATCH as an unconditional patch */
		if (alt->cpufeature < ARM64_CB_PATCH &&
		    !cpus_have_cap(alt->cpufeature))
			continue;

		if (alt->cpufeature == ARM64_CB_PATCH)
			BUG_ON(alt->alt_len != 0);
		else
			BUG_ON(alt->alt_len != alt->orig_len);

		pr_info_once("patching kernel code\n");

		origptr = ALT_ORIG_PTR(alt);
		updptr = is_module ? origptr : lm_alias(origptr);
		nr_inst = alt->orig_len / AARCH64_INSN_SIZE;

		if (alt->cpufeature < ARM64_CB_PATCH)
			alt_cb = patch_alternative;
		else
			alt_cb  = ALT_REPL_PTR(alt);

		alt_cb(alt, origptr, updptr, nr_inst);

		if (!is_module) {
			clean_dcache_range_nopatch((u64)origptr,
						   (u64)(origptr + nr_inst));
		}
	}

	/*
	 * The core module code takes care of cache maintenance in
	 * flush_module_icache().
	 */
	if (!is_module) {
		dsb(ish);
		__flush_icache_all();
		isb();

		/* Ignore ARM64_CB bit from feature mask */
		bitmap_or(applied_alternatives, applied_alternatives,
			  feature_mask, ARM64_NCAPS);
		bitmap_and(applied_alternatives, applied_alternatives,
			   cpu_hwcaps, ARM64_NCAPS);
	}
}

/*
 * We might be patching the stop_machine state machine, so implement a
 * really simple polling protocol here.
 */
static int __apply_alternatives_multi_stop(void *unused)
{
	struct alt_region region = {
		.begin	= (struct alt_instr *)__alt_instructions,
		.end	= (struct alt_instr *)__alt_instructions_end,
	};

	/* We always have a CPU 0 at this point (__init) */
	if (smp_processor_id()) {
		while (!READ_ONCE(all_alternatives_applied))
			cpu_relax();
		isb();
	} else {
		DECLARE_BITMAP(remaining_capabilities, ARM64_NPATCHABLE);

		bitmap_complement(remaining_capabilities, boot_capabilities,
				  ARM64_NPATCHABLE);

		BUG_ON(all_alternatives_applied);
		__apply_alternatives(&region, false, remaining_capabilities);
		/* Barriers provided by the cache flushing */
		WRITE_ONCE(all_alternatives_applied, 1);
	}

	return 0;
}

void __init apply_alternatives_all(void)
{
	/* better not try code patching on a live SMP system */
	stop_machine(__apply_alternatives_multi_stop, NULL, cpu_online_mask);
}

/*
 * This is called very early in the boot process (directly after we run
 * a feature detect on the boot CPU). No need to worry about other CPUs
 * here.
 */
void __init apply_boot_alternatives(void)
{
	struct alt_region region = {
		.begin	= (struct alt_instr *)__alt_instructions,
		.end	= (struct alt_instr *)__alt_instructions_end,
	};

	/* If called on non-boot cpu things could go wrong */
	WARN_ON(smp_processor_id() != 0);

	__apply_alternatives(&region, false, &boot_capabilities[0]);
}

#ifdef CONFIG_MODULES
void apply_alternatives_module(void *start, size_t length)
{
	struct alt_region region = {
		.begin	= start,
		.end	= start + length,
	};
	DECLARE_BITMAP(all_capabilities, ARM64_NPATCHABLE);

	bitmap_fill(all_capabilities, ARM64_NPATCHABLE);

	__apply_alternatives(&region, true, &all_capabilities[0]);
}
#endif
Commit	Line	Data
caab277b	1	// SPDX-License-Identifier: GPL-2.0-only
e039ee4e AP	2	/*
	3	* alternative runtime patching
	4	* inspired by the x86 version
	5	*
	6	* Copyright (C) 2014 ARM Ltd.
e039ee4e AP	7	*/
	8
	9	#define pr_fmt(fmt) "alternatives: " fmt
	10
	11	#include <linux/init.h>
	12	#include <linux/cpu.h>
	13	#include <asm/cacheflush.h>
	14	#include <asm/alternative.h>
	15	#include <asm/cpufeature.h>
7616fc8b	16	#include <asm/insn.h>
ee78fdc7	17	#include <asm/sections.h>
e039ee4e AP	18	#include <linux/stop_machine.h>
e039ee4e AP	19
15ad6ace	20	#define __ALT_PTR(a,f) ((void *)&(a)->f + (a)->f)
7616fc8b MZ	21	#define ALT_ORIG_PTR(a) __ALT_PTR(a, orig_offset)
	22	#define ALT_REPL_PTR(a) __ALT_PTR(a, alt_offset)
	23
e9ab7a2e JT	24	static int all_alternatives_applied;
	25
	26	static DECLARE_BITMAP(applied_alternatives, ARM64_NCAPS);
6d99b689	27
932ded4b AP	28	struct alt_region {
	29	struct alt_instr *begin;
	30	struct alt_instr *end;
	31	};
	32
e9ab7a2e JT	33	bool alternative_is_applied(u16 cpufeature)
	34	{
	35	if (WARN_ON(cpufeature >= ARM64_NCAPS))
	36	return false;
	37
	38	return test_bit(cpufeature, applied_alternatives);
	39	}
	40
7616fc8b MZ	41	/*
	42	* Check if the target PC is within an alternative block.
	43	*/
	44	static bool branch_insn_requires_update(struct alt_instr *alt, unsigned long pc)
	45	{
	46	unsigned long replptr;
	47
	48	if (kernel_text_address(pc))
3c4d9137	49	return true;
7616fc8b MZ	50
	51	replptr = (unsigned long)ALT_REPL_PTR(alt);
	52	if (pc >= replptr && pc <= (replptr + alt->alt_len))
3c4d9137	53	return false;
7616fc8b MZ	54
	55	/*
	56	* Branching into another alternate sequence is doomed, and
	57	* we're not even trying to fix it up.
	58	*/
	59	BUG();
	60	}
	61
c831b2ae SP	62	#define align_down(x, a) ((unsigned long)(x) & ~(((unsigned long)(a)) - 1))
c831b2ae SP	63
15ad6ace	64	static u32 get_alt_insn(struct alt_instr alt, __le32 insnptr, __le32 *altinsnptr)
7616fc8b MZ	65	{
	66	u32 insn;
	67
	68	insn = le32_to_cpu(*altinsnptr);
	69
	70	if (aarch64_insn_is_branch_imm(insn)) {
	71	s32 offset = aarch64_get_branch_offset(insn);
	72	unsigned long target;
	73
	74	target = (unsigned long)altinsnptr + offset;
	75
	76	/*
	77	* If we're branching inside the alternate sequence,
	78	* do not rewrite the instruction, as it is already
	79	* correct. Otherwise, generate the new instruction.
	80	*/
	81	if (branch_insn_requires_update(alt, target)) {
	82	offset = target - (unsigned long)insnptr;
	83	insn = aarch64_set_branch_offset(insn, offset);
	84	}
c831b2ae SP	85	} else if (aarch64_insn_is_adrp(insn)) {
	86	s32 orig_offset, new_offset;
	87	unsigned long target;
	88
	89	/*
	90	* If we're replacing an adrp instruction, which uses PC-relative
	91	* immediate addressing, adjust the offset to reflect the new
	92	* PC. adrp operates on 4K aligned addresses.
	93	*/
	94	orig_offset = aarch64_insn_adrp_get_offset(insn);
	95	target = align_down(altinsnptr, SZ_4K) + orig_offset;
	96	new_offset = target - align_down(insnptr, SZ_4K);
	97	insn = aarch64_insn_adrp_set_offset(insn, new_offset);
baa763b5 SP	98	} else if (aarch64_insn_uses_literal(insn)) {
	99	/*
	100	* Disallow patching unhandled instructions using PC relative
	101	* literal addresses
	102	*/
	103	BUG();
7616fc8b MZ	104	}
	105
	106	return insn;
	107	}
	108
dea5e2a4 MZ	109	static void patch_alternative(struct alt_instr *alt,
	110	__le32 origptr, __le32 updptr, int nr_inst)
	111	{
	112	__le32 *replptr;
	113	int i;
	114
	115	replptr = ALT_REPL_PTR(alt);
	116	for (i = 0; i < nr_inst; i++) {
	117	u32 insn;
	118
	119	insn = get_alt_insn(alt, origptr + i, replptr + i);
	120	updptr[i] = cpu_to_le32(insn);
	121	}
	122	}
	123
42938868 WD	124	/*
	125	* We provide our own, private D-cache cleaning function so that we don't
	126	* accidentally call into the cache.S code, which is patched by us at
	127	* runtime.
	128	*/
	129	static void clean_dcache_range_nopatch(u64 start, u64 end)
	130	{
	131	u64 cur, d_size, ctr_el0;
	132
	133	ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
	134	d_size = 4 << cpuid_feature_extract_unsigned_field(ctr_el0,
	135	CTR_DMINLINE_SHIFT);
	136	cur = start & ~(d_size - 1);
	137	do {
	138	/*
	139	* We must clean+invalidate to the PoC in order to avoid
	140	* Cortex-A53 errata 826319, 827319, 824069 and 819472
	141	* (this corresponds to ARM64_WORKAROUND_CLEAN_CACHE)
	142	*/
	143	asm volatile("dc civac, %0" : : "r" (cur) : "memory");
	144	} while (cur += d_size, cur < end);
	145	}
	146
0ceb0d56 DT	147	static void __apply_alternatives(void *alt_region, bool is_module,
0ceb0d56 DT	148	unsigned long *feature_mask)
e039ee4e AP	149	{
e039ee4e AP	150	struct alt_instr *alt;
932ded4b	151	struct alt_region *region = alt_region;
dea5e2a4 MZ	152	__le32 origptr, updptr;
dea5e2a4 MZ	153	alternative_cb_t alt_cb;
e039ee4e	154
932ded4b	155	for (alt = region->begin; alt < region->end; alt++) {
dea5e2a4	156	int nr_inst;
7616fc8b	157
0ceb0d56 DT	158	if (!test_bit(alt->cpufeature, feature_mask))
	159	continue;
	160
dea5e2a4 MZ	161	/* Use ARM64_CB_PATCH as an unconditional patch */
	162	if (alt->cpufeature < ARM64_CB_PATCH &&
	163	!cpus_have_cap(alt->cpufeature))
e039ee4e AP	164	continue;
e039ee4e AP	165
dea5e2a4 MZ	166	if (alt->cpufeature == ARM64_CB_PATCH)
	167	BUG_ON(alt->alt_len != 0);
	168	else
	169	BUG_ON(alt->alt_len != alt->orig_len);
e039ee4e AP	170
	171	pr_info_once("patching kernel code\n");
	172
7616fc8b	173	origptr = ALT_ORIG_PTR(alt);
42938868	174	updptr = is_module ? origptr : lm_alias(origptr);
dea5e2a4	175	nr_inst = alt->orig_len / AARCH64_INSN_SIZE;
7616fc8b	176
dea5e2a4 MZ	177	if (alt->cpufeature < ARM64_CB_PATCH)
	178	alt_cb = patch_alternative;
	179	else
	180	alt_cb = ALT_REPL_PTR(alt);
	181
	182	alt_cb(alt, origptr, updptr, nr_inst);
7616fc8b	183
42938868 WD	184	if (!is_module) {
	185	clean_dcache_range_nopatch((u64)origptr,
	186	(u64)(origptr + nr_inst));
	187	}
	188	}
	189
	190	/*
	191	* The core module code takes care of cache maintenance in
	192	* flush_module_icache().
	193	*/
	194	if (!is_module) {
	195	dsb(ish);
	196	__flush_icache_all();
	197	isb();
e9ab7a2e	198
0ceb0d56 DT	199	/* Ignore ARM64_CB bit from feature mask */
	200	bitmap_or(applied_alternatives, applied_alternatives,
	201	feature_mask, ARM64_NCAPS);
	202	bitmap_and(applied_alternatives, applied_alternatives,
	203	cpu_hwcaps, ARM64_NCAPS);
e039ee4e	204	}
e039ee4e AP	205	}
e039ee4e AP	206
ef5e724b WD	207	/*
	208	* We might be patching the stop_machine state machine, so implement a
	209	* really simple polling protocol here.
	210	*/
	211	static int __apply_alternatives_multi_stop(void *unused)
e039ee4e	212	{
932ded4b	213	struct alt_region region = {
ee78fdc7 JM	214	.begin = (struct alt_instr *)__alt_instructions,
ee78fdc7 JM	215	.end = (struct alt_instr *)__alt_instructions_end,
932ded4b AP	216	};
932ded4b AP	217
ef5e724b WD	218	/* We always have a CPU 0 at this point (__init) */
ef5e724b WD	219	if (smp_processor_id()) {
e9ab7a2e	220	while (!READ_ONCE(all_alternatives_applied))
ef5e724b	221	cpu_relax();
04b8637b	222	isb();
ef5e724b	223	} else {
0ceb0d56 DT	224	DECLARE_BITMAP(remaining_capabilities, ARM64_NPATCHABLE);
	225
	226	bitmap_complement(remaining_capabilities, boot_capabilities,
	227	ARM64_NPATCHABLE);
	228
e9ab7a2e	229	BUG_ON(all_alternatives_applied);
0ceb0d56	230	__apply_alternatives(&region, false, remaining_capabilities);
ef5e724b	231	/* Barriers provided by the cache flushing */
e9ab7a2e	232	WRITE_ONCE(all_alternatives_applied, 1);
ef5e724b WD	233	}
	234
	235	return 0;
	236	}
	237
	238	void __init apply_alternatives_all(void)
	239	{
e039ee4e	240	/* better not try code patching on a live SMP system */
ef5e724b	241	stop_machine(__apply_alternatives_multi_stop, NULL, cpu_online_mask);
932ded4b AP	242	}
932ded4b AP	243
0ceb0d56 DT	244	/*
	245	* This is called very early in the boot process (directly after we run
	246	* a feature detect on the boot CPU). No need to worry about other CPUs
	247	* here.
	248	*/
	249	void __init apply_boot_alternatives(void)
	250	{
	251	struct alt_region region = {
	252	.begin = (struct alt_instr *)__alt_instructions,
	253	.end = (struct alt_instr *)__alt_instructions_end,
	254	};
	255
	256	/* If called on non-boot cpu things could go wrong */
	257	WARN_ON(smp_processor_id() != 0);
	258
	259	__apply_alternatives(&region, false, &boot_capabilities[0]);
	260	}
	261
42938868 WD	262	#ifdef CONFIG_MODULES
42938868 WD	263	void apply_alternatives_module(void *start, size_t length)
932ded4b AP	264	{
	265	struct alt_region region = {
	266	.begin = start,
	267	.end = start + length,
	268	};
0ceb0d56 DT	269	DECLARE_BITMAP(all_capabilities, ARM64_NPATCHABLE);
	270
	271	bitmap_fill(all_capabilities, ARM64_NPATCHABLE);
932ded4b	272
0ceb0d56	273	__apply_alternatives(&region, true, &all_capabilities[0]);
e039ee4e	274	}
42938868	275	#endif