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60ffc30d CM |
1 | /* |
2 | * Low-level exception handling code | |
3 | * | |
4 | * Copyright (C) 2012 ARM Ltd. | |
5 | * Authors: Catalin Marinas <catalin.marinas@arm.com> | |
6 | * Will Deacon <will.deacon@arm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/linkage.h> | |
23 | ||
8d883b23 | 24 | #include <asm/alternative.h> |
60ffc30d CM |
25 | #include <asm/assembler.h> |
26 | #include <asm/asm-offsets.h> | |
905e8c5d | 27 | #include <asm/cpufeature.h> |
60ffc30d | 28 | #include <asm/errno.h> |
5c1ce6f7 | 29 | #include <asm/esr.h> |
8e23dacd | 30 | #include <asm/irq.h> |
eef94a3d | 31 | #include <asm/processor.h> |
39bc88e5 | 32 | #include <asm/ptrace.h> |
60ffc30d | 33 | #include <asm/thread_info.h> |
b4b8664d | 34 | #include <asm/asm-uaccess.h> |
60ffc30d CM |
35 | #include <asm/unistd.h> |
36 | ||
6c81fe79 LB |
37 | /* |
38 | * Context tracking subsystem. Used to instrument transitions | |
39 | * between user and kernel mode. | |
40 | */ | |
41 | .macro ct_user_exit, syscall = 0 | |
42 | #ifdef CONFIG_CONTEXT_TRACKING | |
43 | bl context_tracking_user_exit | |
44 | .if \syscall == 1 | |
45 | /* | |
46 | * Save/restore needed during syscalls. Restore syscall arguments from | |
47 | * the values already saved on stack during kernel_entry. | |
48 | */ | |
49 | ldp x0, x1, [sp] | |
50 | ldp x2, x3, [sp, #S_X2] | |
51 | ldp x4, x5, [sp, #S_X4] | |
52 | ldp x6, x7, [sp, #S_X6] | |
53 | .endif | |
54 | #endif | |
55 | .endm | |
56 | ||
57 | .macro ct_user_enter | |
58 | #ifdef CONFIG_CONTEXT_TRACKING | |
59 | bl context_tracking_user_enter | |
60 | #endif | |
61 | .endm | |
62 | ||
60ffc30d CM |
63 | /* |
64 | * Bad Abort numbers | |
65 | *----------------- | |
66 | */ | |
67 | #define BAD_SYNC 0 | |
68 | #define BAD_IRQ 1 | |
69 | #define BAD_FIQ 2 | |
70 | #define BAD_ERROR 3 | |
71 | ||
b11e5759 MR |
72 | .macro kernel_ventry label |
73 | .align 7 | |
63648dd2 | 74 | sub sp, sp, #S_FRAME_SIZE |
872d8327 MR |
75 | #ifdef CONFIG_VMAP_STACK |
76 | /* | |
77 | * Test whether the SP has overflowed, without corrupting a GPR. | |
78 | * Task and IRQ stacks are aligned to (1 << THREAD_SHIFT). | |
79 | */ | |
80 | add sp, sp, x0 // sp' = sp + x0 | |
81 | sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp | |
82 | tbnz x0, #THREAD_SHIFT, 0f | |
83 | sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 | |
84 | sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp | |
85 | b \label | |
86 | ||
87 | 0: | |
88 | /* | |
89 | * Either we've just detected an overflow, or we've taken an exception | |
90 | * while on the overflow stack. Either way, we won't return to | |
91 | * userspace, and can clobber EL0 registers to free up GPRs. | |
92 | */ | |
93 | ||
94 | /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */ | |
95 | msr tpidr_el0, x0 | |
96 | ||
97 | /* Recover the original x0 value and stash it in tpidrro_el0 */ | |
98 | sub x0, sp, x0 | |
99 | msr tpidrro_el0, x0 | |
100 | ||
101 | /* Switch to the overflow stack */ | |
102 | adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 | |
103 | ||
104 | /* | |
105 | * Check whether we were already on the overflow stack. This may happen | |
106 | * after panic() re-enables interrupts. | |
107 | */ | |
108 | mrs x0, tpidr_el0 // sp of interrupted context | |
109 | sub x0, sp, x0 // delta with top of overflow stack | |
110 | tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? | |
111 | b.ne __bad_stack // no? -> bad stack pointer | |
112 | ||
113 | /* We were already on the overflow stack. Restore sp/x0 and carry on. */ | |
114 | sub sp, sp, x0 | |
115 | mrs x0, tpidrro_el0 | |
116 | #endif | |
b11e5759 MR |
117 | b \label |
118 | .endm | |
119 | ||
120 | .macro kernel_entry, el, regsize = 64 | |
60ffc30d CM |
121 | .if \regsize == 32 |
122 | mov w0, w0 // zero upper 32 bits of x0 | |
123 | .endif | |
63648dd2 WD |
124 | stp x0, x1, [sp, #16 * 0] |
125 | stp x2, x3, [sp, #16 * 1] | |
126 | stp x4, x5, [sp, #16 * 2] | |
127 | stp x6, x7, [sp, #16 * 3] | |
128 | stp x8, x9, [sp, #16 * 4] | |
129 | stp x10, x11, [sp, #16 * 5] | |
130 | stp x12, x13, [sp, #16 * 6] | |
131 | stp x14, x15, [sp, #16 * 7] | |
132 | stp x16, x17, [sp, #16 * 8] | |
133 | stp x18, x19, [sp, #16 * 9] | |
134 | stp x20, x21, [sp, #16 * 10] | |
135 | stp x22, x23, [sp, #16 * 11] | |
136 | stp x24, x25, [sp, #16 * 12] | |
137 | stp x26, x27, [sp, #16 * 13] | |
138 | stp x28, x29, [sp, #16 * 14] | |
139 | ||
60ffc30d CM |
140 | .if \el == 0 |
141 | mrs x21, sp_el0 | |
c02433dd MR |
142 | ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear, |
143 | ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug | |
2a283070 | 144 | disable_step_tsk x19, x20 // exceptions when scheduling. |
49003a8d JM |
145 | |
146 | mov x29, xzr // fp pointed to user-space | |
60ffc30d CM |
147 | .else |
148 | add x21, sp, #S_FRAME_SIZE | |
e19a6ee2 JM |
149 | get_thread_info tsk |
150 | /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */ | |
c02433dd | 151 | ldr x20, [tsk, #TSK_TI_ADDR_LIMIT] |
e19a6ee2 JM |
152 | str x20, [sp, #S_ORIG_ADDR_LIMIT] |
153 | mov x20, #TASK_SIZE_64 | |
c02433dd | 154 | str x20, [tsk, #TSK_TI_ADDR_LIMIT] |
563cada0 | 155 | /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */ |
e19a6ee2 | 156 | .endif /* \el == 0 */ |
60ffc30d CM |
157 | mrs x22, elr_el1 |
158 | mrs x23, spsr_el1 | |
159 | stp lr, x21, [sp, #S_LR] | |
39bc88e5 | 160 | |
73267498 AB |
161 | /* |
162 | * In order to be able to dump the contents of struct pt_regs at the | |
163 | * time the exception was taken (in case we attempt to walk the call | |
164 | * stack later), chain it together with the stack frames. | |
165 | */ | |
166 | .if \el == 0 | |
167 | stp xzr, xzr, [sp, #S_STACKFRAME] | |
168 | .else | |
169 | stp x29, x22, [sp, #S_STACKFRAME] | |
170 | .endif | |
171 | add x29, sp, #S_STACKFRAME | |
172 | ||
39bc88e5 CM |
173 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
174 | /* | |
175 | * Set the TTBR0 PAN bit in SPSR. When the exception is taken from | |
176 | * EL0, there is no need to check the state of TTBR0_EL1 since | |
177 | * accesses are always enabled. | |
178 | * Note that the meaning of this bit differs from the ARMv8.1 PAN | |
179 | * feature as all TTBR0_EL1 accesses are disabled, not just those to | |
180 | * user mappings. | |
181 | */ | |
182 | alternative_if ARM64_HAS_PAN | |
183 | b 1f // skip TTBR0 PAN | |
184 | alternative_else_nop_endif | |
185 | ||
186 | .if \el != 0 | |
187 | mrs x21, ttbr0_el1 | |
188 | tst x21, #0xffff << 48 // Check for the reserved ASID | |
189 | orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR | |
190 | b.eq 1f // TTBR0 access already disabled | |
191 | and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR | |
192 | .endif | |
193 | ||
194 | __uaccess_ttbr0_disable x21 | |
195 | 1: | |
196 | #endif | |
197 | ||
60ffc30d CM |
198 | stp x22, x23, [sp, #S_PC] |
199 | ||
17c28958 | 200 | /* Not in a syscall by default (el0_svc overwrites for real syscall) */ |
60ffc30d | 201 | .if \el == 0 |
17c28958 | 202 | mov w21, #NO_SYSCALL |
35d0e6fb | 203 | str w21, [sp, #S_SYSCALLNO] |
60ffc30d CM |
204 | .endif |
205 | ||
6cdf9c7c JL |
206 | /* |
207 | * Set sp_el0 to current thread_info. | |
208 | */ | |
209 | .if \el == 0 | |
210 | msr sp_el0, tsk | |
211 | .endif | |
212 | ||
60ffc30d CM |
213 | /* |
214 | * Registers that may be useful after this macro is invoked: | |
215 | * | |
216 | * x21 - aborted SP | |
217 | * x22 - aborted PC | |
218 | * x23 - aborted PSTATE | |
219 | */ | |
220 | .endm | |
221 | ||
412fcb6c | 222 | .macro kernel_exit, el |
e19a6ee2 | 223 | .if \el != 0 |
8d66772e JM |
224 | disable_daif |
225 | ||
e19a6ee2 JM |
226 | /* Restore the task's original addr_limit. */ |
227 | ldr x20, [sp, #S_ORIG_ADDR_LIMIT] | |
c02433dd | 228 | str x20, [tsk, #TSK_TI_ADDR_LIMIT] |
e19a6ee2 JM |
229 | |
230 | /* No need to restore UAO, it will be restored from SPSR_EL1 */ | |
231 | .endif | |
232 | ||
60ffc30d CM |
233 | ldp x21, x22, [sp, #S_PC] // load ELR, SPSR |
234 | .if \el == 0 | |
6c81fe79 | 235 | ct_user_enter |
39bc88e5 CM |
236 | .endif |
237 | ||
238 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN | |
239 | /* | |
240 | * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR | |
241 | * PAN bit checking. | |
242 | */ | |
243 | alternative_if ARM64_HAS_PAN | |
244 | b 2f // skip TTBR0 PAN | |
245 | alternative_else_nop_endif | |
246 | ||
247 | .if \el != 0 | |
248 | tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set | |
249 | .endif | |
250 | ||
251 | __uaccess_ttbr0_enable x0 | |
252 | ||
253 | .if \el == 0 | |
254 | /* | |
255 | * Enable errata workarounds only if returning to user. The only | |
256 | * workaround currently required for TTBR0_EL1 changes are for the | |
257 | * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache | |
258 | * corruption). | |
259 | */ | |
260 | post_ttbr0_update_workaround | |
261 | .endif | |
262 | 1: | |
263 | .if \el != 0 | |
264 | and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit | |
265 | .endif | |
266 | 2: | |
267 | #endif | |
268 | ||
269 | .if \el == 0 | |
60ffc30d | 270 | ldr x23, [sp, #S_SP] // load return stack pointer |
63648dd2 | 271 | msr sp_el0, x23 |
905e8c5d | 272 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
6ba3b554 | 273 | alternative_if ARM64_WORKAROUND_845719 |
e28cabf1 DT |
274 | tbz x22, #4, 1f |
275 | #ifdef CONFIG_PID_IN_CONTEXTIDR | |
276 | mrs x29, contextidr_el1 | |
277 | msr contextidr_el1, x29 | |
905e8c5d | 278 | #else |
e28cabf1 | 279 | msr contextidr_el1, xzr |
905e8c5d | 280 | #endif |
e28cabf1 | 281 | 1: |
6ba3b554 | 282 | alternative_else_nop_endif |
905e8c5d | 283 | #endif |
60ffc30d | 284 | .endif |
39bc88e5 | 285 | |
63648dd2 WD |
286 | msr elr_el1, x21 // set up the return data |
287 | msr spsr_el1, x22 | |
63648dd2 | 288 | ldp x0, x1, [sp, #16 * 0] |
63648dd2 WD |
289 | ldp x2, x3, [sp, #16 * 1] |
290 | ldp x4, x5, [sp, #16 * 2] | |
291 | ldp x6, x7, [sp, #16 * 3] | |
292 | ldp x8, x9, [sp, #16 * 4] | |
293 | ldp x10, x11, [sp, #16 * 5] | |
294 | ldp x12, x13, [sp, #16 * 6] | |
295 | ldp x14, x15, [sp, #16 * 7] | |
296 | ldp x16, x17, [sp, #16 * 8] | |
297 | ldp x18, x19, [sp, #16 * 9] | |
298 | ldp x20, x21, [sp, #16 * 10] | |
299 | ldp x22, x23, [sp, #16 * 11] | |
300 | ldp x24, x25, [sp, #16 * 12] | |
301 | ldp x26, x27, [sp, #16 * 13] | |
302 | ldp x28, x29, [sp, #16 * 14] | |
303 | ldr lr, [sp, #S_LR] | |
304 | add sp, sp, #S_FRAME_SIZE // restore sp | |
60ffc30d CM |
305 | eret // return to kernel |
306 | .endm | |
307 | ||
971c67ce | 308 | .macro irq_stack_entry |
8e23dacd JM |
309 | mov x19, sp // preserve the original sp |
310 | ||
8e23dacd | 311 | /* |
c02433dd MR |
312 | * Compare sp with the base of the task stack. |
313 | * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack, | |
314 | * and should switch to the irq stack. | |
8e23dacd | 315 | */ |
c02433dd MR |
316 | ldr x25, [tsk, TSK_STACK] |
317 | eor x25, x25, x19 | |
318 | and x25, x25, #~(THREAD_SIZE - 1) | |
319 | cbnz x25, 9998f | |
8e23dacd | 320 | |
f60fe78f | 321 | ldr_this_cpu x25, irq_stack_ptr, x26 |
34be98f4 | 322 | mov x26, #IRQ_STACK_SIZE |
8e23dacd | 323 | add x26, x25, x26 |
d224a69e JM |
324 | |
325 | /* switch to the irq stack */ | |
8e23dacd | 326 | mov sp, x26 |
8e23dacd JM |
327 | 9998: |
328 | .endm | |
329 | ||
330 | /* | |
331 | * x19 should be preserved between irq_stack_entry and | |
332 | * irq_stack_exit. | |
333 | */ | |
334 | .macro irq_stack_exit | |
335 | mov sp, x19 | |
336 | .endm | |
337 | ||
60ffc30d CM |
338 | /* |
339 | * These are the registers used in the syscall handler, and allow us to | |
340 | * have in theory up to 7 arguments to a function - x0 to x6. | |
341 | * | |
342 | * x7 is reserved for the system call number in 32-bit mode. | |
343 | */ | |
35d0e6fb DM |
344 | wsc_nr .req w25 // number of system calls |
345 | wscno .req w26 // syscall number | |
346 | xscno .req x26 // syscall number (zero-extended) | |
60ffc30d CM |
347 | stbl .req x27 // syscall table pointer |
348 | tsk .req x28 // current thread_info | |
349 | ||
350 | /* | |
351 | * Interrupt handling. | |
352 | */ | |
353 | .macro irq_handler | |
8e23dacd | 354 | ldr_l x1, handle_arch_irq |
60ffc30d | 355 | mov x0, sp |
971c67ce | 356 | irq_stack_entry |
60ffc30d | 357 | blr x1 |
8e23dacd | 358 | irq_stack_exit |
60ffc30d CM |
359 | .endm |
360 | ||
361 | .text | |
362 | ||
363 | /* | |
364 | * Exception vectors. | |
365 | */ | |
888b3c87 | 366 | .pushsection ".entry.text", "ax" |
60ffc30d CM |
367 | |
368 | .align 11 | |
369 | ENTRY(vectors) | |
b11e5759 MR |
370 | kernel_ventry el1_sync_invalid // Synchronous EL1t |
371 | kernel_ventry el1_irq_invalid // IRQ EL1t | |
372 | kernel_ventry el1_fiq_invalid // FIQ EL1t | |
373 | kernel_ventry el1_error_invalid // Error EL1t | |
60ffc30d | 374 | |
b11e5759 MR |
375 | kernel_ventry el1_sync // Synchronous EL1h |
376 | kernel_ventry el1_irq // IRQ EL1h | |
377 | kernel_ventry el1_fiq_invalid // FIQ EL1h | |
378 | kernel_ventry el1_error_invalid // Error EL1h | |
60ffc30d | 379 | |
b11e5759 MR |
380 | kernel_ventry el0_sync // Synchronous 64-bit EL0 |
381 | kernel_ventry el0_irq // IRQ 64-bit EL0 | |
382 | kernel_ventry el0_fiq_invalid // FIQ 64-bit EL0 | |
383 | kernel_ventry el0_error_invalid // Error 64-bit EL0 | |
60ffc30d CM |
384 | |
385 | #ifdef CONFIG_COMPAT | |
b11e5759 MR |
386 | kernel_ventry el0_sync_compat // Synchronous 32-bit EL0 |
387 | kernel_ventry el0_irq_compat // IRQ 32-bit EL0 | |
388 | kernel_ventry el0_fiq_invalid_compat // FIQ 32-bit EL0 | |
389 | kernel_ventry el0_error_invalid_compat // Error 32-bit EL0 | |
60ffc30d | 390 | #else |
b11e5759 MR |
391 | kernel_ventry el0_sync_invalid // Synchronous 32-bit EL0 |
392 | kernel_ventry el0_irq_invalid // IRQ 32-bit EL0 | |
393 | kernel_ventry el0_fiq_invalid // FIQ 32-bit EL0 | |
394 | kernel_ventry el0_error_invalid // Error 32-bit EL0 | |
60ffc30d CM |
395 | #endif |
396 | END(vectors) | |
397 | ||
872d8327 MR |
398 | #ifdef CONFIG_VMAP_STACK |
399 | /* | |
400 | * We detected an overflow in kernel_ventry, which switched to the | |
401 | * overflow stack. Stash the exception regs, and head to our overflow | |
402 | * handler. | |
403 | */ | |
404 | __bad_stack: | |
405 | /* Restore the original x0 value */ | |
406 | mrs x0, tpidrro_el0 | |
407 | ||
408 | /* | |
409 | * Store the original GPRs to the new stack. The orginal SP (minus | |
410 | * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry. | |
411 | */ | |
412 | sub sp, sp, #S_FRAME_SIZE | |
413 | kernel_entry 1 | |
414 | mrs x0, tpidr_el0 | |
415 | add x0, x0, #S_FRAME_SIZE | |
416 | str x0, [sp, #S_SP] | |
417 | ||
418 | /* Stash the regs for handle_bad_stack */ | |
419 | mov x0, sp | |
420 | ||
421 | /* Time to die */ | |
422 | bl handle_bad_stack | |
423 | ASM_BUG() | |
424 | #endif /* CONFIG_VMAP_STACK */ | |
425 | ||
60ffc30d CM |
426 | /* |
427 | * Invalid mode handlers | |
428 | */ | |
429 | .macro inv_entry, el, reason, regsize = 64 | |
b660950c | 430 | kernel_entry \el, \regsize |
60ffc30d CM |
431 | mov x0, sp |
432 | mov x1, #\reason | |
433 | mrs x2, esr_el1 | |
2d0e751a MR |
434 | bl bad_mode |
435 | ASM_BUG() | |
60ffc30d CM |
436 | .endm |
437 | ||
438 | el0_sync_invalid: | |
439 | inv_entry 0, BAD_SYNC | |
440 | ENDPROC(el0_sync_invalid) | |
441 | ||
442 | el0_irq_invalid: | |
443 | inv_entry 0, BAD_IRQ | |
444 | ENDPROC(el0_irq_invalid) | |
445 | ||
446 | el0_fiq_invalid: | |
447 | inv_entry 0, BAD_FIQ | |
448 | ENDPROC(el0_fiq_invalid) | |
449 | ||
450 | el0_error_invalid: | |
451 | inv_entry 0, BAD_ERROR | |
452 | ENDPROC(el0_error_invalid) | |
453 | ||
454 | #ifdef CONFIG_COMPAT | |
455 | el0_fiq_invalid_compat: | |
456 | inv_entry 0, BAD_FIQ, 32 | |
457 | ENDPROC(el0_fiq_invalid_compat) | |
458 | ||
459 | el0_error_invalid_compat: | |
460 | inv_entry 0, BAD_ERROR, 32 | |
461 | ENDPROC(el0_error_invalid_compat) | |
462 | #endif | |
463 | ||
464 | el1_sync_invalid: | |
465 | inv_entry 1, BAD_SYNC | |
466 | ENDPROC(el1_sync_invalid) | |
467 | ||
468 | el1_irq_invalid: | |
469 | inv_entry 1, BAD_IRQ | |
470 | ENDPROC(el1_irq_invalid) | |
471 | ||
472 | el1_fiq_invalid: | |
473 | inv_entry 1, BAD_FIQ | |
474 | ENDPROC(el1_fiq_invalid) | |
475 | ||
476 | el1_error_invalid: | |
477 | inv_entry 1, BAD_ERROR | |
478 | ENDPROC(el1_error_invalid) | |
479 | ||
480 | /* | |
481 | * EL1 mode handlers. | |
482 | */ | |
483 | .align 6 | |
484 | el1_sync: | |
485 | kernel_entry 1 | |
486 | mrs x1, esr_el1 // read the syndrome register | |
aed40e01 MR |
487 | lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class |
488 | cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1 | |
60ffc30d | 489 | b.eq el1_da |
9adeb8e7 LA |
490 | cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1 |
491 | b.eq el1_ia | |
aed40e01 | 492 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
60ffc30d | 493 | b.eq el1_undef |
aed40e01 | 494 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 495 | b.eq el1_sp_pc |
aed40e01 | 496 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 497 | b.eq el1_sp_pc |
aed40e01 | 498 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1 |
60ffc30d | 499 | b.eq el1_undef |
aed40e01 | 500 | cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 |
60ffc30d CM |
501 | b.ge el1_dbg |
502 | b el1_inv | |
9adeb8e7 LA |
503 | |
504 | el1_ia: | |
505 | /* | |
506 | * Fall through to the Data abort case | |
507 | */ | |
60ffc30d CM |
508 | el1_da: |
509 | /* | |
510 | * Data abort handling | |
511 | */ | |
276e9327 | 512 | mrs x3, far_el1 |
b55a5a1b | 513 | inherit_daif pstate=x23, tmp=x2 |
276e9327 | 514 | clear_address_tag x0, x3 |
60ffc30d CM |
515 | mov x2, sp // struct pt_regs |
516 | bl do_mem_abort | |
517 | ||
60ffc30d CM |
518 | kernel_exit 1 |
519 | el1_sp_pc: | |
520 | /* | |
521 | * Stack or PC alignment exception handling | |
522 | */ | |
523 | mrs x0, far_el1 | |
b55a5a1b | 524 | inherit_daif pstate=x23, tmp=x2 |
60ffc30d | 525 | mov x2, sp |
2d0e751a MR |
526 | bl do_sp_pc_abort |
527 | ASM_BUG() | |
60ffc30d CM |
528 | el1_undef: |
529 | /* | |
530 | * Undefined instruction | |
531 | */ | |
b55a5a1b | 532 | inherit_daif pstate=x23, tmp=x2 |
60ffc30d | 533 | mov x0, sp |
2d0e751a MR |
534 | bl do_undefinstr |
535 | ASM_BUG() | |
60ffc30d CM |
536 | el1_dbg: |
537 | /* | |
538 | * Debug exception handling | |
539 | */ | |
aed40e01 | 540 | cmp x24, #ESR_ELx_EC_BRK64 // if BRK64 |
ee6214ce | 541 | cinc x24, x24, eq // set bit '0' |
60ffc30d CM |
542 | tbz x24, #0, el1_inv // EL1 only |
543 | mrs x0, far_el1 | |
544 | mov x2, sp // struct pt_regs | |
545 | bl do_debug_exception | |
60ffc30d CM |
546 | kernel_exit 1 |
547 | el1_inv: | |
548 | // TODO: add support for undefined instructions in kernel mode | |
b55a5a1b | 549 | inherit_daif pstate=x23, tmp=x2 |
60ffc30d | 550 | mov x0, sp |
1b42804d | 551 | mov x2, x1 |
60ffc30d | 552 | mov x1, #BAD_SYNC |
2d0e751a MR |
553 | bl bad_mode |
554 | ASM_BUG() | |
60ffc30d CM |
555 | ENDPROC(el1_sync) |
556 | ||
557 | .align 6 | |
558 | el1_irq: | |
559 | kernel_entry 1 | |
2a283070 | 560 | enable_dbg |
60ffc30d CM |
561 | #ifdef CONFIG_TRACE_IRQFLAGS |
562 | bl trace_hardirqs_off | |
563 | #endif | |
64681787 | 564 | |
60ffc30d | 565 | irq_handler |
64681787 | 566 | |
60ffc30d | 567 | #ifdef CONFIG_PREEMPT |
c02433dd | 568 | ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count |
717321fc | 569 | cbnz w24, 1f // preempt count != 0 |
c02433dd | 570 | ldr x0, [tsk, #TSK_TI_FLAGS] // get flags |
60ffc30d CM |
571 | tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? |
572 | bl el1_preempt | |
573 | 1: | |
574 | #endif | |
575 | #ifdef CONFIG_TRACE_IRQFLAGS | |
576 | bl trace_hardirqs_on | |
577 | #endif | |
578 | kernel_exit 1 | |
579 | ENDPROC(el1_irq) | |
580 | ||
581 | #ifdef CONFIG_PREEMPT | |
582 | el1_preempt: | |
583 | mov x24, lr | |
2a283070 | 584 | 1: bl preempt_schedule_irq // irq en/disable is done inside |
c02433dd | 585 | ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS |
60ffc30d CM |
586 | tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling? |
587 | ret x24 | |
588 | #endif | |
589 | ||
590 | /* | |
591 | * EL0 mode handlers. | |
592 | */ | |
593 | .align 6 | |
594 | el0_sync: | |
595 | kernel_entry 0 | |
596 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
597 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
598 | cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state | |
60ffc30d | 599 | b.eq el0_svc |
aed40e01 | 600 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 601 | b.eq el0_da |
aed40e01 | 602 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 603 | b.eq el0_ia |
aed40e01 | 604 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 605 | b.eq el0_fpsimd_acc |
aed40e01 | 606 | cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception |
60ffc30d | 607 | b.eq el0_fpsimd_exc |
aed40e01 | 608 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
7dd01aef | 609 | b.eq el0_sys |
aed40e01 | 610 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 611 | b.eq el0_sp_pc |
aed40e01 | 612 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 613 | b.eq el0_sp_pc |
aed40e01 | 614 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 615 | b.eq el0_undef |
aed40e01 | 616 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
617 | b.ge el0_dbg |
618 | b el0_inv | |
619 | ||
620 | #ifdef CONFIG_COMPAT | |
621 | .align 6 | |
622 | el0_sync_compat: | |
623 | kernel_entry 0, 32 | |
624 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
625 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
626 | cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state | |
60ffc30d | 627 | b.eq el0_svc_compat |
aed40e01 | 628 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 629 | b.eq el0_da |
aed40e01 | 630 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 631 | b.eq el0_ia |
aed40e01 | 632 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 633 | b.eq el0_fpsimd_acc |
aed40e01 | 634 | cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception |
60ffc30d | 635 | b.eq el0_fpsimd_exc |
77f3228f MS |
636 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
637 | b.eq el0_sp_pc | |
aed40e01 | 638 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 639 | b.eq el0_undef |
aed40e01 | 640 | cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap |
381cc2b9 | 641 | b.eq el0_undef |
aed40e01 | 642 | cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap |
381cc2b9 | 643 | b.eq el0_undef |
aed40e01 | 644 | cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap |
381cc2b9 | 645 | b.eq el0_undef |
aed40e01 | 646 | cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap |
381cc2b9 | 647 | b.eq el0_undef |
aed40e01 | 648 | cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap |
381cc2b9 | 649 | b.eq el0_undef |
aed40e01 | 650 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
651 | b.ge el0_dbg |
652 | b el0_inv | |
653 | el0_svc_compat: | |
654 | /* | |
655 | * AArch32 syscall handling | |
656 | */ | |
0156411b | 657 | adrp stbl, compat_sys_call_table // load compat syscall table pointer |
35d0e6fb DM |
658 | mov wscno, w7 // syscall number in w7 (r7) |
659 | mov wsc_nr, #__NR_compat_syscalls | |
60ffc30d CM |
660 | b el0_svc_naked |
661 | ||
662 | .align 6 | |
663 | el0_irq_compat: | |
664 | kernel_entry 0, 32 | |
665 | b el0_irq_naked | |
666 | #endif | |
667 | ||
668 | el0_da: | |
669 | /* | |
670 | * Data abort handling | |
671 | */ | |
6ab6463a | 672 | mrs x26, far_el1 |
60ffc30d | 673 | // enable interrupts before calling the main handler |
2a283070 | 674 | enable_dbg_and_irq |
6c81fe79 | 675 | ct_user_exit |
276e9327 | 676 | clear_address_tag x0, x26 |
60ffc30d CM |
677 | mov x1, x25 |
678 | mov x2, sp | |
d54e81f9 WD |
679 | bl do_mem_abort |
680 | b ret_to_user | |
60ffc30d CM |
681 | el0_ia: |
682 | /* | |
683 | * Instruction abort handling | |
684 | */ | |
6ab6463a | 685 | mrs x26, far_el1 |
60ffc30d | 686 | // enable interrupts before calling the main handler |
2a283070 | 687 | enable_dbg_and_irq |
6c81fe79 | 688 | ct_user_exit |
6ab6463a | 689 | mov x0, x26 |
541ec870 | 690 | mov x1, x25 |
60ffc30d | 691 | mov x2, sp |
d54e81f9 WD |
692 | bl do_mem_abort |
693 | b ret_to_user | |
60ffc30d CM |
694 | el0_fpsimd_acc: |
695 | /* | |
696 | * Floating Point or Advanced SIMD access | |
697 | */ | |
2a283070 | 698 | enable_dbg |
6c81fe79 | 699 | ct_user_exit |
60ffc30d CM |
700 | mov x0, x25 |
701 | mov x1, sp | |
d54e81f9 WD |
702 | bl do_fpsimd_acc |
703 | b ret_to_user | |
60ffc30d CM |
704 | el0_fpsimd_exc: |
705 | /* | |
706 | * Floating Point or Advanced SIMD exception | |
707 | */ | |
2a283070 | 708 | enable_dbg |
6c81fe79 | 709 | ct_user_exit |
60ffc30d CM |
710 | mov x0, x25 |
711 | mov x1, sp | |
d54e81f9 WD |
712 | bl do_fpsimd_exc |
713 | b ret_to_user | |
60ffc30d CM |
714 | el0_sp_pc: |
715 | /* | |
716 | * Stack or PC alignment exception handling | |
717 | */ | |
6ab6463a | 718 | mrs x26, far_el1 |
60ffc30d | 719 | // enable interrupts before calling the main handler |
2a283070 | 720 | enable_dbg_and_irq |
46b0567c | 721 | ct_user_exit |
6ab6463a | 722 | mov x0, x26 |
60ffc30d CM |
723 | mov x1, x25 |
724 | mov x2, sp | |
d54e81f9 WD |
725 | bl do_sp_pc_abort |
726 | b ret_to_user | |
60ffc30d CM |
727 | el0_undef: |
728 | /* | |
729 | * Undefined instruction | |
730 | */ | |
2600e130 | 731 | // enable interrupts before calling the main handler |
2a283070 | 732 | enable_dbg_and_irq |
6c81fe79 | 733 | ct_user_exit |
2a283070 | 734 | mov x0, sp |
d54e81f9 WD |
735 | bl do_undefinstr |
736 | b ret_to_user | |
7dd01aef AP |
737 | el0_sys: |
738 | /* | |
739 | * System instructions, for trapped cache maintenance instructions | |
740 | */ | |
741 | enable_dbg_and_irq | |
742 | ct_user_exit | |
743 | mov x0, x25 | |
744 | mov x1, sp | |
745 | bl do_sysinstr | |
746 | b ret_to_user | |
60ffc30d CM |
747 | el0_dbg: |
748 | /* | |
749 | * Debug exception handling | |
750 | */ | |
751 | tbnz x24, #0, el0_inv // EL0 only | |
752 | mrs x0, far_el1 | |
60ffc30d CM |
753 | mov x1, x25 |
754 | mov x2, sp | |
2a283070 WD |
755 | bl do_debug_exception |
756 | enable_dbg | |
6c81fe79 | 757 | ct_user_exit |
2a283070 | 758 | b ret_to_user |
60ffc30d | 759 | el0_inv: |
2a283070 | 760 | enable_dbg |
6c81fe79 | 761 | ct_user_exit |
60ffc30d CM |
762 | mov x0, sp |
763 | mov x1, #BAD_SYNC | |
1b42804d | 764 | mov x2, x25 |
7d9e8f71 | 765 | bl bad_el0_sync |
d54e81f9 | 766 | b ret_to_user |
60ffc30d CM |
767 | ENDPROC(el0_sync) |
768 | ||
769 | .align 6 | |
770 | el0_irq: | |
771 | kernel_entry 0 | |
772 | el0_irq_naked: | |
60ffc30d CM |
773 | enable_dbg |
774 | #ifdef CONFIG_TRACE_IRQFLAGS | |
775 | bl trace_hardirqs_off | |
776 | #endif | |
64681787 | 777 | |
6c81fe79 | 778 | ct_user_exit |
60ffc30d | 779 | irq_handler |
64681787 | 780 | |
60ffc30d CM |
781 | #ifdef CONFIG_TRACE_IRQFLAGS |
782 | bl trace_hardirqs_on | |
783 | #endif | |
784 | b ret_to_user | |
785 | ENDPROC(el0_irq) | |
786 | ||
60ffc30d CM |
787 | /* |
788 | * This is the fast syscall return path. We do as little as possible here, | |
789 | * and this includes saving x0 back into the kernel stack. | |
790 | */ | |
791 | ret_fast_syscall: | |
8d66772e | 792 | disable_daif |
412fcb6c | 793 | str x0, [sp, #S_X0] // returned x0 |
c02433dd | 794 | ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for syscall tracing |
04d7e098 JS |
795 | and x2, x1, #_TIF_SYSCALL_WORK |
796 | cbnz x2, ret_fast_syscall_trace | |
60ffc30d | 797 | and x2, x1, #_TIF_WORK_MASK |
412fcb6c | 798 | cbnz x2, work_pending |
2a283070 | 799 | enable_step_tsk x1, x2 |
412fcb6c | 800 | kernel_exit 0 |
04d7e098 | 801 | ret_fast_syscall_trace: |
8d66772e | 802 | enable_daif |
412fcb6c | 803 | b __sys_trace_return_skipped // we already saved x0 |
60ffc30d CM |
804 | |
805 | /* | |
806 | * Ok, we need to do extra processing, enter the slow path. | |
807 | */ | |
60ffc30d | 808 | work_pending: |
60ffc30d | 809 | mov x0, sp // 'regs' |
60ffc30d | 810 | bl do_notify_resume |
db3899a6 | 811 | #ifdef CONFIG_TRACE_IRQFLAGS |
421dd6fa | 812 | bl trace_hardirqs_on // enabled while in userspace |
db3899a6 | 813 | #endif |
c02433dd | 814 | ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step |
421dd6fa | 815 | b finish_ret_to_user |
60ffc30d CM |
816 | /* |
817 | * "slow" syscall return path. | |
818 | */ | |
59dc67b0 | 819 | ret_to_user: |
8d66772e | 820 | disable_daif |
c02433dd | 821 | ldr x1, [tsk, #TSK_TI_FLAGS] |
60ffc30d CM |
822 | and x2, x1, #_TIF_WORK_MASK |
823 | cbnz x2, work_pending | |
421dd6fa | 824 | finish_ret_to_user: |
2a283070 | 825 | enable_step_tsk x1, x2 |
412fcb6c | 826 | kernel_exit 0 |
60ffc30d CM |
827 | ENDPROC(ret_to_user) |
828 | ||
60ffc30d CM |
829 | /* |
830 | * SVC handler. | |
831 | */ | |
832 | .align 6 | |
833 | el0_svc: | |
834 | adrp stbl, sys_call_table // load syscall table pointer | |
35d0e6fb DM |
835 | mov wscno, w8 // syscall number in w8 |
836 | mov wsc_nr, #__NR_syscalls | |
60ffc30d | 837 | el0_svc_naked: // compat entry point |
35d0e6fb | 838 | stp x0, xscno, [sp, #S_ORIG_X0] // save the original x0 and syscall number |
2a283070 | 839 | enable_dbg_and_irq |
6c81fe79 | 840 | ct_user_exit 1 |
60ffc30d | 841 | |
c02433dd | 842 | ldr x16, [tsk, #TSK_TI_FLAGS] // check for syscall hooks |
449f81a4 AT |
843 | tst x16, #_TIF_SYSCALL_WORK |
844 | b.ne __sys_trace | |
35d0e6fb | 845 | cmp wscno, wsc_nr // check upper syscall limit |
60ffc30d | 846 | b.hs ni_sys |
35d0e6fb | 847 | ldr x16, [stbl, xscno, lsl #3] // address in the syscall table |
d54e81f9 WD |
848 | blr x16 // call sys_* routine |
849 | b ret_fast_syscall | |
60ffc30d CM |
850 | ni_sys: |
851 | mov x0, sp | |
d54e81f9 WD |
852 | bl do_ni_syscall |
853 | b ret_fast_syscall | |
60ffc30d CM |
854 | ENDPROC(el0_svc) |
855 | ||
856 | /* | |
857 | * This is the really slow path. We're going to be doing context | |
858 | * switches, and waiting for our parent to respond. | |
859 | */ | |
860 | __sys_trace: | |
17c28958 | 861 | cmp wscno, #NO_SYSCALL // user-issued syscall(-1)? |
1014c81d | 862 | b.ne 1f |
35d0e6fb | 863 | mov x0, #-ENOSYS // set default errno if so |
1014c81d AT |
864 | str x0, [sp, #S_X0] |
865 | 1: mov x0, sp | |
3157858f | 866 | bl syscall_trace_enter |
17c28958 | 867 | cmp w0, #NO_SYSCALL // skip the syscall? |
1014c81d | 868 | b.eq __sys_trace_return_skipped |
35d0e6fb | 869 | mov wscno, w0 // syscall number (possibly new) |
60ffc30d | 870 | mov x1, sp // pointer to regs |
35d0e6fb | 871 | cmp wscno, wsc_nr // check upper syscall limit |
d54e81f9 | 872 | b.hs __ni_sys_trace |
60ffc30d CM |
873 | ldp x0, x1, [sp] // restore the syscall args |
874 | ldp x2, x3, [sp, #S_X2] | |
875 | ldp x4, x5, [sp, #S_X4] | |
876 | ldp x6, x7, [sp, #S_X6] | |
35d0e6fb | 877 | ldr x16, [stbl, xscno, lsl #3] // address in the syscall table |
d54e81f9 | 878 | blr x16 // call sys_* routine |
60ffc30d CM |
879 | |
880 | __sys_trace_return: | |
1014c81d AT |
881 | str x0, [sp, #S_X0] // save returned x0 |
882 | __sys_trace_return_skipped: | |
3157858f AT |
883 | mov x0, sp |
884 | bl syscall_trace_exit | |
60ffc30d CM |
885 | b ret_to_user |
886 | ||
d54e81f9 WD |
887 | __ni_sys_trace: |
888 | mov x0, sp | |
889 | bl do_ni_syscall | |
890 | b __sys_trace_return | |
891 | ||
888b3c87 PA |
892 | .popsection // .entry.text |
893 | ||
60ffc30d CM |
894 | /* |
895 | * Special system call wrappers. | |
896 | */ | |
60ffc30d CM |
897 | ENTRY(sys_rt_sigreturn_wrapper) |
898 | mov x0, sp | |
899 | b sys_rt_sigreturn | |
900 | ENDPROC(sys_rt_sigreturn_wrapper) | |
ed84b4e9 MR |
901 | |
902 | /* | |
903 | * Register switch for AArch64. The callee-saved registers need to be saved | |
904 | * and restored. On entry: | |
905 | * x0 = previous task_struct (must be preserved across the switch) | |
906 | * x1 = next task_struct | |
907 | * Previous and next are guaranteed not to be the same. | |
908 | * | |
909 | */ | |
910 | ENTRY(cpu_switch_to) | |
911 | mov x10, #THREAD_CPU_CONTEXT | |
912 | add x8, x0, x10 | |
913 | mov x9, sp | |
914 | stp x19, x20, [x8], #16 // store callee-saved registers | |
915 | stp x21, x22, [x8], #16 | |
916 | stp x23, x24, [x8], #16 | |
917 | stp x25, x26, [x8], #16 | |
918 | stp x27, x28, [x8], #16 | |
919 | stp x29, x9, [x8], #16 | |
920 | str lr, [x8] | |
921 | add x8, x1, x10 | |
922 | ldp x19, x20, [x8], #16 // restore callee-saved registers | |
923 | ldp x21, x22, [x8], #16 | |
924 | ldp x23, x24, [x8], #16 | |
925 | ldp x25, x26, [x8], #16 | |
926 | ldp x27, x28, [x8], #16 | |
927 | ldp x29, x9, [x8], #16 | |
928 | ldr lr, [x8] | |
929 | mov sp, x9 | |
930 | msr sp_el0, x1 | |
931 | ret | |
932 | ENDPROC(cpu_switch_to) | |
933 | NOKPROBE(cpu_switch_to) | |
934 | ||
935 | /* | |
936 | * This is how we return from a fork. | |
937 | */ | |
938 | ENTRY(ret_from_fork) | |
939 | bl schedule_tail | |
940 | cbz x19, 1f // not a kernel thread | |
941 | mov x0, x20 | |
942 | blr x19 | |
943 | 1: get_thread_info tsk | |
944 | b ret_to_user | |
945 | ENDPROC(ret_from_fork) | |
946 | NOKPROBE(ret_from_fork) |