[thirdparty/kernel/stable.git] / arch / arm64 / kernel / process.c

/*
 * Based on arch/arm/kernel/process.c
 *
 * Original Copyright (C) 1995  Linus Torvalds
 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <stdarg.h>

#include <linux/compat.h>
#include <linux/efi.h>
#include <linux/export.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/user.h>
#include <linux/delay.h>
#include <linux/reboot.h>
#include <linux/interrupt.h>
#include <linux/kallsyms.h>
#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/elfcore.h>
#include <linux/pm.h>
#include <linux/tick.h>
#include <linux/utsname.h>
#include <linux/uaccess.h>
#include <linux/random.h>
#include <linux/hw_breakpoint.h>
#include <linux/personality.h>
#include <linux/notifier.h>
#include <trace/events/power.h>

#include <asm/alternative.h>
#include <asm/compat.h>
#include <asm/cacheflush.h>
#include <asm/fpsimd.h>
#include <asm/mmu_context.h>
#include <asm/processor.h>
#include <asm/stacktrace.h>

#ifdef CONFIG_CC_STACKPROTECTOR
#include <linux/stackprotector.h>
unsigned long __stack_chk_guard __read_mostly;
EXPORT_SYMBOL(__stack_chk_guard);
#endif

/*
 * Function pointers to optional machine specific functions
 */
void (*pm_power_off)(void);
EXPORT_SYMBOL_GPL(pm_power_off);

void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);

/*
 * This is our default idle handler.
 */
void arch_cpu_idle(void)
{
	/*
	 * This should do all the clock switching and wait for interrupt
	 * tricks
	 */
	trace_cpu_idle_rcuidle(1, smp_processor_id());
	cpu_do_idle();
	local_irq_enable();
	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
}

#ifdef CONFIG_HOTPLUG_CPU
void arch_cpu_idle_dead(void)
{
       cpu_die();
}
#endif

/*
 * Called by kexec, immediately prior to machine_kexec().
 *
 * This must completely disable all secondary CPUs; simply causing those CPUs
 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
 * kexec'd kernel to use any and all RAM as it sees fit, without having to
 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
 * functionality embodied in disable_nonboot_cpus() to achieve this.
 */
void machine_shutdown(void)
{
	disable_nonboot_cpus();
}

/*
 * Halting simply requires that the secondary CPUs stop performing any
 * activity (executing tasks, handling interrupts). smp_send_stop()
 * achieves this.
 */
void machine_halt(void)
{
	local_irq_disable();
	smp_send_stop();
	while (1);
}

/*
 * Power-off simply requires that the secondary CPUs stop performing any
 * activity (executing tasks, handling interrupts). smp_send_stop()
 * achieves this. When the system power is turned off, it will take all CPUs
 * with it.
 */
void machine_power_off(void)
{
	local_irq_disable();
	smp_send_stop();
	if (pm_power_off)
		pm_power_off();
}

/*
 * Restart requires that the secondary CPUs stop performing any activity
 * while the primary CPU resets the system. Systems with multiple CPUs must
 * provide a HW restart implementation, to ensure that all CPUs reset at once.
 * This is required so that any code running after reset on the primary CPU
 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
 * executing pre-reset code, and using RAM that the primary CPU's code wishes
 * to use. Implementing such co-ordination would be essentially impossible.
 */
void machine_restart(char *cmd)
{
	/* Disable interrupts first */
	local_irq_disable();
	smp_send_stop();

	/*
	 * UpdateCapsule() depends on the system being reset via
	 * ResetSystem().
	 */
	if (efi_enabled(EFI_RUNTIME_SERVICES))
		efi_reboot(reboot_mode, NULL);

	/* Now call the architecture specific reboot code. */
	if (arm_pm_restart)
		arm_pm_restart(reboot_mode, cmd);
	else
		do_kernel_restart(cmd);

	/*
	 * Whoops - the architecture was unable to reboot.
	 */
	printk("Reboot failed -- System halted\n");
	while (1);
}

void __show_regs(struct pt_regs *regs)
{
	int i, top_reg;
	u64 lr, sp;

	if (compat_user_mode(regs)) {
		lr = regs->compat_lr;
		sp = regs->compat_sp;
		top_reg = 12;
	} else {
		lr = regs->regs[30];
		sp = regs->sp;
		top_reg = 29;
	}

	show_regs_print_info(KERN_DEFAULT);
	print_symbol("PC is at %s\n", instruction_pointer(regs));
	print_symbol("LR is at %s\n", lr);
	printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
	       regs->pc, lr, regs->pstate);
	printk("sp : %016llx\n", sp);
	for (i = top_reg; i >= 0; i--) {
		printk("x%-2d: %016llx ", i, regs->regs[i]);
		if (i % 2 == 0)
			printk("\n");
	}
	printk("\n");
}

void show_regs(struct pt_regs * regs)
{
	printk("\n");
	__show_regs(regs);
}

/*
 * Free current thread data structures etc..
 */
void exit_thread(void)
{
}

static void tls_thread_flush(void)
{
	asm ("msr tpidr_el0, xzr");

	if (is_compat_task()) {
		current->thread.tp_value = 0;

		/*
		 * We need to ensure ordering between the shadow state and the
		 * hardware state, so that we don't corrupt the hardware state
		 * with a stale shadow state during context switch.
		 */
		barrier();
		asm ("msr tpidrro_el0, xzr");
	}
}

void flush_thread(void)
{
	fpsimd_flush_thread();
	tls_thread_flush();
	flush_ptrace_hw_breakpoint(current);
}

void release_thread(struct task_struct *dead_task)
{
}

int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
{
	if (current->mm)
		fpsimd_preserve_current_state();
	*dst = *src;
	return 0;
}

asmlinkage void ret_from_fork(void) asm("ret_from_fork");

int copy_thread(unsigned long clone_flags, unsigned long stack_start,
		unsigned long stk_sz, struct task_struct *p)
{
	struct pt_regs *childregs = task_pt_regs(p);

	memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));

	if (likely(!(p->flags & PF_KTHREAD))) {
		*childregs = *current_pt_regs();
		childregs->regs[0] = 0;

		/*
		 * Read the current TLS pointer from tpidr_el0 as it may be
		 * out-of-sync with the saved value.
		 */
		asm("mrs %0, tpidr_el0" : "=r" (*task_user_tls(p)));

		if (stack_start) {
			if (is_compat_thread(task_thread_info(p)))
				childregs->compat_sp = stack_start;
			/* 16-byte aligned stack mandatory on AArch64 */
			else if (stack_start & 15)
				return -EINVAL;
			else
				childregs->sp = stack_start;
		}

		/*
		 * If a TLS pointer was passed to clone (4th argument), use it
		 * for the new thread.
		 */
		if (clone_flags & CLONE_SETTLS)
			p->thread.tp_value = childregs->regs[3];
	} else {
		memset(childregs, 0, sizeof(struct pt_regs));
		childregs->pstate = PSR_MODE_EL1h;
		if (IS_ENABLED(CONFIG_ARM64_UAO) &&
		    cpus_have_cap(ARM64_HAS_UAO))
			childregs->pstate |= PSR_UAO_BIT;
		p->thread.cpu_context.x19 = stack_start;
		p->thread.cpu_context.x20 = stk_sz;
	}
	p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
	p->thread.cpu_context.sp = (unsigned long)childregs;

	ptrace_hw_copy_thread(p);

	return 0;
}

static void tls_thread_switch(struct task_struct *next)
{
	unsigned long tpidr, tpidrro;

	asm("mrs %0, tpidr_el0" : "=r" (tpidr));
	*task_user_tls(current) = tpidr;

	tpidr = *task_user_tls(next);
	tpidrro = is_compat_thread(task_thread_info(next)) ?
		  next->thread.tp_value : 0;

	asm(
	"	msr	tpidr_el0, %0\n"
	"	msr	tpidrro_el0, %1"
	: : "r" (tpidr), "r" (tpidrro));
}

/* Restore the UAO state depending on next's addr_limit */
static void uao_thread_switch(struct task_struct *next)
{
	if (IS_ENABLED(CONFIG_ARM64_UAO)) {
		if (task_thread_info(next)->addr_limit == KERNEL_DS)
			asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
		else
			asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO));
	}
}

/*
 * Thread switching.
 */
struct task_struct *__switch_to(struct task_struct *prev,
				struct task_struct *next)
{
	struct task_struct *last;

	fpsimd_thread_switch(next);
	tls_thread_switch(next);
	hw_breakpoint_thread_switch(next);
	contextidr_thread_switch(next);
	uao_thread_switch(next);

	/*
	 * Complete any pending TLB or cache maintenance on this CPU in case
	 * the thread migrates to a different CPU.
	 */
	dsb(ish);

	/* the actual thread switch */
	last = cpu_switch_to(prev, next);

	return last;
}

unsigned long get_wchan(struct task_struct *p)
{
	struct stackframe frame;
	unsigned long stack_page;
	int count = 0;
	if (!p || p == current || p->state == TASK_RUNNING)
		return 0;

	frame.fp = thread_saved_fp(p);
	frame.sp = thread_saved_sp(p);
	frame.pc = thread_saved_pc(p);
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
	frame.graph = p->curr_ret_stack;
#endif
	stack_page = (unsigned long)task_stack_page(p);
	do {
		if (frame.sp < stack_page ||
		    frame.sp >= stack_page + THREAD_SIZE ||
		    unwind_frame(p, &frame))
			return 0;
		if (!in_sched_functions(frame.pc))
			return frame.pc;
	} while (count ++ < 16);
	return 0;
}

unsigned long arch_align_stack(unsigned long sp)
{
	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
		sp -= get_random_int() & ~PAGE_MASK;
	return sp & ~0xf;
}

static unsigned long randomize_base(unsigned long base)
{
	unsigned long range_end = base + (STACK_RND_MASK << PAGE_SHIFT) + 1;
	return randomize_range(base, range_end, 0) ? : base;
}

unsigned long arch_randomize_brk(struct mm_struct *mm)
{
	return randomize_base(mm->brk);
}
Commit	Line	Data
b3901d54 CM	1	/*
	2	* Based on arch/arm/kernel/process.c
	3	*
	4	* Original Copyright (C) 1995 Linus Torvalds
	5	* Copyright (C) 1996-2000 Russell King - Converted to ARM.
	6	* Copyright (C) 2012 ARM Ltd.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include <stdarg.h>
	22
fd92d4a5	23	#include <linux/compat.h>
60c0d45a	24	#include <linux/efi.h>
b3901d54 CM	25	#include <linux/export.h>
	26	#include <linux/sched.h>
	27	#include <linux/kernel.h>
	28	#include <linux/mm.h>
	29	#include <linux/stddef.h>
	30	#include <linux/unistd.h>
	31	#include <linux/user.h>
	32	#include <linux/delay.h>
	33	#include <linux/reboot.h>
	34	#include <linux/interrupt.h>
	35	#include <linux/kallsyms.h>
	36	#include <linux/init.h>
	37	#include <linux/cpu.h>
	38	#include <linux/elfcore.h>
	39	#include <linux/pm.h>
	40	#include <linux/tick.h>
	41	#include <linux/utsname.h>
	42	#include <linux/uaccess.h>
	43	#include <linux/random.h>
	44	#include <linux/hw_breakpoint.h>
	45	#include <linux/personality.h>
	46	#include <linux/notifier.h>
096b3224	47	#include <trace/events/power.h>
b3901d54	48
57f4959b	49	#include <asm/alternative.h>
b3901d54 CM	50	#include <asm/compat.h>
b3901d54 CM	51	#include <asm/cacheflush.h>
ec45d1cf WD	52	#include <asm/fpsimd.h>
ec45d1cf WD	53	#include <asm/mmu_context.h>
b3901d54 CM	54	#include <asm/processor.h>
b3901d54 CM	55	#include <asm/stacktrace.h>
b3901d54	56
c0c264ae LA	57	#ifdef CONFIG_CC_STACKPROTECTOR
	58	#include <linux/stackprotector.h>
	59	unsigned long __stack_chk_guard __read_mostly;
	60	EXPORT_SYMBOL(__stack_chk_guard);
	61	#endif
	62
b3901d54 CM	63	/*
	64	* Function pointers to optional machine specific functions
	65	*/
	66	void (*pm_power_off)(void);
	67	EXPORT_SYMBOL_GPL(pm_power_off);
	68
b0946fc8	69	void (arm_pm_restart)(enum reboot_mode reboot_mode, const char cmd);
b3901d54	70
b3901d54 CM	71	/*
	72	* This is our default idle handler.
	73	*/
0087298f	74	void arch_cpu_idle(void)
b3901d54 CM	75	{
	76	/*
	77	* This should do all the clock switching and wait for interrupt
	78	* tricks
	79	*/
096b3224	80	trace_cpu_idle_rcuidle(1, smp_processor_id());
6990566b NP	81	cpu_do_idle();
6990566b NP	82	local_irq_enable();
096b3224	83	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
b3901d54 CM	84	}
b3901d54 CM	85
9327e2c6 MR	86	#ifdef CONFIG_HOTPLUG_CPU
	87	void arch_cpu_idle_dead(void)
	88	{
	89	cpu_die();
	90	}
	91	#endif
	92
90f51a09 AK	93	/*
	94	* Called by kexec, immediately prior to machine_kexec().
	95	*
	96	* This must completely disable all secondary CPUs; simply causing those CPUs
	97	* to execute e.g. a RAM-based pin loop is not sufficient. This allows the
	98	* kexec'd kernel to use any and all RAM as it sees fit, without having to
	99	* avoid any code or data used by any SW CPU pin loop. The CPU hotplug
	100	* functionality embodied in disable_nonboot_cpus() to achieve this.
	101	*/
b3901d54 CM	102	void machine_shutdown(void)
b3901d54 CM	103	{
90f51a09	104	disable_nonboot_cpus();
b3901d54 CM	105	}
b3901d54 CM	106
90f51a09 AK	107	/*
	108	* Halting simply requires that the secondary CPUs stop performing any
	109	* activity (executing tasks, handling interrupts). smp_send_stop()
	110	* achieves this.
	111	*/
b3901d54 CM	112	void machine_halt(void)
b3901d54 CM	113	{
b9acc49e	114	local_irq_disable();
90f51a09	115	smp_send_stop();
b3901d54 CM	116	while (1);
	117	}
	118
90f51a09 AK	119	/*
	120	* Power-off simply requires that the secondary CPUs stop performing any
	121	* activity (executing tasks, handling interrupts). smp_send_stop()
	122	* achieves this. When the system power is turned off, it will take all CPUs
	123	* with it.
	124	*/
b3901d54 CM	125	void machine_power_off(void)
b3901d54 CM	126	{
b9acc49e	127	local_irq_disable();
90f51a09	128	smp_send_stop();
b3901d54 CM	129	if (pm_power_off)
	130	pm_power_off();
	131	}
	132
90f51a09 AK	133	/*
90f51a09 AK	134	* Restart requires that the secondary CPUs stop performing any activity
68234df4	135	* while the primary CPU resets the system. Systems with multiple CPUs must
90f51a09 AK	136	* provide a HW restart implementation, to ensure that all CPUs reset at once.
	137	* This is required so that any code running after reset on the primary CPU
	138	* doesn't have to co-ordinate with other CPUs to ensure they aren't still
	139	* executing pre-reset code, and using RAM that the primary CPU's code wishes
	140	* to use. Implementing such co-ordination would be essentially impossible.
	141	*/
b3901d54 CM	142	void machine_restart(char *cmd)
b3901d54 CM	143	{
b3901d54 CM	144	/* Disable interrupts first */
b3901d54 CM	145	local_irq_disable();
b9acc49e	146	smp_send_stop();
b3901d54	147
60c0d45a AB	148	/*
	149	* UpdateCapsule() depends on the system being reset via
	150	* ResetSystem().
	151	*/
	152	if (efi_enabled(EFI_RUNTIME_SERVICES))
	153	efi_reboot(reboot_mode, NULL);
	154
b3901d54	155	/* Now call the architecture specific reboot code. */
aa1e8ec1	156	if (arm_pm_restart)
ff701306	157	arm_pm_restart(reboot_mode, cmd);
1c7ffc32 GR	158	else
1c7ffc32 GR	159	do_kernel_restart(cmd);
b3901d54 CM	160
	161	/*
	162	* Whoops - the architecture was unable to reboot.
	163	*/
	164	printk("Reboot failed -- System halted\n");
	165	while (1);
	166	}
	167
	168	void __show_regs(struct pt_regs *regs)
	169	{
6ca68e80 CM	170	int i, top_reg;
	171	u64 lr, sp;
	172
	173	if (compat_user_mode(regs)) {
	174	lr = regs->compat_lr;
	175	sp = regs->compat_sp;
	176	top_reg = 12;
	177	} else {
	178	lr = regs->regs[30];
	179	sp = regs->sp;
	180	top_reg = 29;
	181	}
b3901d54	182
a43cb95d	183	show_regs_print_info(KERN_DEFAULT);
b3901d54	184	print_symbol("PC is at %s\n", instruction_pointer(regs));
6ca68e80	185	print_symbol("LR is at %s\n", lr);
b3901d54	186	printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
6ca68e80 CM	187	regs->pc, lr, regs->pstate);
	188	printk("sp : %016llx\n", sp);
	189	for (i = top_reg; i >= 0; i--) {
b3901d54 CM	190	printk("x%-2d: %016llx ", i, regs->regs[i]);
	191	if (i % 2 == 0)
	192	printk("\n");
	193	}
	194	printk("\n");
	195	}
	196
	197	void show_regs(struct pt_regs * regs)
	198	{
	199	printk("\n");
b3901d54 CM	200	__show_regs(regs);
	201	}
	202
	203	/*
	204	* Free current thread data structures etc..
	205	*/
	206	void exit_thread(void)
	207	{
	208	}
	209
eb35bdd7 WD	210	static void tls_thread_flush(void)
	211	{
	212	asm ("msr tpidr_el0, xzr");
	213
	214	if (is_compat_task()) {
	215	current->thread.tp_value = 0;
	216
	217	/*
	218	* We need to ensure ordering between the shadow state and the
	219	* hardware state, so that we don't corrupt the hardware state
	220	* with a stale shadow state during context switch.
	221	*/
	222	barrier();
	223	asm ("msr tpidrro_el0, xzr");
	224	}
	225	}
	226
b3901d54 CM	227	void flush_thread(void)
	228	{
	229	fpsimd_flush_thread();
eb35bdd7	230	tls_thread_flush();
b3901d54 CM	231	flush_ptrace_hw_breakpoint(current);
	232	}
	233
	234	void release_thread(struct task_struct *dead_task)
	235	{
	236	}
	237
	238	int arch_dup_task_struct(struct task_struct dst, struct task_struct src)
	239	{
6eb6c801 JL	240	if (current->mm)
6eb6c801 JL	241	fpsimd_preserve_current_state();
b3901d54 CM	242	dst = src;
	243	return 0;
	244	}
	245
	246	asmlinkage void ret_from_fork(void) asm("ret_from_fork");
	247
	248	int copy_thread(unsigned long clone_flags, unsigned long stack_start,
afa86fc4	249	unsigned long stk_sz, struct task_struct *p)
b3901d54 CM	250	{
b3901d54 CM	251	struct pt_regs *childregs = task_pt_regs(p);
b3901d54	252
c34501d2	253	memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
b3901d54	254
9ac08002 AV	255	if (likely(!(p->flags & PF_KTHREAD))) {
9ac08002 AV	256	childregs = current_pt_regs();
c34501d2	257	childregs->regs[0] = 0;
d00a3810 WD	258
	259	/*
	260	* Read the current TLS pointer from tpidr_el0 as it may be
	261	* out-of-sync with the saved value.
	262	*/
	263	asm("mrs %0, tpidr_el0" : "=r" (*task_user_tls(p)));
	264
	265	if (stack_start) {
	266	if (is_compat_thread(task_thread_info(p)))
e0fd18ce	267	childregs->compat_sp = stack_start;
d00a3810 WD	268	/* 16-byte aligned stack mandatory on AArch64 */
	269	else if (stack_start & 15)
	270	return -EINVAL;
	271	else
e0fd18ce	272	childregs->sp = stack_start;
c34501d2	273	}
d00a3810	274
b3901d54	275	/*
c34501d2 CM	276	* If a TLS pointer was passed to clone (4th argument), use it
c34501d2 CM	277	* for the new thread.
b3901d54	278	*/
c34501d2	279	if (clone_flags & CLONE_SETTLS)
d00a3810	280	p->thread.tp_value = childregs->regs[3];
c34501d2 CM	281	} else {
	282	memset(childregs, 0, sizeof(struct pt_regs));
	283	childregs->pstate = PSR_MODE_EL1h;
57f4959b JM	284	if (IS_ENABLED(CONFIG_ARM64_UAO) &&
	285	cpus_have_cap(ARM64_HAS_UAO))
	286	childregs->pstate \|= PSR_UAO_BIT;
c34501d2 CM	287	p->thread.cpu_context.x19 = stack_start;
c34501d2 CM	288	p->thread.cpu_context.x20 = stk_sz;
b3901d54	289	}
b3901d54	290	p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
c34501d2	291	p->thread.cpu_context.sp = (unsigned long)childregs;
b3901d54 CM	292
	293	ptrace_hw_copy_thread(p);
	294
	295	return 0;
	296	}
	297
	298	static void tls_thread_switch(struct task_struct *next)
	299	{
	300	unsigned long tpidr, tpidrro;
	301
d00a3810 WD	302	asm("mrs %0, tpidr_el0" : "=r" (tpidr));
d00a3810 WD	303	*task_user_tls(current) = tpidr;
b3901d54	304
d00a3810 WD	305	tpidr = *task_user_tls(next);
	306	tpidrro = is_compat_thread(task_thread_info(next)) ?
	307	next->thread.tp_value : 0;
b3901d54 CM	308
	309	asm(
	310	" msr tpidr_el0, %0\n"
	311	" msr tpidrro_el0, %1"
	312	: : "r" (tpidr), "r" (tpidrro));
	313	}
	314
57f4959b JM	315	/* Restore the UAO state depending on next's addr_limit */
	316	static void uao_thread_switch(struct task_struct *next)
	317	{
e950631e CM	318	if (IS_ENABLED(CONFIG_ARM64_UAO)) {
	319	if (task_thread_info(next)->addr_limit == KERNEL_DS)
	320	asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
	321	else
	322	asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO));
	323	}
57f4959b JM	324	}
57f4959b JM	325
b3901d54 CM	326	/*
	327	* Thread switching.
	328	*/
	329	struct task_struct __switch_to(struct task_struct prev,
	330	struct task_struct *next)
	331	{
	332	struct task_struct *last;
	333
	334	fpsimd_thread_switch(next);
	335	tls_thread_switch(next);
	336	hw_breakpoint_thread_switch(next);
3325732f	337	contextidr_thread_switch(next);
57f4959b	338	uao_thread_switch(next);
b3901d54	339
5108c67c CM	340	/*
	341	* Complete any pending TLB or cache maintenance on this CPU in case
	342	* the thread migrates to a different CPU.
	343	*/
98f7685e	344	dsb(ish);
b3901d54 CM	345
	346	/* the actual thread switch */
	347	last = cpu_switch_to(prev, next);
	348
	349	return last;
	350	}
	351
b3901d54 CM	352	unsigned long get_wchan(struct task_struct *p)
	353	{
	354	struct stackframe frame;
408c3658	355	unsigned long stack_page;
b3901d54 CM	356	int count = 0;
	357	if (!p \|\| p == current \|\| p->state == TASK_RUNNING)
	358	return 0;
	359
	360	frame.fp = thread_saved_fp(p);
	361	frame.sp = thread_saved_sp(p);
	362	frame.pc = thread_saved_pc(p);
20380bb3 AT	363	#ifdef CONFIG_FUNCTION_GRAPH_TRACER
	364	frame.graph = p->curr_ret_stack;
	365	#endif
408c3658	366	stack_page = (unsigned long)task_stack_page(p);
b3901d54	367	do {
408c3658 KK	368	if (frame.sp < stack_page \|\|
408c3658 KK	369	frame.sp >= stack_page + THREAD_SIZE \|\|
fe13f95b	370	unwind_frame(p, &frame))
b3901d54 CM	371	return 0;
	372	if (!in_sched_functions(frame.pc))
	373	return frame.pc;
	374	} while (count ++ < 16);
	375	return 0;
	376	}
	377
	378	unsigned long arch_align_stack(unsigned long sp)
	379	{
	380	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
	381	sp -= get_random_int() & ~PAGE_MASK;
	382	return sp & ~0xf;
	383	}
	384
	385	static unsigned long randomize_base(unsigned long base)
	386	{
	387	unsigned long range_end = base + (STACK_RND_MASK << PAGE_SHIFT) + 1;
	388	return randomize_range(base, range_end, 0) ? : base;
	389	}
	390
	391	unsigned long arch_randomize_brk(struct mm_struct *mm)
	392	{
	393	return randomize_base(mm->brk);
	394	}