]>
Commit | Line | Data |
---|---|---|
08e875c1 CM |
1 | /* |
2 | * SMP initialisation and IPI support | |
3 | * Based on arch/arm/kernel/smp.c | |
4 | * | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
0f078336 | 20 | #include <linux/acpi.h> |
08e875c1 CM |
21 | #include <linux/delay.h> |
22 | #include <linux/init.h> | |
23 | #include <linux/spinlock.h> | |
68e21be2 | 24 | #include <linux/sched/mm.h> |
ef8bd77f | 25 | #include <linux/sched/hotplug.h> |
68db0cf1 | 26 | #include <linux/sched/task_stack.h> |
08e875c1 CM |
27 | #include <linux/interrupt.h> |
28 | #include <linux/cache.h> | |
29 | #include <linux/profile.h> | |
30 | #include <linux/errno.h> | |
31 | #include <linux/mm.h> | |
32 | #include <linux/err.h> | |
33 | #include <linux/cpu.h> | |
34 | #include <linux/smp.h> | |
35 | #include <linux/seq_file.h> | |
36 | #include <linux/irq.h> | |
37 | #include <linux/percpu.h> | |
38 | #include <linux/clockchips.h> | |
39 | #include <linux/completion.h> | |
40 | #include <linux/of.h> | |
eb631bb5 | 41 | #include <linux/irq_work.h> |
08e875c1 | 42 | |
e039ee4e | 43 | #include <asm/alternative.h> |
08e875c1 CM |
44 | #include <asm/atomic.h> |
45 | #include <asm/cacheflush.h> | |
df857416 | 46 | #include <asm/cpu.h> |
08e875c1 | 47 | #include <asm/cputype.h> |
cd1aebf5 | 48 | #include <asm/cpu_ops.h> |
08e875c1 | 49 | #include <asm/mmu_context.h> |
1a2db300 | 50 | #include <asm/numa.h> |
08e875c1 CM |
51 | #include <asm/pgtable.h> |
52 | #include <asm/pgalloc.h> | |
53 | #include <asm/processor.h> | |
4c7aa002 | 54 | #include <asm/smp_plat.h> |
08e875c1 CM |
55 | #include <asm/sections.h> |
56 | #include <asm/tlbflush.h> | |
57 | #include <asm/ptrace.h> | |
377bcff9 | 58 | #include <asm/virt.h> |
08e875c1 | 59 | |
45ed695a NP |
60 | #define CREATE_TRACE_POINTS |
61 | #include <trace/events/ipi.h> | |
62 | ||
57c82954 MR |
63 | DEFINE_PER_CPU_READ_MOSTLY(int, cpu_number); |
64 | EXPORT_PER_CPU_SYMBOL(cpu_number); | |
65 | ||
08e875c1 CM |
66 | /* |
67 | * as from 2.5, kernels no longer have an init_tasks structure | |
68 | * so we need some other way of telling a new secondary core | |
69 | * where to place its SVC stack | |
70 | */ | |
71 | struct secondary_data secondary_data; | |
bb905274 SP |
72 | /* Number of CPUs which aren't online, but looping in kernel text. */ |
73 | int cpus_stuck_in_kernel; | |
08e875c1 CM |
74 | |
75 | enum ipi_msg_type { | |
76 | IPI_RESCHEDULE, | |
77 | IPI_CALL_FUNC, | |
08e875c1 | 78 | IPI_CPU_STOP, |
1f85008e | 79 | IPI_TIMER, |
eb631bb5 | 80 | IPI_IRQ_WORK, |
5e89c55e | 81 | IPI_WAKEUP |
08e875c1 CM |
82 | }; |
83 | ||
ac1ad20f SP |
84 | #ifdef CONFIG_ARM64_VHE |
85 | ||
86 | /* Whether the boot CPU is running in HYP mode or not*/ | |
87 | static bool boot_cpu_hyp_mode; | |
88 | ||
89 | static inline void save_boot_cpu_run_el(void) | |
90 | { | |
91 | boot_cpu_hyp_mode = is_kernel_in_hyp_mode(); | |
92 | } | |
93 | ||
94 | static inline bool is_boot_cpu_in_hyp_mode(void) | |
95 | { | |
96 | return boot_cpu_hyp_mode; | |
97 | } | |
98 | ||
99 | /* | |
100 | * Verify that a secondary CPU is running the kernel at the same | |
101 | * EL as that of the boot CPU. | |
102 | */ | |
103 | void verify_cpu_run_el(void) | |
104 | { | |
105 | bool in_el2 = is_kernel_in_hyp_mode(); | |
106 | bool boot_cpu_el2 = is_boot_cpu_in_hyp_mode(); | |
107 | ||
108 | if (in_el2 ^ boot_cpu_el2) { | |
109 | pr_crit("CPU%d: mismatched Exception Level(EL%d) with boot CPU(EL%d)\n", | |
110 | smp_processor_id(), | |
111 | in_el2 ? 2 : 1, | |
112 | boot_cpu_el2 ? 2 : 1); | |
113 | cpu_panic_kernel(); | |
114 | } | |
115 | } | |
116 | ||
117 | #else | |
118 | static inline void save_boot_cpu_run_el(void) {} | |
119 | #endif | |
120 | ||
bb905274 SP |
121 | #ifdef CONFIG_HOTPLUG_CPU |
122 | static int op_cpu_kill(unsigned int cpu); | |
123 | #else | |
124 | static inline int op_cpu_kill(unsigned int cpu) | |
125 | { | |
126 | return -ENOSYS; | |
127 | } | |
128 | #endif | |
129 | ||
130 | ||
08e875c1 CM |
131 | /* |
132 | * Boot a secondary CPU, and assign it the specified idle task. | |
133 | * This also gives us the initial stack to use for this CPU. | |
134 | */ | |
b8c6453a | 135 | static int boot_secondary(unsigned int cpu, struct task_struct *idle) |
08e875c1 | 136 | { |
652af899 MR |
137 | if (cpu_ops[cpu]->cpu_boot) |
138 | return cpu_ops[cpu]->cpu_boot(cpu); | |
08e875c1 | 139 | |
652af899 | 140 | return -EOPNOTSUPP; |
08e875c1 CM |
141 | } |
142 | ||
143 | static DECLARE_COMPLETION(cpu_running); | |
144 | ||
b8c6453a | 145 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
08e875c1 CM |
146 | { |
147 | int ret; | |
bb905274 | 148 | long status; |
08e875c1 CM |
149 | |
150 | /* | |
151 | * We need to tell the secondary core where to find its stack and the | |
152 | * page tables. | |
153 | */ | |
c02433dd | 154 | secondary_data.task = idle; |
08e875c1 | 155 | secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; |
bb905274 | 156 | update_cpu_boot_status(CPU_MMU_OFF); |
08e875c1 CM |
157 | __flush_dcache_area(&secondary_data, sizeof(secondary_data)); |
158 | ||
159 | /* | |
160 | * Now bring the CPU into our world. | |
161 | */ | |
162 | ret = boot_secondary(cpu, idle); | |
163 | if (ret == 0) { | |
164 | /* | |
165 | * CPU was successfully started, wait for it to come online or | |
166 | * time out. | |
167 | */ | |
168 | wait_for_completion_timeout(&cpu_running, | |
169 | msecs_to_jiffies(1000)); | |
170 | ||
171 | if (!cpu_online(cpu)) { | |
172 | pr_crit("CPU%u: failed to come online\n", cpu); | |
173 | ret = -EIO; | |
174 | } | |
175 | } else { | |
176 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
177 | } | |
178 | ||
c02433dd | 179 | secondary_data.task = NULL; |
08e875c1 | 180 | secondary_data.stack = NULL; |
bb905274 SP |
181 | status = READ_ONCE(secondary_data.status); |
182 | if (ret && status) { | |
183 | ||
184 | if (status == CPU_MMU_OFF) | |
185 | status = READ_ONCE(__early_cpu_boot_status); | |
186 | ||
187 | switch (status) { | |
188 | default: | |
189 | pr_err("CPU%u: failed in unknown state : 0x%lx\n", | |
190 | cpu, status); | |
191 | break; | |
192 | case CPU_KILL_ME: | |
193 | if (!op_cpu_kill(cpu)) { | |
194 | pr_crit("CPU%u: died during early boot\n", cpu); | |
195 | break; | |
196 | } | |
197 | /* Fall through */ | |
198 | pr_crit("CPU%u: may not have shut down cleanly\n", cpu); | |
199 | case CPU_STUCK_IN_KERNEL: | |
200 | pr_crit("CPU%u: is stuck in kernel\n", cpu); | |
201 | cpus_stuck_in_kernel++; | |
202 | break; | |
203 | case CPU_PANIC_KERNEL: | |
204 | panic("CPU%u detected unsupported configuration\n", cpu); | |
205 | } | |
206 | } | |
08e875c1 CM |
207 | |
208 | return ret; | |
209 | } | |
210 | ||
211 | /* | |
212 | * This is the secondary CPU boot entry. We're using this CPUs | |
213 | * idle thread stack, but a set of temporary page tables. | |
214 | */ | |
b8c6453a | 215 | asmlinkage void secondary_start_kernel(void) |
08e875c1 CM |
216 | { |
217 | struct mm_struct *mm = &init_mm; | |
580efaa7 MR |
218 | unsigned int cpu; |
219 | ||
220 | cpu = task_cpu(current); | |
221 | set_my_cpu_offset(per_cpu_offset(cpu)); | |
08e875c1 | 222 | |
08e875c1 CM |
223 | /* |
224 | * All kernel threads share the same mm context; grab a | |
225 | * reference and switch to it. | |
226 | */ | |
f1f10076 | 227 | mmgrab(mm); |
08e875c1 | 228 | current->active_mm = mm; |
08e875c1 CM |
229 | |
230 | /* | |
231 | * TTBR0 is only used for the identity mapping at this stage. Make it | |
232 | * point to zero page to avoid speculatively fetching new entries. | |
233 | */ | |
9e8e865b | 234 | cpu_uninstall_idmap(); |
08e875c1 CM |
235 | |
236 | preempt_disable(); | |
237 | trace_hardirqs_off(); | |
238 | ||
dbb4e152 SP |
239 | /* |
240 | * If the system has established the capabilities, make sure | |
241 | * this CPU ticks all of those. If it doesn't, the CPU will | |
242 | * fail to come online. | |
243 | */ | |
c47a1900 | 244 | check_local_cpu_capabilities(); |
dbb4e152 | 245 | |
652af899 MR |
246 | if (cpu_ops[cpu]->cpu_postboot) |
247 | cpu_ops[cpu]->cpu_postboot(); | |
08e875c1 | 248 | |
df857416 MR |
249 | /* |
250 | * Log the CPU info before it is marked online and might get read. | |
251 | */ | |
252 | cpuinfo_store_cpu(); | |
253 | ||
7ade67b5 MZ |
254 | /* |
255 | * Enable GIC and timers. | |
256 | */ | |
257 | notify_cpu_starting(cpu); | |
258 | ||
c18df0ad | 259 | store_cpu_topology(cpu); |
f6e763b9 | 260 | |
08e875c1 CM |
261 | /* |
262 | * OK, now it's safe to let the boot CPU continue. Wait for | |
263 | * the CPU migration code to notice that the CPU is online | |
264 | * before we continue. | |
265 | */ | |
64f17818 SP |
266 | pr_info("CPU%u: Booted secondary processor [%08x]\n", |
267 | cpu, read_cpuid_id()); | |
bb905274 | 268 | update_cpu_boot_status(CPU_BOOT_SUCCESS); |
08e875c1 | 269 | set_cpu_online(cpu, true); |
b3770b32 | 270 | complete(&cpu_running); |
08e875c1 | 271 | |
53ae3acd | 272 | local_irq_enable(); |
b3bf6aa7 | 273 | local_async_enable(); |
53ae3acd | 274 | |
08e875c1 CM |
275 | /* |
276 | * OK, it's off to the idle thread for us | |
277 | */ | |
fc6d73d6 | 278 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
08e875c1 CM |
279 | } |
280 | ||
9327e2c6 MR |
281 | #ifdef CONFIG_HOTPLUG_CPU |
282 | static int op_cpu_disable(unsigned int cpu) | |
283 | { | |
284 | /* | |
285 | * If we don't have a cpu_die method, abort before we reach the point | |
286 | * of no return. CPU0 may not have an cpu_ops, so test for it. | |
287 | */ | |
288 | if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die) | |
289 | return -EOPNOTSUPP; | |
290 | ||
291 | /* | |
292 | * We may need to abort a hot unplug for some other mechanism-specific | |
293 | * reason. | |
294 | */ | |
295 | if (cpu_ops[cpu]->cpu_disable) | |
296 | return cpu_ops[cpu]->cpu_disable(cpu); | |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
301 | /* | |
302 | * __cpu_disable runs on the processor to be shutdown. | |
303 | */ | |
304 | int __cpu_disable(void) | |
305 | { | |
306 | unsigned int cpu = smp_processor_id(); | |
307 | int ret; | |
308 | ||
309 | ret = op_cpu_disable(cpu); | |
310 | if (ret) | |
311 | return ret; | |
312 | ||
313 | /* | |
314 | * Take this CPU offline. Once we clear this, we can't return, | |
315 | * and we must not schedule until we're ready to give up the cpu. | |
316 | */ | |
317 | set_cpu_online(cpu, false); | |
318 | ||
319 | /* | |
320 | * OK - migrate IRQs away from this CPU | |
321 | */ | |
217d453d YY |
322 | irq_migrate_all_off_this_cpu(); |
323 | ||
9327e2c6 MR |
324 | return 0; |
325 | } | |
326 | ||
c814ca02 AC |
327 | static int op_cpu_kill(unsigned int cpu) |
328 | { | |
329 | /* | |
330 | * If we have no means of synchronising with the dying CPU, then assume | |
331 | * that it is really dead. We can only wait for an arbitrary length of | |
332 | * time and hope that it's dead, so let's skip the wait and just hope. | |
333 | */ | |
334 | if (!cpu_ops[cpu]->cpu_kill) | |
6b99c68c | 335 | return 0; |
c814ca02 AC |
336 | |
337 | return cpu_ops[cpu]->cpu_kill(cpu); | |
338 | } | |
339 | ||
9327e2c6 MR |
340 | /* |
341 | * called on the thread which is asking for a CPU to be shutdown - | |
342 | * waits until shutdown has completed, or it is timed out. | |
343 | */ | |
344 | void __cpu_die(unsigned int cpu) | |
345 | { | |
6b99c68c MR |
346 | int err; |
347 | ||
05981277 | 348 | if (!cpu_wait_death(cpu, 5)) { |
9327e2c6 MR |
349 | pr_crit("CPU%u: cpu didn't die\n", cpu); |
350 | return; | |
351 | } | |
352 | pr_notice("CPU%u: shutdown\n", cpu); | |
c814ca02 AC |
353 | |
354 | /* | |
355 | * Now that the dying CPU is beyond the point of no return w.r.t. | |
356 | * in-kernel synchronisation, try to get the firwmare to help us to | |
357 | * verify that it has really left the kernel before we consider | |
358 | * clobbering anything it might still be using. | |
359 | */ | |
6b99c68c MR |
360 | err = op_cpu_kill(cpu); |
361 | if (err) | |
362 | pr_warn("CPU%d may not have shut down cleanly: %d\n", | |
363 | cpu, err); | |
9327e2c6 MR |
364 | } |
365 | ||
366 | /* | |
367 | * Called from the idle thread for the CPU which has been shutdown. | |
368 | * | |
369 | * Note that we disable IRQs here, but do not re-enable them | |
370 | * before returning to the caller. This is also the behaviour | |
371 | * of the other hotplug-cpu capable cores, so presumably coming | |
372 | * out of idle fixes this. | |
373 | */ | |
374 | void cpu_die(void) | |
375 | { | |
376 | unsigned int cpu = smp_processor_id(); | |
377 | ||
378 | idle_task_exit(); | |
379 | ||
380 | local_irq_disable(); | |
381 | ||
382 | /* Tell __cpu_die() that this CPU is now safe to dispose of */ | |
05981277 | 383 | (void)cpu_report_death(); |
9327e2c6 MR |
384 | |
385 | /* | |
386 | * Actually shutdown the CPU. This must never fail. The specific hotplug | |
387 | * mechanism must perform all required cache maintenance to ensure that | |
388 | * no dirty lines are lost in the process of shutting down the CPU. | |
389 | */ | |
390 | cpu_ops[cpu]->cpu_die(cpu); | |
391 | ||
392 | BUG(); | |
393 | } | |
394 | #endif | |
395 | ||
fce6361f SP |
396 | /* |
397 | * Kill the calling secondary CPU, early in bringup before it is turned | |
398 | * online. | |
399 | */ | |
400 | void cpu_die_early(void) | |
401 | { | |
402 | int cpu = smp_processor_id(); | |
403 | ||
404 | pr_crit("CPU%d: will not boot\n", cpu); | |
405 | ||
406 | /* Mark this CPU absent */ | |
407 | set_cpu_present(cpu, 0); | |
408 | ||
409 | #ifdef CONFIG_HOTPLUG_CPU | |
bb905274 | 410 | update_cpu_boot_status(CPU_KILL_ME); |
fce6361f SP |
411 | /* Check if we can park ourselves */ |
412 | if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die) | |
413 | cpu_ops[cpu]->cpu_die(cpu); | |
414 | #endif | |
bb905274 | 415 | update_cpu_boot_status(CPU_STUCK_IN_KERNEL); |
fce6361f SP |
416 | |
417 | cpu_park_loop(); | |
418 | } | |
419 | ||
377bcff9 JR |
420 | static void __init hyp_mode_check(void) |
421 | { | |
422 | if (is_hyp_mode_available()) | |
423 | pr_info("CPU: All CPU(s) started at EL2\n"); | |
424 | else if (is_hyp_mode_mismatched()) | |
425 | WARN_TAINT(1, TAINT_CPU_OUT_OF_SPEC, | |
426 | "CPU: CPUs started in inconsistent modes"); | |
427 | else | |
428 | pr_info("CPU: All CPU(s) started at EL1\n"); | |
429 | } | |
430 | ||
08e875c1 CM |
431 | void __init smp_cpus_done(unsigned int max_cpus) |
432 | { | |
326b16db | 433 | pr_info("SMP: Total of %d processors activated.\n", num_online_cpus()); |
3a75578e | 434 | setup_cpu_features(); |
377bcff9 JR |
435 | hyp_mode_check(); |
436 | apply_alternatives_all(); | |
08e875c1 CM |
437 | } |
438 | ||
439 | void __init smp_prepare_boot_cpu(void) | |
440 | { | |
9113c2aa | 441 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
efd9e03f CM |
442 | /* |
443 | * Initialise the static keys early as they may be enabled by the | |
444 | * cpufeature code. | |
445 | */ | |
446 | jump_label_init(); | |
4b998ff1 | 447 | cpuinfo_store_boot_cpu(); |
ac1ad20f | 448 | save_boot_cpu_run_el(); |
c47a1900 SP |
449 | /* |
450 | * Run the errata work around checks on the boot CPU, once we have | |
451 | * initialised the cpu feature infrastructure from | |
452 | * cpuinfo_store_boot_cpu() above. | |
453 | */ | |
454 | update_cpu_errata_workarounds(); | |
08e875c1 CM |
455 | } |
456 | ||
0f078336 LP |
457 | static u64 __init of_get_cpu_mpidr(struct device_node *dn) |
458 | { | |
459 | const __be32 *cell; | |
460 | u64 hwid; | |
461 | ||
462 | /* | |
463 | * A cpu node with missing "reg" property is | |
464 | * considered invalid to build a cpu_logical_map | |
465 | * entry. | |
466 | */ | |
467 | cell = of_get_property(dn, "reg", NULL); | |
468 | if (!cell) { | |
469 | pr_err("%s: missing reg property\n", dn->full_name); | |
470 | return INVALID_HWID; | |
471 | } | |
472 | ||
473 | hwid = of_read_number(cell, of_n_addr_cells(dn)); | |
474 | /* | |
475 | * Non affinity bits must be set to 0 in the DT | |
476 | */ | |
477 | if (hwid & ~MPIDR_HWID_BITMASK) { | |
478 | pr_err("%s: invalid reg property\n", dn->full_name); | |
479 | return INVALID_HWID; | |
480 | } | |
481 | return hwid; | |
482 | } | |
483 | ||
484 | /* | |
485 | * Duplicate MPIDRs are a recipe for disaster. Scan all initialized | |
486 | * entries and check for duplicates. If any is found just ignore the | |
487 | * cpu. cpu_logical_map was initialized to INVALID_HWID to avoid | |
488 | * matching valid MPIDR values. | |
489 | */ | |
490 | static bool __init is_mpidr_duplicate(unsigned int cpu, u64 hwid) | |
491 | { | |
492 | unsigned int i; | |
493 | ||
494 | for (i = 1; (i < cpu) && (i < NR_CPUS); i++) | |
495 | if (cpu_logical_map(i) == hwid) | |
496 | return true; | |
497 | return false; | |
498 | } | |
499 | ||
819a8826 LP |
500 | /* |
501 | * Initialize cpu operations for a logical cpu and | |
502 | * set it in the possible mask on success | |
503 | */ | |
504 | static int __init smp_cpu_setup(int cpu) | |
505 | { | |
506 | if (cpu_read_ops(cpu)) | |
507 | return -ENODEV; | |
508 | ||
509 | if (cpu_ops[cpu]->cpu_init(cpu)) | |
510 | return -ENODEV; | |
511 | ||
512 | set_cpu_possible(cpu, true); | |
513 | ||
514 | return 0; | |
515 | } | |
516 | ||
0f078336 LP |
517 | static bool bootcpu_valid __initdata; |
518 | static unsigned int cpu_count = 1; | |
519 | ||
520 | #ifdef CONFIG_ACPI | |
521 | /* | |
522 | * acpi_map_gic_cpu_interface - parse processor MADT entry | |
523 | * | |
524 | * Carry out sanity checks on MADT processor entry and initialize | |
525 | * cpu_logical_map on success | |
526 | */ | |
527 | static void __init | |
528 | acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor) | |
529 | { | |
530 | u64 hwid = processor->arm_mpidr; | |
531 | ||
f9058929 HG |
532 | if (!(processor->flags & ACPI_MADT_ENABLED)) { |
533 | pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid); | |
0f078336 LP |
534 | return; |
535 | } | |
536 | ||
f9058929 HG |
537 | if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) { |
538 | pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid); | |
0f078336 LP |
539 | return; |
540 | } | |
541 | ||
542 | if (is_mpidr_duplicate(cpu_count, hwid)) { | |
543 | pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid); | |
544 | return; | |
545 | } | |
546 | ||
547 | /* Check if GICC structure of boot CPU is available in the MADT */ | |
548 | if (cpu_logical_map(0) == hwid) { | |
549 | if (bootcpu_valid) { | |
550 | pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n", | |
551 | hwid); | |
552 | return; | |
553 | } | |
554 | bootcpu_valid = true; | |
baa5567c | 555 | early_map_cpu_to_node(0, acpi_numa_get_nid(0, hwid)); |
0f078336 LP |
556 | return; |
557 | } | |
558 | ||
559 | if (cpu_count >= NR_CPUS) | |
560 | return; | |
561 | ||
562 | /* map the logical cpu id to cpu MPIDR */ | |
563 | cpu_logical_map(cpu_count) = hwid; | |
564 | ||
5e89c55e LP |
565 | /* |
566 | * Set-up the ACPI parking protocol cpu entries | |
567 | * while initializing the cpu_logical_map to | |
568 | * avoid parsing MADT entries multiple times for | |
569 | * nothing (ie a valid cpu_logical_map entry should | |
570 | * contain a valid parking protocol data set to | |
571 | * initialize the cpu if the parking protocol is | |
572 | * the only available enable method). | |
573 | */ | |
574 | acpi_set_mailbox_entry(cpu_count, processor); | |
575 | ||
d8b47fca HG |
576 | early_map_cpu_to_node(cpu_count, acpi_numa_get_nid(cpu_count, hwid)); |
577 | ||
0f078336 LP |
578 | cpu_count++; |
579 | } | |
580 | ||
581 | static int __init | |
582 | acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header, | |
583 | const unsigned long end) | |
584 | { | |
585 | struct acpi_madt_generic_interrupt *processor; | |
586 | ||
587 | processor = (struct acpi_madt_generic_interrupt *)header; | |
99e3e3ae | 588 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
0f078336 LP |
589 | return -EINVAL; |
590 | ||
591 | acpi_table_print_madt_entry(header); | |
592 | ||
593 | acpi_map_gic_cpu_interface(processor); | |
594 | ||
595 | return 0; | |
596 | } | |
597 | #else | |
598 | #define acpi_table_parse_madt(...) do { } while (0) | |
599 | #endif | |
600 | ||
08e875c1 | 601 | /* |
4c7aa002 JM |
602 | * Enumerate the possible CPU set from the device tree and build the |
603 | * cpu logical map array containing MPIDR values related to logical | |
604 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
08e875c1 | 605 | */ |
29b8302b | 606 | static void __init of_parse_and_init_cpus(void) |
08e875c1 | 607 | { |
3d29a9a0 | 608 | struct device_node *dn; |
08e875c1 | 609 | |
3d29a9a0 | 610 | for_each_node_by_type(dn, "cpu") { |
0f078336 | 611 | u64 hwid = of_get_cpu_mpidr(dn); |
4c7aa002 | 612 | |
0f078336 | 613 | if (hwid == INVALID_HWID) |
4c7aa002 | 614 | goto next; |
4c7aa002 | 615 | |
0f078336 LP |
616 | if (is_mpidr_duplicate(cpu_count, hwid)) { |
617 | pr_err("%s: duplicate cpu reg properties in the DT\n", | |
618 | dn->full_name); | |
4c7aa002 JM |
619 | goto next; |
620 | } | |
621 | ||
4c7aa002 JM |
622 | /* |
623 | * The numbering scheme requires that the boot CPU | |
624 | * must be assigned logical id 0. Record it so that | |
625 | * the logical map built from DT is validated and can | |
626 | * be used. | |
627 | */ | |
628 | if (hwid == cpu_logical_map(0)) { | |
629 | if (bootcpu_valid) { | |
630 | pr_err("%s: duplicate boot cpu reg property in DT\n", | |
631 | dn->full_name); | |
632 | goto next; | |
633 | } | |
634 | ||
635 | bootcpu_valid = true; | |
7ba5f605 | 636 | early_map_cpu_to_node(0, of_node_to_nid(dn)); |
4c7aa002 JM |
637 | |
638 | /* | |
639 | * cpu_logical_map has already been | |
640 | * initialized and the boot cpu doesn't need | |
641 | * the enable-method so continue without | |
642 | * incrementing cpu. | |
643 | */ | |
644 | continue; | |
645 | } | |
646 | ||
0f078336 | 647 | if (cpu_count >= NR_CPUS) |
08e875c1 CM |
648 | goto next; |
649 | ||
4c7aa002 | 650 | pr_debug("cpu logical map 0x%llx\n", hwid); |
0f078336 | 651 | cpu_logical_map(cpu_count) = hwid; |
1a2db300 GK |
652 | |
653 | early_map_cpu_to_node(cpu_count, of_node_to_nid(dn)); | |
08e875c1 | 654 | next: |
0f078336 | 655 | cpu_count++; |
08e875c1 | 656 | } |
0f078336 LP |
657 | } |
658 | ||
659 | /* | |
660 | * Enumerate the possible CPU set from the device tree or ACPI and build the | |
661 | * cpu logical map array containing MPIDR values related to logical | |
662 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
663 | */ | |
664 | void __init smp_init_cpus(void) | |
665 | { | |
666 | int i; | |
667 | ||
668 | if (acpi_disabled) | |
669 | of_parse_and_init_cpus(); | |
670 | else | |
671 | /* | |
672 | * do a walk of MADT to determine how many CPUs | |
673 | * we have including disabled CPUs, and get information | |
674 | * we need for SMP init | |
675 | */ | |
676 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
677 | acpi_parse_gic_cpu_interface, 0); | |
08e875c1 | 678 | |
50ee91bd KW |
679 | if (cpu_count > nr_cpu_ids) |
680 | pr_warn("Number of cores (%d) exceeds configured maximum of %d - clipping\n", | |
681 | cpu_count, nr_cpu_ids); | |
4c7aa002 JM |
682 | |
683 | if (!bootcpu_valid) { | |
0f078336 | 684 | pr_err("missing boot CPU MPIDR, not enabling secondaries\n"); |
4c7aa002 JM |
685 | return; |
686 | } | |
687 | ||
688 | /* | |
819a8826 LP |
689 | * We need to set the cpu_logical_map entries before enabling |
690 | * the cpus so that cpu processor description entries (DT cpu nodes | |
691 | * and ACPI MADT entries) can be retrieved by matching the cpu hwid | |
692 | * with entries in cpu_logical_map while initializing the cpus. | |
693 | * If the cpu set-up fails, invalidate the cpu_logical_map entry. | |
4c7aa002 | 694 | */ |
50ee91bd | 695 | for (i = 1; i < nr_cpu_ids; i++) { |
819a8826 LP |
696 | if (cpu_logical_map(i) != INVALID_HWID) { |
697 | if (smp_cpu_setup(i)) | |
698 | cpu_logical_map(i) = INVALID_HWID; | |
699 | } | |
700 | } | |
08e875c1 CM |
701 | } |
702 | ||
703 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
704 | { | |
cd1aebf5 | 705 | int err; |
44dbcc93 | 706 | unsigned int cpu; |
c18df0ad | 707 | unsigned int this_cpu; |
08e875c1 | 708 | |
f6e763b9 MB |
709 | init_cpu_topology(); |
710 | ||
c18df0ad DD |
711 | this_cpu = smp_processor_id(); |
712 | store_cpu_topology(this_cpu); | |
713 | numa_store_cpu_info(this_cpu); | |
f6e763b9 | 714 | |
e75118a7 SP |
715 | /* |
716 | * If UP is mandated by "nosmp" (which implies "maxcpus=0"), don't set | |
717 | * secondary CPUs present. | |
718 | */ | |
719 | if (max_cpus == 0) | |
720 | return; | |
721 | ||
08e875c1 CM |
722 | /* |
723 | * Initialise the present map (which describes the set of CPUs | |
724 | * actually populated at the present time) and release the | |
725 | * secondaries from the bootloader. | |
726 | */ | |
727 | for_each_possible_cpu(cpu) { | |
08e875c1 | 728 | |
57c82954 MR |
729 | per_cpu(cpu_number, cpu) = cpu; |
730 | ||
d329de3f MZ |
731 | if (cpu == smp_processor_id()) |
732 | continue; | |
733 | ||
cd1aebf5 | 734 | if (!cpu_ops[cpu]) |
08e875c1 CM |
735 | continue; |
736 | ||
cd1aebf5 | 737 | err = cpu_ops[cpu]->cpu_prepare(cpu); |
d329de3f MZ |
738 | if (err) |
739 | continue; | |
08e875c1 CM |
740 | |
741 | set_cpu_present(cpu, true); | |
c18df0ad | 742 | numa_store_cpu_info(cpu); |
08e875c1 | 743 | } |
08e875c1 CM |
744 | } |
745 | ||
36310736 | 746 | void (*__smp_cross_call)(const struct cpumask *, unsigned int); |
08e875c1 CM |
747 | |
748 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
749 | { | |
45ed695a | 750 | __smp_cross_call = fn; |
08e875c1 CM |
751 | } |
752 | ||
45ed695a NP |
753 | static const char *ipi_types[NR_IPI] __tracepoint_string = { |
754 | #define S(x,s) [x] = s | |
08e875c1 CM |
755 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), |
756 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
08e875c1 | 757 | S(IPI_CPU_STOP, "CPU stop interrupts"), |
1f85008e | 758 | S(IPI_TIMER, "Timer broadcast interrupts"), |
eb631bb5 | 759 | S(IPI_IRQ_WORK, "IRQ work interrupts"), |
5e89c55e | 760 | S(IPI_WAKEUP, "CPU wake-up interrupts"), |
08e875c1 CM |
761 | }; |
762 | ||
45ed695a NP |
763 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) |
764 | { | |
765 | trace_ipi_raise(target, ipi_types[ipinr]); | |
766 | __smp_cross_call(target, ipinr); | |
767 | } | |
768 | ||
08e875c1 CM |
769 | void show_ipi_list(struct seq_file *p, int prec) |
770 | { | |
771 | unsigned int cpu, i; | |
772 | ||
773 | for (i = 0; i < NR_IPI; i++) { | |
45ed695a | 774 | seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, |
08e875c1 | 775 | prec >= 4 ? " " : ""); |
67317c26 | 776 | for_each_online_cpu(cpu) |
08e875c1 CM |
777 | seq_printf(p, "%10u ", |
778 | __get_irq_stat(cpu, ipi_irqs[i])); | |
779 | seq_printf(p, " %s\n", ipi_types[i]); | |
780 | } | |
781 | } | |
782 | ||
783 | u64 smp_irq_stat_cpu(unsigned int cpu) | |
784 | { | |
785 | u64 sum = 0; | |
786 | int i; | |
787 | ||
788 | for (i = 0; i < NR_IPI; i++) | |
789 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
790 | ||
791 | return sum; | |
792 | } | |
793 | ||
45ed695a NP |
794 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
795 | { | |
796 | smp_cross_call(mask, IPI_CALL_FUNC); | |
797 | } | |
798 | ||
799 | void arch_send_call_function_single_ipi(int cpu) | |
800 | { | |
0aaf0dae | 801 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); |
45ed695a NP |
802 | } |
803 | ||
5e89c55e LP |
804 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
805 | void arch_send_wakeup_ipi_mask(const struct cpumask *mask) | |
806 | { | |
807 | smp_cross_call(mask, IPI_WAKEUP); | |
808 | } | |
809 | #endif | |
810 | ||
45ed695a NP |
811 | #ifdef CONFIG_IRQ_WORK |
812 | void arch_irq_work_raise(void) | |
813 | { | |
814 | if (__smp_cross_call) | |
815 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); | |
816 | } | |
817 | #endif | |
818 | ||
08e875c1 CM |
819 | /* |
820 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
821 | */ | |
822 | static void ipi_cpu_stop(unsigned int cpu) | |
823 | { | |
08e875c1 CM |
824 | set_cpu_online(cpu, false); |
825 | ||
08e875c1 CM |
826 | local_irq_disable(); |
827 | ||
828 | while (1) | |
829 | cpu_relax(); | |
830 | } | |
831 | ||
832 | /* | |
833 | * Main handler for inter-processor interrupts | |
834 | */ | |
835 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
836 | { | |
837 | unsigned int cpu = smp_processor_id(); | |
838 | struct pt_regs *old_regs = set_irq_regs(regs); | |
839 | ||
45ed695a | 840 | if ((unsigned)ipinr < NR_IPI) { |
be081d9b | 841 | trace_ipi_entry_rcuidle(ipi_types[ipinr]); |
45ed695a NP |
842 | __inc_irq_stat(cpu, ipi_irqs[ipinr]); |
843 | } | |
08e875c1 CM |
844 | |
845 | switch (ipinr) { | |
846 | case IPI_RESCHEDULE: | |
847 | scheduler_ipi(); | |
848 | break; | |
849 | ||
850 | case IPI_CALL_FUNC: | |
851 | irq_enter(); | |
852 | generic_smp_call_function_interrupt(); | |
853 | irq_exit(); | |
854 | break; | |
855 | ||
08e875c1 CM |
856 | case IPI_CPU_STOP: |
857 | irq_enter(); | |
858 | ipi_cpu_stop(cpu); | |
859 | irq_exit(); | |
860 | break; | |
861 | ||
1f85008e LP |
862 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
863 | case IPI_TIMER: | |
864 | irq_enter(); | |
865 | tick_receive_broadcast(); | |
866 | irq_exit(); | |
867 | break; | |
868 | #endif | |
869 | ||
eb631bb5 LB |
870 | #ifdef CONFIG_IRQ_WORK |
871 | case IPI_IRQ_WORK: | |
872 | irq_enter(); | |
873 | irq_work_run(); | |
874 | irq_exit(); | |
875 | break; | |
876 | #endif | |
877 | ||
5e89c55e LP |
878 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
879 | case IPI_WAKEUP: | |
880 | WARN_ONCE(!acpi_parking_protocol_valid(cpu), | |
881 | "CPU%u: Wake-up IPI outside the ACPI parking protocol\n", | |
882 | cpu); | |
883 | break; | |
884 | #endif | |
885 | ||
08e875c1 CM |
886 | default: |
887 | pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); | |
888 | break; | |
889 | } | |
45ed695a NP |
890 | |
891 | if ((unsigned)ipinr < NR_IPI) | |
be081d9b | 892 | trace_ipi_exit_rcuidle(ipi_types[ipinr]); |
08e875c1 CM |
893 | set_irq_regs(old_regs); |
894 | } | |
895 | ||
896 | void smp_send_reschedule(int cpu) | |
897 | { | |
898 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); | |
899 | } | |
900 | ||
1f85008e LP |
901 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
902 | void tick_broadcast(const struct cpumask *mask) | |
903 | { | |
904 | smp_cross_call(mask, IPI_TIMER); | |
905 | } | |
906 | #endif | |
907 | ||
08e875c1 CM |
908 | void smp_send_stop(void) |
909 | { | |
910 | unsigned long timeout; | |
911 | ||
912 | if (num_online_cpus() > 1) { | |
913 | cpumask_t mask; | |
914 | ||
915 | cpumask_copy(&mask, cpu_online_mask); | |
434ed7f4 | 916 | cpumask_clear_cpu(smp_processor_id(), &mask); |
08e875c1 | 917 | |
82611c14 JG |
918 | if (system_state == SYSTEM_BOOTING || |
919 | system_state == SYSTEM_RUNNING) | |
920 | pr_crit("SMP: stopping secondary CPUs\n"); | |
08e875c1 CM |
921 | smp_cross_call(&mask, IPI_CPU_STOP); |
922 | } | |
923 | ||
924 | /* Wait up to one second for other CPUs to stop */ | |
925 | timeout = USEC_PER_SEC; | |
926 | while (num_online_cpus() > 1 && timeout--) | |
927 | udelay(1); | |
928 | ||
929 | if (num_online_cpus() > 1) | |
82611c14 JG |
930 | pr_warning("SMP: failed to stop secondary CPUs %*pbl\n", |
931 | cpumask_pr_args(cpu_online_mask)); | |
08e875c1 CM |
932 | } |
933 | ||
934 | /* | |
935 | * not supported here | |
936 | */ | |
937 | int setup_profiling_timer(unsigned int multiplier) | |
938 | { | |
939 | return -EINVAL; | |
940 | } | |
5c492c3f JM |
941 | |
942 | static bool have_cpu_die(void) | |
943 | { | |
944 | #ifdef CONFIG_HOTPLUG_CPU | |
945 | int any_cpu = raw_smp_processor_id(); | |
946 | ||
947 | if (cpu_ops[any_cpu]->cpu_die) | |
948 | return true; | |
949 | #endif | |
950 | return false; | |
951 | } | |
952 | ||
953 | bool cpus_are_stuck_in_kernel(void) | |
954 | { | |
955 | bool smp_spin_tables = (num_possible_cpus() > 1 && !have_cpu_die()); | |
956 | ||
957 | return !!cpus_stuck_in_kernel || smp_spin_tables; | |
958 | } |