]> git.ipfire.org Git - thirdparty/linux.git/blame - arch/arm64/kernel/smp.c
arm64: assembler: introduce ldr_this_cpu
[thirdparty/linux.git] / arch / arm64 / kernel / smp.c
CommitLineData
08e875c1
CM
1/*
2 * SMP initialisation and IPI support
3 * Based on arch/arm/kernel/smp.c
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
0f078336 20#include <linux/acpi.h>
08e875c1
CM
21#include <linux/delay.h>
22#include <linux/init.h>
23#include <linux/spinlock.h>
24#include <linux/sched.h>
25#include <linux/interrupt.h>
26#include <linux/cache.h>
27#include <linux/profile.h>
28#include <linux/errno.h>
29#include <linux/mm.h>
30#include <linux/err.h>
31#include <linux/cpu.h>
32#include <linux/smp.h>
33#include <linux/seq_file.h>
34#include <linux/irq.h>
35#include <linux/percpu.h>
36#include <linux/clockchips.h>
37#include <linux/completion.h>
38#include <linux/of.h>
eb631bb5 39#include <linux/irq_work.h>
08e875c1 40
e039ee4e 41#include <asm/alternative.h>
08e875c1
CM
42#include <asm/atomic.h>
43#include <asm/cacheflush.h>
df857416 44#include <asm/cpu.h>
08e875c1 45#include <asm/cputype.h>
cd1aebf5 46#include <asm/cpu_ops.h>
08e875c1 47#include <asm/mmu_context.h>
1a2db300 48#include <asm/numa.h>
08e875c1
CM
49#include <asm/pgtable.h>
50#include <asm/pgalloc.h>
51#include <asm/processor.h>
4c7aa002 52#include <asm/smp_plat.h>
08e875c1
CM
53#include <asm/sections.h>
54#include <asm/tlbflush.h>
55#include <asm/ptrace.h>
377bcff9 56#include <asm/virt.h>
08e875c1 57
45ed695a
NP
58#define CREATE_TRACE_POINTS
59#include <trace/events/ipi.h>
60
57c82954
MR
61DEFINE_PER_CPU_READ_MOSTLY(int, cpu_number);
62EXPORT_PER_CPU_SYMBOL(cpu_number);
63
08e875c1
CM
64/*
65 * as from 2.5, kernels no longer have an init_tasks structure
66 * so we need some other way of telling a new secondary core
67 * where to place its SVC stack
68 */
69struct secondary_data secondary_data;
bb905274
SP
70/* Number of CPUs which aren't online, but looping in kernel text. */
71int cpus_stuck_in_kernel;
08e875c1
CM
72
73enum ipi_msg_type {
74 IPI_RESCHEDULE,
75 IPI_CALL_FUNC,
08e875c1 76 IPI_CPU_STOP,
1f85008e 77 IPI_TIMER,
eb631bb5 78 IPI_IRQ_WORK,
5e89c55e 79 IPI_WAKEUP
08e875c1
CM
80};
81
ac1ad20f
SP
82#ifdef CONFIG_ARM64_VHE
83
84/* Whether the boot CPU is running in HYP mode or not*/
85static bool boot_cpu_hyp_mode;
86
87static inline void save_boot_cpu_run_el(void)
88{
89 boot_cpu_hyp_mode = is_kernel_in_hyp_mode();
90}
91
92static inline bool is_boot_cpu_in_hyp_mode(void)
93{
94 return boot_cpu_hyp_mode;
95}
96
97/*
98 * Verify that a secondary CPU is running the kernel at the same
99 * EL as that of the boot CPU.
100 */
101void verify_cpu_run_el(void)
102{
103 bool in_el2 = is_kernel_in_hyp_mode();
104 bool boot_cpu_el2 = is_boot_cpu_in_hyp_mode();
105
106 if (in_el2 ^ boot_cpu_el2) {
107 pr_crit("CPU%d: mismatched Exception Level(EL%d) with boot CPU(EL%d)\n",
108 smp_processor_id(),
109 in_el2 ? 2 : 1,
110 boot_cpu_el2 ? 2 : 1);
111 cpu_panic_kernel();
112 }
113}
114
115#else
116static inline void save_boot_cpu_run_el(void) {}
117#endif
118
bb905274
SP
119#ifdef CONFIG_HOTPLUG_CPU
120static int op_cpu_kill(unsigned int cpu);
121#else
122static inline int op_cpu_kill(unsigned int cpu)
123{
124 return -ENOSYS;
125}
126#endif
127
128
08e875c1
CM
129/*
130 * Boot a secondary CPU, and assign it the specified idle task.
131 * This also gives us the initial stack to use for this CPU.
132 */
b8c6453a 133static int boot_secondary(unsigned int cpu, struct task_struct *idle)
08e875c1 134{
652af899
MR
135 if (cpu_ops[cpu]->cpu_boot)
136 return cpu_ops[cpu]->cpu_boot(cpu);
08e875c1 137
652af899 138 return -EOPNOTSUPP;
08e875c1
CM
139}
140
141static DECLARE_COMPLETION(cpu_running);
142
b8c6453a 143int __cpu_up(unsigned int cpu, struct task_struct *idle)
08e875c1
CM
144{
145 int ret;
bb905274 146 long status;
08e875c1
CM
147
148 /*
149 * We need to tell the secondary core where to find its stack and the
150 * page tables.
151 */
152 secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
bb905274 153 update_cpu_boot_status(CPU_MMU_OFF);
08e875c1
CM
154 __flush_dcache_area(&secondary_data, sizeof(secondary_data));
155
156 /*
157 * Now bring the CPU into our world.
158 */
159 ret = boot_secondary(cpu, idle);
160 if (ret == 0) {
161 /*
162 * CPU was successfully started, wait for it to come online or
163 * time out.
164 */
165 wait_for_completion_timeout(&cpu_running,
166 msecs_to_jiffies(1000));
167
168 if (!cpu_online(cpu)) {
169 pr_crit("CPU%u: failed to come online\n", cpu);
170 ret = -EIO;
171 }
172 } else {
173 pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
174 }
175
176 secondary_data.stack = NULL;
bb905274
SP
177 status = READ_ONCE(secondary_data.status);
178 if (ret && status) {
179
180 if (status == CPU_MMU_OFF)
181 status = READ_ONCE(__early_cpu_boot_status);
182
183 switch (status) {
184 default:
185 pr_err("CPU%u: failed in unknown state : 0x%lx\n",
186 cpu, status);
187 break;
188 case CPU_KILL_ME:
189 if (!op_cpu_kill(cpu)) {
190 pr_crit("CPU%u: died during early boot\n", cpu);
191 break;
192 }
193 /* Fall through */
194 pr_crit("CPU%u: may not have shut down cleanly\n", cpu);
195 case CPU_STUCK_IN_KERNEL:
196 pr_crit("CPU%u: is stuck in kernel\n", cpu);
197 cpus_stuck_in_kernel++;
198 break;
199 case CPU_PANIC_KERNEL:
200 panic("CPU%u detected unsupported configuration\n", cpu);
201 }
202 }
08e875c1
CM
203
204 return ret;
205}
206
207/*
208 * This is the secondary CPU boot entry. We're using this CPUs
209 * idle thread stack, but a set of temporary page tables.
210 */
b8c6453a 211asmlinkage void secondary_start_kernel(void)
08e875c1
CM
212{
213 struct mm_struct *mm = &init_mm;
580efaa7
MR
214 unsigned int cpu;
215
216 cpu = task_cpu(current);
217 set_my_cpu_offset(per_cpu_offset(cpu));
08e875c1 218
08e875c1
CM
219 /*
220 * All kernel threads share the same mm context; grab a
221 * reference and switch to it.
222 */
223 atomic_inc(&mm->mm_count);
224 current->active_mm = mm;
08e875c1
CM
225
226 /*
227 * TTBR0 is only used for the identity mapping at this stage. Make it
228 * point to zero page to avoid speculatively fetching new entries.
229 */
9e8e865b 230 cpu_uninstall_idmap();
08e875c1
CM
231
232 preempt_disable();
233 trace_hardirqs_off();
234
dbb4e152
SP
235 /*
236 * If the system has established the capabilities, make sure
237 * this CPU ticks all of those. If it doesn't, the CPU will
238 * fail to come online.
239 */
c47a1900 240 check_local_cpu_capabilities();
dbb4e152 241
652af899
MR
242 if (cpu_ops[cpu]->cpu_postboot)
243 cpu_ops[cpu]->cpu_postboot();
08e875c1 244
df857416
MR
245 /*
246 * Log the CPU info before it is marked online and might get read.
247 */
248 cpuinfo_store_cpu();
249
7ade67b5
MZ
250 /*
251 * Enable GIC and timers.
252 */
253 notify_cpu_starting(cpu);
254
c18df0ad 255 store_cpu_topology(cpu);
f6e763b9 256
08e875c1
CM
257 /*
258 * OK, now it's safe to let the boot CPU continue. Wait for
259 * the CPU migration code to notice that the CPU is online
260 * before we continue.
261 */
64f17818
SP
262 pr_info("CPU%u: Booted secondary processor [%08x]\n",
263 cpu, read_cpuid_id());
bb905274 264 update_cpu_boot_status(CPU_BOOT_SUCCESS);
08e875c1 265 set_cpu_online(cpu, true);
b3770b32 266 complete(&cpu_running);
08e875c1 267
53ae3acd 268 local_irq_enable();
b3bf6aa7 269 local_async_enable();
53ae3acd 270
08e875c1
CM
271 /*
272 * OK, it's off to the idle thread for us
273 */
fc6d73d6 274 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
08e875c1
CM
275}
276
9327e2c6
MR
277#ifdef CONFIG_HOTPLUG_CPU
278static int op_cpu_disable(unsigned int cpu)
279{
280 /*
281 * If we don't have a cpu_die method, abort before we reach the point
282 * of no return. CPU0 may not have an cpu_ops, so test for it.
283 */
284 if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die)
285 return -EOPNOTSUPP;
286
287 /*
288 * We may need to abort a hot unplug for some other mechanism-specific
289 * reason.
290 */
291 if (cpu_ops[cpu]->cpu_disable)
292 return cpu_ops[cpu]->cpu_disable(cpu);
293
294 return 0;
295}
296
297/*
298 * __cpu_disable runs on the processor to be shutdown.
299 */
300int __cpu_disable(void)
301{
302 unsigned int cpu = smp_processor_id();
303 int ret;
304
305 ret = op_cpu_disable(cpu);
306 if (ret)
307 return ret;
308
309 /*
310 * Take this CPU offline. Once we clear this, we can't return,
311 * and we must not schedule until we're ready to give up the cpu.
312 */
313 set_cpu_online(cpu, false);
314
315 /*
316 * OK - migrate IRQs away from this CPU
317 */
217d453d
YY
318 irq_migrate_all_off_this_cpu();
319
9327e2c6
MR
320 return 0;
321}
322
c814ca02
AC
323static int op_cpu_kill(unsigned int cpu)
324{
325 /*
326 * If we have no means of synchronising with the dying CPU, then assume
327 * that it is really dead. We can only wait for an arbitrary length of
328 * time and hope that it's dead, so let's skip the wait and just hope.
329 */
330 if (!cpu_ops[cpu]->cpu_kill)
6b99c68c 331 return 0;
c814ca02
AC
332
333 return cpu_ops[cpu]->cpu_kill(cpu);
334}
335
9327e2c6
MR
336/*
337 * called on the thread which is asking for a CPU to be shutdown -
338 * waits until shutdown has completed, or it is timed out.
339 */
340void __cpu_die(unsigned int cpu)
341{
6b99c68c
MR
342 int err;
343
05981277 344 if (!cpu_wait_death(cpu, 5)) {
9327e2c6
MR
345 pr_crit("CPU%u: cpu didn't die\n", cpu);
346 return;
347 }
348 pr_notice("CPU%u: shutdown\n", cpu);
c814ca02
AC
349
350 /*
351 * Now that the dying CPU is beyond the point of no return w.r.t.
352 * in-kernel synchronisation, try to get the firwmare to help us to
353 * verify that it has really left the kernel before we consider
354 * clobbering anything it might still be using.
355 */
6b99c68c
MR
356 err = op_cpu_kill(cpu);
357 if (err)
358 pr_warn("CPU%d may not have shut down cleanly: %d\n",
359 cpu, err);
9327e2c6
MR
360}
361
362/*
363 * Called from the idle thread for the CPU which has been shutdown.
364 *
365 * Note that we disable IRQs here, but do not re-enable them
366 * before returning to the caller. This is also the behaviour
367 * of the other hotplug-cpu capable cores, so presumably coming
368 * out of idle fixes this.
369 */
370void cpu_die(void)
371{
372 unsigned int cpu = smp_processor_id();
373
374 idle_task_exit();
375
376 local_irq_disable();
377
378 /* Tell __cpu_die() that this CPU is now safe to dispose of */
05981277 379 (void)cpu_report_death();
9327e2c6
MR
380
381 /*
382 * Actually shutdown the CPU. This must never fail. The specific hotplug
383 * mechanism must perform all required cache maintenance to ensure that
384 * no dirty lines are lost in the process of shutting down the CPU.
385 */
386 cpu_ops[cpu]->cpu_die(cpu);
387
388 BUG();
389}
390#endif
391
fce6361f
SP
392/*
393 * Kill the calling secondary CPU, early in bringup before it is turned
394 * online.
395 */
396void cpu_die_early(void)
397{
398 int cpu = smp_processor_id();
399
400 pr_crit("CPU%d: will not boot\n", cpu);
401
402 /* Mark this CPU absent */
403 set_cpu_present(cpu, 0);
404
405#ifdef CONFIG_HOTPLUG_CPU
bb905274 406 update_cpu_boot_status(CPU_KILL_ME);
fce6361f
SP
407 /* Check if we can park ourselves */
408 if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die)
409 cpu_ops[cpu]->cpu_die(cpu);
410#endif
bb905274 411 update_cpu_boot_status(CPU_STUCK_IN_KERNEL);
fce6361f
SP
412
413 cpu_park_loop();
414}
415
377bcff9
JR
416static void __init hyp_mode_check(void)
417{
418 if (is_hyp_mode_available())
419 pr_info("CPU: All CPU(s) started at EL2\n");
420 else if (is_hyp_mode_mismatched())
421 WARN_TAINT(1, TAINT_CPU_OUT_OF_SPEC,
422 "CPU: CPUs started in inconsistent modes");
423 else
424 pr_info("CPU: All CPU(s) started at EL1\n");
425}
426
08e875c1
CM
427void __init smp_cpus_done(unsigned int max_cpus)
428{
326b16db 429 pr_info("SMP: Total of %d processors activated.\n", num_online_cpus());
3a75578e 430 setup_cpu_features();
377bcff9
JR
431 hyp_mode_check();
432 apply_alternatives_all();
08e875c1
CM
433}
434
435void __init smp_prepare_boot_cpu(void)
436{
9113c2aa 437 set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
efd9e03f
CM
438 /*
439 * Initialise the static keys early as they may be enabled by the
440 * cpufeature code.
441 */
442 jump_label_init();
4b998ff1 443 cpuinfo_store_boot_cpu();
ac1ad20f 444 save_boot_cpu_run_el();
c47a1900
SP
445 /*
446 * Run the errata work around checks on the boot CPU, once we have
447 * initialised the cpu feature infrastructure from
448 * cpuinfo_store_boot_cpu() above.
449 */
450 update_cpu_errata_workarounds();
08e875c1
CM
451}
452
0f078336
LP
453static u64 __init of_get_cpu_mpidr(struct device_node *dn)
454{
455 const __be32 *cell;
456 u64 hwid;
457
458 /*
459 * A cpu node with missing "reg" property is
460 * considered invalid to build a cpu_logical_map
461 * entry.
462 */
463 cell = of_get_property(dn, "reg", NULL);
464 if (!cell) {
465 pr_err("%s: missing reg property\n", dn->full_name);
466 return INVALID_HWID;
467 }
468
469 hwid = of_read_number(cell, of_n_addr_cells(dn));
470 /*
471 * Non affinity bits must be set to 0 in the DT
472 */
473 if (hwid & ~MPIDR_HWID_BITMASK) {
474 pr_err("%s: invalid reg property\n", dn->full_name);
475 return INVALID_HWID;
476 }
477 return hwid;
478}
479
480/*
481 * Duplicate MPIDRs are a recipe for disaster. Scan all initialized
482 * entries and check for duplicates. If any is found just ignore the
483 * cpu. cpu_logical_map was initialized to INVALID_HWID to avoid
484 * matching valid MPIDR values.
485 */
486static bool __init is_mpidr_duplicate(unsigned int cpu, u64 hwid)
487{
488 unsigned int i;
489
490 for (i = 1; (i < cpu) && (i < NR_CPUS); i++)
491 if (cpu_logical_map(i) == hwid)
492 return true;
493 return false;
494}
495
819a8826
LP
496/*
497 * Initialize cpu operations for a logical cpu and
498 * set it in the possible mask on success
499 */
500static int __init smp_cpu_setup(int cpu)
501{
502 if (cpu_read_ops(cpu))
503 return -ENODEV;
504
505 if (cpu_ops[cpu]->cpu_init(cpu))
506 return -ENODEV;
507
508 set_cpu_possible(cpu, true);
509
510 return 0;
511}
512
0f078336
LP
513static bool bootcpu_valid __initdata;
514static unsigned int cpu_count = 1;
515
516#ifdef CONFIG_ACPI
517/*
518 * acpi_map_gic_cpu_interface - parse processor MADT entry
519 *
520 * Carry out sanity checks on MADT processor entry and initialize
521 * cpu_logical_map on success
522 */
523static void __init
524acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
525{
526 u64 hwid = processor->arm_mpidr;
527
f9058929
HG
528 if (!(processor->flags & ACPI_MADT_ENABLED)) {
529 pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid);
0f078336
LP
530 return;
531 }
532
f9058929
HG
533 if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) {
534 pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid);
0f078336
LP
535 return;
536 }
537
538 if (is_mpidr_duplicate(cpu_count, hwid)) {
539 pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid);
540 return;
541 }
542
543 /* Check if GICC structure of boot CPU is available in the MADT */
544 if (cpu_logical_map(0) == hwid) {
545 if (bootcpu_valid) {
546 pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n",
547 hwid);
548 return;
549 }
550 bootcpu_valid = true;
baa5567c 551 early_map_cpu_to_node(0, acpi_numa_get_nid(0, hwid));
0f078336
LP
552 return;
553 }
554
555 if (cpu_count >= NR_CPUS)
556 return;
557
558 /* map the logical cpu id to cpu MPIDR */
559 cpu_logical_map(cpu_count) = hwid;
560
5e89c55e
LP
561 /*
562 * Set-up the ACPI parking protocol cpu entries
563 * while initializing the cpu_logical_map to
564 * avoid parsing MADT entries multiple times for
565 * nothing (ie a valid cpu_logical_map entry should
566 * contain a valid parking protocol data set to
567 * initialize the cpu if the parking protocol is
568 * the only available enable method).
569 */
570 acpi_set_mailbox_entry(cpu_count, processor);
571
d8b47fca
HG
572 early_map_cpu_to_node(cpu_count, acpi_numa_get_nid(cpu_count, hwid));
573
0f078336
LP
574 cpu_count++;
575}
576
577static int __init
578acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header,
579 const unsigned long end)
580{
581 struct acpi_madt_generic_interrupt *processor;
582
583 processor = (struct acpi_madt_generic_interrupt *)header;
99e3e3ae 584 if (BAD_MADT_GICC_ENTRY(processor, end))
0f078336
LP
585 return -EINVAL;
586
587 acpi_table_print_madt_entry(header);
588
589 acpi_map_gic_cpu_interface(processor);
590
591 return 0;
592}
593#else
594#define acpi_table_parse_madt(...) do { } while (0)
595#endif
596
08e875c1 597/*
4c7aa002
JM
598 * Enumerate the possible CPU set from the device tree and build the
599 * cpu logical map array containing MPIDR values related to logical
600 * cpus. Assumes that cpu_logical_map(0) has already been initialized.
08e875c1 601 */
29b8302b 602static void __init of_parse_and_init_cpus(void)
08e875c1 603{
08e875c1 604 struct device_node *dn = NULL;
08e875c1
CM
605
606 while ((dn = of_find_node_by_type(dn, "cpu"))) {
0f078336 607 u64 hwid = of_get_cpu_mpidr(dn);
4c7aa002 608
0f078336 609 if (hwid == INVALID_HWID)
4c7aa002 610 goto next;
4c7aa002 611
0f078336
LP
612 if (is_mpidr_duplicate(cpu_count, hwid)) {
613 pr_err("%s: duplicate cpu reg properties in the DT\n",
614 dn->full_name);
4c7aa002
JM
615 goto next;
616 }
617
4c7aa002
JM
618 /*
619 * The numbering scheme requires that the boot CPU
620 * must be assigned logical id 0. Record it so that
621 * the logical map built from DT is validated and can
622 * be used.
623 */
624 if (hwid == cpu_logical_map(0)) {
625 if (bootcpu_valid) {
626 pr_err("%s: duplicate boot cpu reg property in DT\n",
627 dn->full_name);
628 goto next;
629 }
630
631 bootcpu_valid = true;
7ba5f605 632 early_map_cpu_to_node(0, of_node_to_nid(dn));
4c7aa002
JM
633
634 /*
635 * cpu_logical_map has already been
636 * initialized and the boot cpu doesn't need
637 * the enable-method so continue without
638 * incrementing cpu.
639 */
640 continue;
641 }
642
0f078336 643 if (cpu_count >= NR_CPUS)
08e875c1
CM
644 goto next;
645
4c7aa002 646 pr_debug("cpu logical map 0x%llx\n", hwid);
0f078336 647 cpu_logical_map(cpu_count) = hwid;
1a2db300
GK
648
649 early_map_cpu_to_node(cpu_count, of_node_to_nid(dn));
08e875c1 650next:
0f078336 651 cpu_count++;
08e875c1 652 }
0f078336
LP
653}
654
655/*
656 * Enumerate the possible CPU set from the device tree or ACPI and build the
657 * cpu logical map array containing MPIDR values related to logical
658 * cpus. Assumes that cpu_logical_map(0) has already been initialized.
659 */
660void __init smp_init_cpus(void)
661{
662 int i;
663
664 if (acpi_disabled)
665 of_parse_and_init_cpus();
666 else
667 /*
668 * do a walk of MADT to determine how many CPUs
669 * we have including disabled CPUs, and get information
670 * we need for SMP init
671 */
672 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
673 acpi_parse_gic_cpu_interface, 0);
08e875c1 674
50ee91bd
KW
675 if (cpu_count > nr_cpu_ids)
676 pr_warn("Number of cores (%d) exceeds configured maximum of %d - clipping\n",
677 cpu_count, nr_cpu_ids);
4c7aa002
JM
678
679 if (!bootcpu_valid) {
0f078336 680 pr_err("missing boot CPU MPIDR, not enabling secondaries\n");
4c7aa002
JM
681 return;
682 }
683
684 /*
819a8826
LP
685 * We need to set the cpu_logical_map entries before enabling
686 * the cpus so that cpu processor description entries (DT cpu nodes
687 * and ACPI MADT entries) can be retrieved by matching the cpu hwid
688 * with entries in cpu_logical_map while initializing the cpus.
689 * If the cpu set-up fails, invalidate the cpu_logical_map entry.
4c7aa002 690 */
50ee91bd 691 for (i = 1; i < nr_cpu_ids; i++) {
819a8826
LP
692 if (cpu_logical_map(i) != INVALID_HWID) {
693 if (smp_cpu_setup(i))
694 cpu_logical_map(i) = INVALID_HWID;
695 }
696 }
08e875c1
CM
697}
698
699void __init smp_prepare_cpus(unsigned int max_cpus)
700{
cd1aebf5 701 int err;
44dbcc93 702 unsigned int cpu;
c18df0ad 703 unsigned int this_cpu;
08e875c1 704
f6e763b9
MB
705 init_cpu_topology();
706
c18df0ad
DD
707 this_cpu = smp_processor_id();
708 store_cpu_topology(this_cpu);
709 numa_store_cpu_info(this_cpu);
f6e763b9 710
e75118a7
SP
711 /*
712 * If UP is mandated by "nosmp" (which implies "maxcpus=0"), don't set
713 * secondary CPUs present.
714 */
715 if (max_cpus == 0)
716 return;
717
08e875c1
CM
718 /*
719 * Initialise the present map (which describes the set of CPUs
720 * actually populated at the present time) and release the
721 * secondaries from the bootloader.
722 */
723 for_each_possible_cpu(cpu) {
08e875c1 724
57c82954
MR
725 per_cpu(cpu_number, cpu) = cpu;
726
d329de3f
MZ
727 if (cpu == smp_processor_id())
728 continue;
729
cd1aebf5 730 if (!cpu_ops[cpu])
08e875c1
CM
731 continue;
732
cd1aebf5 733 err = cpu_ops[cpu]->cpu_prepare(cpu);
d329de3f
MZ
734 if (err)
735 continue;
08e875c1
CM
736
737 set_cpu_present(cpu, true);
c18df0ad 738 numa_store_cpu_info(cpu);
08e875c1 739 }
08e875c1
CM
740}
741
36310736 742void (*__smp_cross_call)(const struct cpumask *, unsigned int);
08e875c1
CM
743
744void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
745{
45ed695a 746 __smp_cross_call = fn;
08e875c1
CM
747}
748
45ed695a
NP
749static const char *ipi_types[NR_IPI] __tracepoint_string = {
750#define S(x,s) [x] = s
08e875c1
CM
751 S(IPI_RESCHEDULE, "Rescheduling interrupts"),
752 S(IPI_CALL_FUNC, "Function call interrupts"),
08e875c1 753 S(IPI_CPU_STOP, "CPU stop interrupts"),
1f85008e 754 S(IPI_TIMER, "Timer broadcast interrupts"),
eb631bb5 755 S(IPI_IRQ_WORK, "IRQ work interrupts"),
5e89c55e 756 S(IPI_WAKEUP, "CPU wake-up interrupts"),
08e875c1
CM
757};
758
45ed695a
NP
759static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
760{
761 trace_ipi_raise(target, ipi_types[ipinr]);
762 __smp_cross_call(target, ipinr);
763}
764
08e875c1
CM
765void show_ipi_list(struct seq_file *p, int prec)
766{
767 unsigned int cpu, i;
768
769 for (i = 0; i < NR_IPI; i++) {
45ed695a 770 seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i,
08e875c1 771 prec >= 4 ? " " : "");
67317c26 772 for_each_online_cpu(cpu)
08e875c1
CM
773 seq_printf(p, "%10u ",
774 __get_irq_stat(cpu, ipi_irqs[i]));
775 seq_printf(p, " %s\n", ipi_types[i]);
776 }
777}
778
779u64 smp_irq_stat_cpu(unsigned int cpu)
780{
781 u64 sum = 0;
782 int i;
783
784 for (i = 0; i < NR_IPI; i++)
785 sum += __get_irq_stat(cpu, ipi_irqs[i]);
786
787 return sum;
788}
789
45ed695a
NP
790void arch_send_call_function_ipi_mask(const struct cpumask *mask)
791{
792 smp_cross_call(mask, IPI_CALL_FUNC);
793}
794
795void arch_send_call_function_single_ipi(int cpu)
796{
0aaf0dae 797 smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC);
45ed695a
NP
798}
799
5e89c55e
LP
800#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL
801void arch_send_wakeup_ipi_mask(const struct cpumask *mask)
802{
803 smp_cross_call(mask, IPI_WAKEUP);
804}
805#endif
806
45ed695a
NP
807#ifdef CONFIG_IRQ_WORK
808void arch_irq_work_raise(void)
809{
810 if (__smp_cross_call)
811 smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK);
812}
813#endif
814
08e875c1
CM
815/*
816 * ipi_cpu_stop - handle IPI from smp_send_stop()
817 */
818static void ipi_cpu_stop(unsigned int cpu)
819{
08e875c1
CM
820 set_cpu_online(cpu, false);
821
08e875c1
CM
822 local_irq_disable();
823
824 while (1)
825 cpu_relax();
826}
827
828/*
829 * Main handler for inter-processor interrupts
830 */
831void handle_IPI(int ipinr, struct pt_regs *regs)
832{
833 unsigned int cpu = smp_processor_id();
834 struct pt_regs *old_regs = set_irq_regs(regs);
835
45ed695a 836 if ((unsigned)ipinr < NR_IPI) {
be081d9b 837 trace_ipi_entry_rcuidle(ipi_types[ipinr]);
45ed695a
NP
838 __inc_irq_stat(cpu, ipi_irqs[ipinr]);
839 }
08e875c1
CM
840
841 switch (ipinr) {
842 case IPI_RESCHEDULE:
843 scheduler_ipi();
844 break;
845
846 case IPI_CALL_FUNC:
847 irq_enter();
848 generic_smp_call_function_interrupt();
849 irq_exit();
850 break;
851
08e875c1
CM
852 case IPI_CPU_STOP:
853 irq_enter();
854 ipi_cpu_stop(cpu);
855 irq_exit();
856 break;
857
1f85008e
LP
858#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
859 case IPI_TIMER:
860 irq_enter();
861 tick_receive_broadcast();
862 irq_exit();
863 break;
864#endif
865
eb631bb5
LB
866#ifdef CONFIG_IRQ_WORK
867 case IPI_IRQ_WORK:
868 irq_enter();
869 irq_work_run();
870 irq_exit();
871 break;
872#endif
873
5e89c55e
LP
874#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL
875 case IPI_WAKEUP:
876 WARN_ONCE(!acpi_parking_protocol_valid(cpu),
877 "CPU%u: Wake-up IPI outside the ACPI parking protocol\n",
878 cpu);
879 break;
880#endif
881
08e875c1
CM
882 default:
883 pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
884 break;
885 }
45ed695a
NP
886
887 if ((unsigned)ipinr < NR_IPI)
be081d9b 888 trace_ipi_exit_rcuidle(ipi_types[ipinr]);
08e875c1
CM
889 set_irq_regs(old_regs);
890}
891
892void smp_send_reschedule(int cpu)
893{
894 smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
895}
896
1f85008e
LP
897#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
898void tick_broadcast(const struct cpumask *mask)
899{
900 smp_cross_call(mask, IPI_TIMER);
901}
902#endif
903
08e875c1
CM
904void smp_send_stop(void)
905{
906 unsigned long timeout;
907
908 if (num_online_cpus() > 1) {
909 cpumask_t mask;
910
911 cpumask_copy(&mask, cpu_online_mask);
434ed7f4 912 cpumask_clear_cpu(smp_processor_id(), &mask);
08e875c1 913
82611c14
JG
914 if (system_state == SYSTEM_BOOTING ||
915 system_state == SYSTEM_RUNNING)
916 pr_crit("SMP: stopping secondary CPUs\n");
08e875c1
CM
917 smp_cross_call(&mask, IPI_CPU_STOP);
918 }
919
920 /* Wait up to one second for other CPUs to stop */
921 timeout = USEC_PER_SEC;
922 while (num_online_cpus() > 1 && timeout--)
923 udelay(1);
924
925 if (num_online_cpus() > 1)
82611c14
JG
926 pr_warning("SMP: failed to stop secondary CPUs %*pbl\n",
927 cpumask_pr_args(cpu_online_mask));
08e875c1
CM
928}
929
930/*
931 * not supported here
932 */
933int setup_profiling_timer(unsigned int multiplier)
934{
935 return -EINVAL;
936}
5c492c3f
JM
937
938static bool have_cpu_die(void)
939{
940#ifdef CONFIG_HOTPLUG_CPU
941 int any_cpu = raw_smp_processor_id();
942
943 if (cpu_ops[any_cpu]->cpu_die)
944 return true;
945#endif
946 return false;
947}
948
949bool cpus_are_stuck_in_kernel(void)
950{
951 bool smp_spin_tables = (num_possible_cpus() > 1 && !have_cpu_die());
952
953 return !!cpus_stuck_in_kernel || smp_spin_tables;
954}