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Commit | Line | Data |
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08e875c1 CM |
1 | /* |
2 | * SMP initialisation and IPI support | |
3 | * Based on arch/arm/kernel/smp.c | |
4 | * | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <linux/delay.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/sched.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/cache.h> | |
26 | #include <linux/profile.h> | |
27 | #include <linux/errno.h> | |
28 | #include <linux/mm.h> | |
29 | #include <linux/err.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/smp.h> | |
32 | #include <linux/seq_file.h> | |
33 | #include <linux/irq.h> | |
34 | #include <linux/percpu.h> | |
35 | #include <linux/clockchips.h> | |
36 | #include <linux/completion.h> | |
37 | #include <linux/of.h> | |
eb631bb5 | 38 | #include <linux/irq_work.h> |
08e875c1 | 39 | |
e039ee4e | 40 | #include <asm/alternative.h> |
08e875c1 CM |
41 | #include <asm/atomic.h> |
42 | #include <asm/cacheflush.h> | |
df857416 | 43 | #include <asm/cpu.h> |
08e875c1 | 44 | #include <asm/cputype.h> |
cd1aebf5 | 45 | #include <asm/cpu_ops.h> |
08e875c1 CM |
46 | #include <asm/mmu_context.h> |
47 | #include <asm/pgtable.h> | |
48 | #include <asm/pgalloc.h> | |
49 | #include <asm/processor.h> | |
4c7aa002 | 50 | #include <asm/smp_plat.h> |
08e875c1 CM |
51 | #include <asm/sections.h> |
52 | #include <asm/tlbflush.h> | |
53 | #include <asm/ptrace.h> | |
08e875c1 | 54 | |
45ed695a NP |
55 | #define CREATE_TRACE_POINTS |
56 | #include <trace/events/ipi.h> | |
57 | ||
08e875c1 CM |
58 | /* |
59 | * as from 2.5, kernels no longer have an init_tasks structure | |
60 | * so we need some other way of telling a new secondary core | |
61 | * where to place its SVC stack | |
62 | */ | |
63 | struct secondary_data secondary_data; | |
08e875c1 CM |
64 | |
65 | enum ipi_msg_type { | |
66 | IPI_RESCHEDULE, | |
67 | IPI_CALL_FUNC, | |
08e875c1 | 68 | IPI_CPU_STOP, |
1f85008e | 69 | IPI_TIMER, |
eb631bb5 | 70 | IPI_IRQ_WORK, |
08e875c1 CM |
71 | }; |
72 | ||
08e875c1 CM |
73 | /* |
74 | * Boot a secondary CPU, and assign it the specified idle task. | |
75 | * This also gives us the initial stack to use for this CPU. | |
76 | */ | |
b8c6453a | 77 | static int boot_secondary(unsigned int cpu, struct task_struct *idle) |
08e875c1 | 78 | { |
652af899 MR |
79 | if (cpu_ops[cpu]->cpu_boot) |
80 | return cpu_ops[cpu]->cpu_boot(cpu); | |
08e875c1 | 81 | |
652af899 | 82 | return -EOPNOTSUPP; |
08e875c1 CM |
83 | } |
84 | ||
85 | static DECLARE_COMPLETION(cpu_running); | |
86 | ||
b8c6453a | 87 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
08e875c1 CM |
88 | { |
89 | int ret; | |
90 | ||
91 | /* | |
92 | * We need to tell the secondary core where to find its stack and the | |
93 | * page tables. | |
94 | */ | |
95 | secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; | |
96 | __flush_dcache_area(&secondary_data, sizeof(secondary_data)); | |
97 | ||
98 | /* | |
99 | * Now bring the CPU into our world. | |
100 | */ | |
101 | ret = boot_secondary(cpu, idle); | |
102 | if (ret == 0) { | |
103 | /* | |
104 | * CPU was successfully started, wait for it to come online or | |
105 | * time out. | |
106 | */ | |
107 | wait_for_completion_timeout(&cpu_running, | |
108 | msecs_to_jiffies(1000)); | |
109 | ||
110 | if (!cpu_online(cpu)) { | |
111 | pr_crit("CPU%u: failed to come online\n", cpu); | |
112 | ret = -EIO; | |
113 | } | |
114 | } else { | |
115 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
116 | } | |
117 | ||
118 | secondary_data.stack = NULL; | |
119 | ||
120 | return ret; | |
121 | } | |
122 | ||
f6e763b9 MB |
123 | static void smp_store_cpu_info(unsigned int cpuid) |
124 | { | |
125 | store_cpu_topology(cpuid); | |
126 | } | |
127 | ||
08e875c1 CM |
128 | /* |
129 | * This is the secondary CPU boot entry. We're using this CPUs | |
130 | * idle thread stack, but a set of temporary page tables. | |
131 | */ | |
b8c6453a | 132 | asmlinkage void secondary_start_kernel(void) |
08e875c1 CM |
133 | { |
134 | struct mm_struct *mm = &init_mm; | |
135 | unsigned int cpu = smp_processor_id(); | |
136 | ||
08e875c1 CM |
137 | /* |
138 | * All kernel threads share the same mm context; grab a | |
139 | * reference and switch to it. | |
140 | */ | |
141 | atomic_inc(&mm->mm_count); | |
142 | current->active_mm = mm; | |
143 | cpumask_set_cpu(cpu, mm_cpumask(mm)); | |
144 | ||
71586276 WD |
145 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
146 | printk("CPU%u: Booted secondary processor\n", cpu); | |
147 | ||
08e875c1 CM |
148 | /* |
149 | * TTBR0 is only used for the identity mapping at this stage. Make it | |
150 | * point to zero page to avoid speculatively fetching new entries. | |
151 | */ | |
152 | cpu_set_reserved_ttbr0(); | |
153 | flush_tlb_all(); | |
dd006da2 | 154 | cpu_set_default_tcr_t0sz(); |
08e875c1 CM |
155 | |
156 | preempt_disable(); | |
157 | trace_hardirqs_off(); | |
158 | ||
652af899 MR |
159 | if (cpu_ops[cpu]->cpu_postboot) |
160 | cpu_ops[cpu]->cpu_postboot(); | |
08e875c1 | 161 | |
df857416 MR |
162 | /* |
163 | * Log the CPU info before it is marked online and might get read. | |
164 | */ | |
165 | cpuinfo_store_cpu(); | |
166 | ||
7ade67b5 MZ |
167 | /* |
168 | * Enable GIC and timers. | |
169 | */ | |
170 | notify_cpu_starting(cpu); | |
171 | ||
f6e763b9 MB |
172 | smp_store_cpu_info(cpu); |
173 | ||
08e875c1 CM |
174 | /* |
175 | * OK, now it's safe to let the boot CPU continue. Wait for | |
176 | * the CPU migration code to notice that the CPU is online | |
177 | * before we continue. | |
178 | */ | |
179 | set_cpu_online(cpu, true); | |
b3770b32 | 180 | complete(&cpu_running); |
08e875c1 | 181 | |
d8ed442a | 182 | local_dbg_enable(); |
53ae3acd | 183 | local_irq_enable(); |
b3bf6aa7 | 184 | local_async_enable(); |
53ae3acd | 185 | |
08e875c1 CM |
186 | /* |
187 | * OK, it's off to the idle thread for us | |
188 | */ | |
0087298f | 189 | cpu_startup_entry(CPUHP_ONLINE); |
08e875c1 CM |
190 | } |
191 | ||
9327e2c6 MR |
192 | #ifdef CONFIG_HOTPLUG_CPU |
193 | static int op_cpu_disable(unsigned int cpu) | |
194 | { | |
195 | /* | |
196 | * If we don't have a cpu_die method, abort before we reach the point | |
197 | * of no return. CPU0 may not have an cpu_ops, so test for it. | |
198 | */ | |
199 | if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die) | |
200 | return -EOPNOTSUPP; | |
201 | ||
202 | /* | |
203 | * We may need to abort a hot unplug for some other mechanism-specific | |
204 | * reason. | |
205 | */ | |
206 | if (cpu_ops[cpu]->cpu_disable) | |
207 | return cpu_ops[cpu]->cpu_disable(cpu); | |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
212 | /* | |
213 | * __cpu_disable runs on the processor to be shutdown. | |
214 | */ | |
215 | int __cpu_disable(void) | |
216 | { | |
217 | unsigned int cpu = smp_processor_id(); | |
218 | int ret; | |
219 | ||
220 | ret = op_cpu_disable(cpu); | |
221 | if (ret) | |
222 | return ret; | |
223 | ||
224 | /* | |
225 | * Take this CPU offline. Once we clear this, we can't return, | |
226 | * and we must not schedule until we're ready to give up the cpu. | |
227 | */ | |
228 | set_cpu_online(cpu, false); | |
229 | ||
230 | /* | |
231 | * OK - migrate IRQs away from this CPU | |
232 | */ | |
233 | migrate_irqs(); | |
234 | ||
235 | /* | |
236 | * Remove this CPU from the vm mask set of all processes. | |
237 | */ | |
238 | clear_tasks_mm_cpumask(cpu); | |
239 | ||
240 | return 0; | |
241 | } | |
242 | ||
c814ca02 AC |
243 | static int op_cpu_kill(unsigned int cpu) |
244 | { | |
245 | /* | |
246 | * If we have no means of synchronising with the dying CPU, then assume | |
247 | * that it is really dead. We can only wait for an arbitrary length of | |
248 | * time and hope that it's dead, so let's skip the wait and just hope. | |
249 | */ | |
250 | if (!cpu_ops[cpu]->cpu_kill) | |
251 | return 1; | |
252 | ||
253 | return cpu_ops[cpu]->cpu_kill(cpu); | |
254 | } | |
255 | ||
9327e2c6 MR |
256 | static DECLARE_COMPLETION(cpu_died); |
257 | ||
258 | /* | |
259 | * called on the thread which is asking for a CPU to be shutdown - | |
260 | * waits until shutdown has completed, or it is timed out. | |
261 | */ | |
262 | void __cpu_die(unsigned int cpu) | |
263 | { | |
264 | if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) { | |
265 | pr_crit("CPU%u: cpu didn't die\n", cpu); | |
266 | return; | |
267 | } | |
268 | pr_notice("CPU%u: shutdown\n", cpu); | |
c814ca02 AC |
269 | |
270 | /* | |
271 | * Now that the dying CPU is beyond the point of no return w.r.t. | |
272 | * in-kernel synchronisation, try to get the firwmare to help us to | |
273 | * verify that it has really left the kernel before we consider | |
274 | * clobbering anything it might still be using. | |
275 | */ | |
276 | if (!op_cpu_kill(cpu)) | |
277 | pr_warn("CPU%d may not have shut down cleanly\n", cpu); | |
9327e2c6 MR |
278 | } |
279 | ||
280 | /* | |
281 | * Called from the idle thread for the CPU which has been shutdown. | |
282 | * | |
283 | * Note that we disable IRQs here, but do not re-enable them | |
284 | * before returning to the caller. This is also the behaviour | |
285 | * of the other hotplug-cpu capable cores, so presumably coming | |
286 | * out of idle fixes this. | |
287 | */ | |
288 | void cpu_die(void) | |
289 | { | |
290 | unsigned int cpu = smp_processor_id(); | |
291 | ||
292 | idle_task_exit(); | |
293 | ||
294 | local_irq_disable(); | |
295 | ||
296 | /* Tell __cpu_die() that this CPU is now safe to dispose of */ | |
297 | complete(&cpu_died); | |
298 | ||
299 | /* | |
300 | * Actually shutdown the CPU. This must never fail. The specific hotplug | |
301 | * mechanism must perform all required cache maintenance to ensure that | |
302 | * no dirty lines are lost in the process of shutting down the CPU. | |
303 | */ | |
304 | cpu_ops[cpu]->cpu_die(cpu); | |
305 | ||
306 | BUG(); | |
307 | } | |
308 | #endif | |
309 | ||
08e875c1 CM |
310 | void __init smp_cpus_done(unsigned int max_cpus) |
311 | { | |
326b16db | 312 | pr_info("SMP: Total of %d processors activated.\n", num_online_cpus()); |
137650aa | 313 | do_post_cpus_up_work(); |
08e875c1 CM |
314 | } |
315 | ||
316 | void __init smp_prepare_boot_cpu(void) | |
317 | { | |
71586276 | 318 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
08e875c1 CM |
319 | } |
320 | ||
819a8826 LP |
321 | /* |
322 | * Initialize cpu operations for a logical cpu and | |
323 | * set it in the possible mask on success | |
324 | */ | |
325 | static int __init smp_cpu_setup(int cpu) | |
326 | { | |
327 | if (cpu_read_ops(cpu)) | |
328 | return -ENODEV; | |
329 | ||
330 | if (cpu_ops[cpu]->cpu_init(cpu)) | |
331 | return -ENODEV; | |
332 | ||
333 | set_cpu_possible(cpu, true); | |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
08e875c1 | 338 | /* |
4c7aa002 JM |
339 | * Enumerate the possible CPU set from the device tree and build the |
340 | * cpu logical map array containing MPIDR values related to logical | |
341 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
08e875c1 | 342 | */ |
fccb9a81 | 343 | void __init of_smp_init_cpus(void) |
08e875c1 | 344 | { |
08e875c1 | 345 | struct device_node *dn = NULL; |
cd1aebf5 | 346 | unsigned int i, cpu = 1; |
4c7aa002 | 347 | bool bootcpu_valid = false; |
08e875c1 CM |
348 | |
349 | while ((dn = of_find_node_by_type(dn, "cpu"))) { | |
72aea393 | 350 | const u32 *cell; |
4c7aa002 JM |
351 | u64 hwid; |
352 | ||
353 | /* | |
354 | * A cpu node with missing "reg" property is | |
355 | * considered invalid to build a cpu_logical_map | |
356 | * entry. | |
357 | */ | |
72aea393 WD |
358 | cell = of_get_property(dn, "reg", NULL); |
359 | if (!cell) { | |
4c7aa002 JM |
360 | pr_err("%s: missing reg property\n", dn->full_name); |
361 | goto next; | |
362 | } | |
72aea393 | 363 | hwid = of_read_number(cell, of_n_addr_cells(dn)); |
4c7aa002 JM |
364 | |
365 | /* | |
366 | * Non affinity bits must be set to 0 in the DT | |
367 | */ | |
368 | if (hwid & ~MPIDR_HWID_BITMASK) { | |
369 | pr_err("%s: invalid reg property\n", dn->full_name); | |
370 | goto next; | |
371 | } | |
372 | ||
373 | /* | |
374 | * Duplicate MPIDRs are a recipe for disaster. Scan | |
375 | * all initialized entries and check for | |
376 | * duplicates. If any is found just ignore the cpu. | |
377 | * cpu_logical_map was initialized to INVALID_HWID to | |
378 | * avoid matching valid MPIDR values. | |
379 | */ | |
380 | for (i = 1; (i < cpu) && (i < NR_CPUS); i++) { | |
381 | if (cpu_logical_map(i) == hwid) { | |
382 | pr_err("%s: duplicate cpu reg properties in the DT\n", | |
383 | dn->full_name); | |
384 | goto next; | |
385 | } | |
386 | } | |
387 | ||
388 | /* | |
389 | * The numbering scheme requires that the boot CPU | |
390 | * must be assigned logical id 0. Record it so that | |
391 | * the logical map built from DT is validated and can | |
392 | * be used. | |
393 | */ | |
394 | if (hwid == cpu_logical_map(0)) { | |
395 | if (bootcpu_valid) { | |
396 | pr_err("%s: duplicate boot cpu reg property in DT\n", | |
397 | dn->full_name); | |
398 | goto next; | |
399 | } | |
400 | ||
401 | bootcpu_valid = true; | |
402 | ||
403 | /* | |
404 | * cpu_logical_map has already been | |
405 | * initialized and the boot cpu doesn't need | |
406 | * the enable-method so continue without | |
407 | * incrementing cpu. | |
408 | */ | |
409 | continue; | |
410 | } | |
411 | ||
08e875c1 CM |
412 | if (cpu >= NR_CPUS) |
413 | goto next; | |
414 | ||
4c7aa002 JM |
415 | pr_debug("cpu logical map 0x%llx\n", hwid); |
416 | cpu_logical_map(cpu) = hwid; | |
08e875c1 CM |
417 | next: |
418 | cpu++; | |
419 | } | |
420 | ||
421 | /* sanity check */ | |
422 | if (cpu > NR_CPUS) | |
423 | pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n", | |
424 | cpu, NR_CPUS); | |
4c7aa002 JM |
425 | |
426 | if (!bootcpu_valid) { | |
427 | pr_err("DT missing boot CPU MPIDR, not enabling secondaries\n"); | |
428 | return; | |
429 | } | |
430 | ||
431 | /* | |
819a8826 LP |
432 | * We need to set the cpu_logical_map entries before enabling |
433 | * the cpus so that cpu processor description entries (DT cpu nodes | |
434 | * and ACPI MADT entries) can be retrieved by matching the cpu hwid | |
435 | * with entries in cpu_logical_map while initializing the cpus. | |
436 | * If the cpu set-up fails, invalidate the cpu_logical_map entry. | |
4c7aa002 | 437 | */ |
819a8826 LP |
438 | for (i = 1; i < NR_CPUS; i++) { |
439 | if (cpu_logical_map(i) != INVALID_HWID) { | |
440 | if (smp_cpu_setup(i)) | |
441 | cpu_logical_map(i) = INVALID_HWID; | |
442 | } | |
443 | } | |
08e875c1 CM |
444 | } |
445 | ||
446 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
447 | { | |
cd1aebf5 MR |
448 | int err; |
449 | unsigned int cpu, ncores = num_possible_cpus(); | |
08e875c1 | 450 | |
f6e763b9 MB |
451 | init_cpu_topology(); |
452 | ||
453 | smp_store_cpu_info(smp_processor_id()); | |
454 | ||
08e875c1 CM |
455 | /* |
456 | * are we trying to boot more cores than exist? | |
457 | */ | |
458 | if (max_cpus > ncores) | |
459 | max_cpus = ncores; | |
460 | ||
d329de3f MZ |
461 | /* Don't bother if we're effectively UP */ |
462 | if (max_cpus <= 1) | |
463 | return; | |
464 | ||
08e875c1 CM |
465 | /* |
466 | * Initialise the present map (which describes the set of CPUs | |
467 | * actually populated at the present time) and release the | |
468 | * secondaries from the bootloader. | |
d329de3f MZ |
469 | * |
470 | * Make sure we online at most (max_cpus - 1) additional CPUs. | |
08e875c1 | 471 | */ |
d329de3f | 472 | max_cpus--; |
08e875c1 CM |
473 | for_each_possible_cpu(cpu) { |
474 | if (max_cpus == 0) | |
475 | break; | |
476 | ||
d329de3f MZ |
477 | if (cpu == smp_processor_id()) |
478 | continue; | |
479 | ||
cd1aebf5 | 480 | if (!cpu_ops[cpu]) |
08e875c1 CM |
481 | continue; |
482 | ||
cd1aebf5 | 483 | err = cpu_ops[cpu]->cpu_prepare(cpu); |
d329de3f MZ |
484 | if (err) |
485 | continue; | |
08e875c1 CM |
486 | |
487 | set_cpu_present(cpu, true); | |
488 | max_cpus--; | |
489 | } | |
08e875c1 CM |
490 | } |
491 | ||
36310736 | 492 | void (*__smp_cross_call)(const struct cpumask *, unsigned int); |
08e875c1 CM |
493 | |
494 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
495 | { | |
45ed695a | 496 | __smp_cross_call = fn; |
08e875c1 CM |
497 | } |
498 | ||
45ed695a NP |
499 | static const char *ipi_types[NR_IPI] __tracepoint_string = { |
500 | #define S(x,s) [x] = s | |
08e875c1 CM |
501 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), |
502 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
08e875c1 | 503 | S(IPI_CPU_STOP, "CPU stop interrupts"), |
1f85008e | 504 | S(IPI_TIMER, "Timer broadcast interrupts"), |
eb631bb5 | 505 | S(IPI_IRQ_WORK, "IRQ work interrupts"), |
08e875c1 CM |
506 | }; |
507 | ||
45ed695a NP |
508 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) |
509 | { | |
510 | trace_ipi_raise(target, ipi_types[ipinr]); | |
511 | __smp_cross_call(target, ipinr); | |
512 | } | |
513 | ||
08e875c1 CM |
514 | void show_ipi_list(struct seq_file *p, int prec) |
515 | { | |
516 | unsigned int cpu, i; | |
517 | ||
518 | for (i = 0; i < NR_IPI; i++) { | |
45ed695a | 519 | seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, |
08e875c1 | 520 | prec >= 4 ? " " : ""); |
67317c26 | 521 | for_each_online_cpu(cpu) |
08e875c1 CM |
522 | seq_printf(p, "%10u ", |
523 | __get_irq_stat(cpu, ipi_irqs[i])); | |
524 | seq_printf(p, " %s\n", ipi_types[i]); | |
525 | } | |
526 | } | |
527 | ||
528 | u64 smp_irq_stat_cpu(unsigned int cpu) | |
529 | { | |
530 | u64 sum = 0; | |
531 | int i; | |
532 | ||
533 | for (i = 0; i < NR_IPI; i++) | |
534 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
535 | ||
536 | return sum; | |
537 | } | |
538 | ||
45ed695a NP |
539 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
540 | { | |
541 | smp_cross_call(mask, IPI_CALL_FUNC); | |
542 | } | |
543 | ||
544 | void arch_send_call_function_single_ipi(int cpu) | |
545 | { | |
0aaf0dae | 546 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); |
45ed695a NP |
547 | } |
548 | ||
549 | #ifdef CONFIG_IRQ_WORK | |
550 | void arch_irq_work_raise(void) | |
551 | { | |
552 | if (__smp_cross_call) | |
553 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); | |
554 | } | |
555 | #endif | |
556 | ||
08e875c1 CM |
557 | static DEFINE_RAW_SPINLOCK(stop_lock); |
558 | ||
559 | /* | |
560 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
561 | */ | |
562 | static void ipi_cpu_stop(unsigned int cpu) | |
563 | { | |
564 | if (system_state == SYSTEM_BOOTING || | |
565 | system_state == SYSTEM_RUNNING) { | |
566 | raw_spin_lock(&stop_lock); | |
567 | pr_crit("CPU%u: stopping\n", cpu); | |
568 | dump_stack(); | |
569 | raw_spin_unlock(&stop_lock); | |
570 | } | |
571 | ||
572 | set_cpu_online(cpu, false); | |
573 | ||
08e875c1 CM |
574 | local_irq_disable(); |
575 | ||
576 | while (1) | |
577 | cpu_relax(); | |
578 | } | |
579 | ||
580 | /* | |
581 | * Main handler for inter-processor interrupts | |
582 | */ | |
583 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
584 | { | |
585 | unsigned int cpu = smp_processor_id(); | |
586 | struct pt_regs *old_regs = set_irq_regs(regs); | |
587 | ||
45ed695a NP |
588 | if ((unsigned)ipinr < NR_IPI) { |
589 | trace_ipi_entry(ipi_types[ipinr]); | |
590 | __inc_irq_stat(cpu, ipi_irqs[ipinr]); | |
591 | } | |
08e875c1 CM |
592 | |
593 | switch (ipinr) { | |
594 | case IPI_RESCHEDULE: | |
595 | scheduler_ipi(); | |
596 | break; | |
597 | ||
598 | case IPI_CALL_FUNC: | |
599 | irq_enter(); | |
600 | generic_smp_call_function_interrupt(); | |
601 | irq_exit(); | |
602 | break; | |
603 | ||
08e875c1 CM |
604 | case IPI_CPU_STOP: |
605 | irq_enter(); | |
606 | ipi_cpu_stop(cpu); | |
607 | irq_exit(); | |
608 | break; | |
609 | ||
1f85008e LP |
610 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
611 | case IPI_TIMER: | |
612 | irq_enter(); | |
613 | tick_receive_broadcast(); | |
614 | irq_exit(); | |
615 | break; | |
616 | #endif | |
617 | ||
eb631bb5 LB |
618 | #ifdef CONFIG_IRQ_WORK |
619 | case IPI_IRQ_WORK: | |
620 | irq_enter(); | |
621 | irq_work_run(); | |
622 | irq_exit(); | |
623 | break; | |
624 | #endif | |
625 | ||
08e875c1 CM |
626 | default: |
627 | pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); | |
628 | break; | |
629 | } | |
45ed695a NP |
630 | |
631 | if ((unsigned)ipinr < NR_IPI) | |
632 | trace_ipi_exit(ipi_types[ipinr]); | |
08e875c1 CM |
633 | set_irq_regs(old_regs); |
634 | } | |
635 | ||
636 | void smp_send_reschedule(int cpu) | |
637 | { | |
638 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); | |
639 | } | |
640 | ||
1f85008e LP |
641 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
642 | void tick_broadcast(const struct cpumask *mask) | |
643 | { | |
644 | smp_cross_call(mask, IPI_TIMER); | |
645 | } | |
646 | #endif | |
647 | ||
08e875c1 CM |
648 | void smp_send_stop(void) |
649 | { | |
650 | unsigned long timeout; | |
651 | ||
652 | if (num_online_cpus() > 1) { | |
653 | cpumask_t mask; | |
654 | ||
655 | cpumask_copy(&mask, cpu_online_mask); | |
434ed7f4 | 656 | cpumask_clear_cpu(smp_processor_id(), &mask); |
08e875c1 CM |
657 | |
658 | smp_cross_call(&mask, IPI_CPU_STOP); | |
659 | } | |
660 | ||
661 | /* Wait up to one second for other CPUs to stop */ | |
662 | timeout = USEC_PER_SEC; | |
663 | while (num_online_cpus() > 1 && timeout--) | |
664 | udelay(1); | |
665 | ||
666 | if (num_online_cpus() > 1) | |
667 | pr_warning("SMP: failed to stop secondary CPUs\n"); | |
668 | } | |
669 | ||
670 | /* | |
671 | * not supported here | |
672 | */ | |
673 | int setup_profiling_timer(unsigned int multiplier) | |
674 | { | |
675 | return -EINVAL; | |
676 | } |