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Commit | Line | Data |
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08e875c1 CM |
1 | /* |
2 | * SMP initialisation and IPI support | |
3 | * Based on arch/arm/kernel/smp.c | |
4 | * | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
0f078336 | 20 | #include <linux/acpi.h> |
08e875c1 CM |
21 | #include <linux/delay.h> |
22 | #include <linux/init.h> | |
23 | #include <linux/spinlock.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/profile.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/err.h> | |
31 | #include <linux/cpu.h> | |
32 | #include <linux/smp.h> | |
33 | #include <linux/seq_file.h> | |
34 | #include <linux/irq.h> | |
35 | #include <linux/percpu.h> | |
36 | #include <linux/clockchips.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/of.h> | |
eb631bb5 | 39 | #include <linux/irq_work.h> |
08e875c1 | 40 | |
e039ee4e | 41 | #include <asm/alternative.h> |
08e875c1 CM |
42 | #include <asm/atomic.h> |
43 | #include <asm/cacheflush.h> | |
df857416 | 44 | #include <asm/cpu.h> |
08e875c1 | 45 | #include <asm/cputype.h> |
cd1aebf5 | 46 | #include <asm/cpu_ops.h> |
08e875c1 CM |
47 | #include <asm/mmu_context.h> |
48 | #include <asm/pgtable.h> | |
49 | #include <asm/pgalloc.h> | |
50 | #include <asm/processor.h> | |
4c7aa002 | 51 | #include <asm/smp_plat.h> |
08e875c1 CM |
52 | #include <asm/sections.h> |
53 | #include <asm/tlbflush.h> | |
54 | #include <asm/ptrace.h> | |
08e875c1 | 55 | |
45ed695a NP |
56 | #define CREATE_TRACE_POINTS |
57 | #include <trace/events/ipi.h> | |
58 | ||
08e875c1 CM |
59 | /* |
60 | * as from 2.5, kernels no longer have an init_tasks structure | |
61 | * so we need some other way of telling a new secondary core | |
62 | * where to place its SVC stack | |
63 | */ | |
64 | struct secondary_data secondary_data; | |
08e875c1 CM |
65 | |
66 | enum ipi_msg_type { | |
67 | IPI_RESCHEDULE, | |
68 | IPI_CALL_FUNC, | |
08e875c1 | 69 | IPI_CPU_STOP, |
1f85008e | 70 | IPI_TIMER, |
eb631bb5 | 71 | IPI_IRQ_WORK, |
08e875c1 CM |
72 | }; |
73 | ||
08e875c1 CM |
74 | /* |
75 | * Boot a secondary CPU, and assign it the specified idle task. | |
76 | * This also gives us the initial stack to use for this CPU. | |
77 | */ | |
b8c6453a | 78 | static int boot_secondary(unsigned int cpu, struct task_struct *idle) |
08e875c1 | 79 | { |
652af899 MR |
80 | if (cpu_ops[cpu]->cpu_boot) |
81 | return cpu_ops[cpu]->cpu_boot(cpu); | |
08e875c1 | 82 | |
652af899 | 83 | return -EOPNOTSUPP; |
08e875c1 CM |
84 | } |
85 | ||
86 | static DECLARE_COMPLETION(cpu_running); | |
87 | ||
b8c6453a | 88 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
08e875c1 CM |
89 | { |
90 | int ret; | |
91 | ||
92 | /* | |
93 | * We need to tell the secondary core where to find its stack and the | |
94 | * page tables. | |
95 | */ | |
96 | secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; | |
97 | __flush_dcache_area(&secondary_data, sizeof(secondary_data)); | |
98 | ||
99 | /* | |
100 | * Now bring the CPU into our world. | |
101 | */ | |
102 | ret = boot_secondary(cpu, idle); | |
103 | if (ret == 0) { | |
104 | /* | |
105 | * CPU was successfully started, wait for it to come online or | |
106 | * time out. | |
107 | */ | |
108 | wait_for_completion_timeout(&cpu_running, | |
109 | msecs_to_jiffies(1000)); | |
110 | ||
111 | if (!cpu_online(cpu)) { | |
112 | pr_crit("CPU%u: failed to come online\n", cpu); | |
113 | ret = -EIO; | |
114 | } | |
115 | } else { | |
116 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
117 | } | |
118 | ||
119 | secondary_data.stack = NULL; | |
120 | ||
121 | return ret; | |
122 | } | |
123 | ||
f6e763b9 MB |
124 | static void smp_store_cpu_info(unsigned int cpuid) |
125 | { | |
126 | store_cpu_topology(cpuid); | |
127 | } | |
128 | ||
08e875c1 CM |
129 | /* |
130 | * This is the secondary CPU boot entry. We're using this CPUs | |
131 | * idle thread stack, but a set of temporary page tables. | |
132 | */ | |
b8c6453a | 133 | asmlinkage void secondary_start_kernel(void) |
08e875c1 CM |
134 | { |
135 | struct mm_struct *mm = &init_mm; | |
136 | unsigned int cpu = smp_processor_id(); | |
137 | ||
08e875c1 CM |
138 | /* |
139 | * All kernel threads share the same mm context; grab a | |
140 | * reference and switch to it. | |
141 | */ | |
142 | atomic_inc(&mm->mm_count); | |
143 | current->active_mm = mm; | |
144 | cpumask_set_cpu(cpu, mm_cpumask(mm)); | |
145 | ||
71586276 WD |
146 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
147 | printk("CPU%u: Booted secondary processor\n", cpu); | |
148 | ||
08e875c1 CM |
149 | /* |
150 | * TTBR0 is only used for the identity mapping at this stage. Make it | |
151 | * point to zero page to avoid speculatively fetching new entries. | |
152 | */ | |
153 | cpu_set_reserved_ttbr0(); | |
154 | flush_tlb_all(); | |
dd006da2 | 155 | cpu_set_default_tcr_t0sz(); |
08e875c1 CM |
156 | |
157 | preempt_disable(); | |
158 | trace_hardirqs_off(); | |
159 | ||
652af899 MR |
160 | if (cpu_ops[cpu]->cpu_postboot) |
161 | cpu_ops[cpu]->cpu_postboot(); | |
08e875c1 | 162 | |
df857416 MR |
163 | /* |
164 | * Log the CPU info before it is marked online and might get read. | |
165 | */ | |
166 | cpuinfo_store_cpu(); | |
167 | ||
7ade67b5 MZ |
168 | /* |
169 | * Enable GIC and timers. | |
170 | */ | |
171 | notify_cpu_starting(cpu); | |
172 | ||
f6e763b9 MB |
173 | smp_store_cpu_info(cpu); |
174 | ||
08e875c1 CM |
175 | /* |
176 | * OK, now it's safe to let the boot CPU continue. Wait for | |
177 | * the CPU migration code to notice that the CPU is online | |
178 | * before we continue. | |
179 | */ | |
180 | set_cpu_online(cpu, true); | |
b3770b32 | 181 | complete(&cpu_running); |
08e875c1 | 182 | |
d8ed442a | 183 | local_dbg_enable(); |
53ae3acd | 184 | local_irq_enable(); |
b3bf6aa7 | 185 | local_async_enable(); |
53ae3acd | 186 | |
08e875c1 CM |
187 | /* |
188 | * OK, it's off to the idle thread for us | |
189 | */ | |
0087298f | 190 | cpu_startup_entry(CPUHP_ONLINE); |
08e875c1 CM |
191 | } |
192 | ||
9327e2c6 MR |
193 | #ifdef CONFIG_HOTPLUG_CPU |
194 | static int op_cpu_disable(unsigned int cpu) | |
195 | { | |
196 | /* | |
197 | * If we don't have a cpu_die method, abort before we reach the point | |
198 | * of no return. CPU0 may not have an cpu_ops, so test for it. | |
199 | */ | |
200 | if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die) | |
201 | return -EOPNOTSUPP; | |
202 | ||
203 | /* | |
204 | * We may need to abort a hot unplug for some other mechanism-specific | |
205 | * reason. | |
206 | */ | |
207 | if (cpu_ops[cpu]->cpu_disable) | |
208 | return cpu_ops[cpu]->cpu_disable(cpu); | |
209 | ||
210 | return 0; | |
211 | } | |
212 | ||
213 | /* | |
214 | * __cpu_disable runs on the processor to be shutdown. | |
215 | */ | |
216 | int __cpu_disable(void) | |
217 | { | |
218 | unsigned int cpu = smp_processor_id(); | |
219 | int ret; | |
220 | ||
221 | ret = op_cpu_disable(cpu); | |
222 | if (ret) | |
223 | return ret; | |
224 | ||
225 | /* | |
226 | * Take this CPU offline. Once we clear this, we can't return, | |
227 | * and we must not schedule until we're ready to give up the cpu. | |
228 | */ | |
229 | set_cpu_online(cpu, false); | |
230 | ||
231 | /* | |
232 | * OK - migrate IRQs away from this CPU | |
233 | */ | |
234 | migrate_irqs(); | |
235 | ||
236 | /* | |
237 | * Remove this CPU from the vm mask set of all processes. | |
238 | */ | |
239 | clear_tasks_mm_cpumask(cpu); | |
240 | ||
241 | return 0; | |
242 | } | |
243 | ||
c814ca02 AC |
244 | static int op_cpu_kill(unsigned int cpu) |
245 | { | |
246 | /* | |
247 | * If we have no means of synchronising with the dying CPU, then assume | |
248 | * that it is really dead. We can only wait for an arbitrary length of | |
249 | * time and hope that it's dead, so let's skip the wait and just hope. | |
250 | */ | |
251 | if (!cpu_ops[cpu]->cpu_kill) | |
6b99c68c | 252 | return 0; |
c814ca02 AC |
253 | |
254 | return cpu_ops[cpu]->cpu_kill(cpu); | |
255 | } | |
256 | ||
9327e2c6 MR |
257 | /* |
258 | * called on the thread which is asking for a CPU to be shutdown - | |
259 | * waits until shutdown has completed, or it is timed out. | |
260 | */ | |
261 | void __cpu_die(unsigned int cpu) | |
262 | { | |
6b99c68c MR |
263 | int err; |
264 | ||
05981277 | 265 | if (!cpu_wait_death(cpu, 5)) { |
9327e2c6 MR |
266 | pr_crit("CPU%u: cpu didn't die\n", cpu); |
267 | return; | |
268 | } | |
269 | pr_notice("CPU%u: shutdown\n", cpu); | |
c814ca02 AC |
270 | |
271 | /* | |
272 | * Now that the dying CPU is beyond the point of no return w.r.t. | |
273 | * in-kernel synchronisation, try to get the firwmare to help us to | |
274 | * verify that it has really left the kernel before we consider | |
275 | * clobbering anything it might still be using. | |
276 | */ | |
6b99c68c MR |
277 | err = op_cpu_kill(cpu); |
278 | if (err) | |
279 | pr_warn("CPU%d may not have shut down cleanly: %d\n", | |
280 | cpu, err); | |
9327e2c6 MR |
281 | } |
282 | ||
283 | /* | |
284 | * Called from the idle thread for the CPU which has been shutdown. | |
285 | * | |
286 | * Note that we disable IRQs here, but do not re-enable them | |
287 | * before returning to the caller. This is also the behaviour | |
288 | * of the other hotplug-cpu capable cores, so presumably coming | |
289 | * out of idle fixes this. | |
290 | */ | |
291 | void cpu_die(void) | |
292 | { | |
293 | unsigned int cpu = smp_processor_id(); | |
294 | ||
295 | idle_task_exit(); | |
296 | ||
297 | local_irq_disable(); | |
298 | ||
299 | /* Tell __cpu_die() that this CPU is now safe to dispose of */ | |
05981277 | 300 | (void)cpu_report_death(); |
9327e2c6 MR |
301 | |
302 | /* | |
303 | * Actually shutdown the CPU. This must never fail. The specific hotplug | |
304 | * mechanism must perform all required cache maintenance to ensure that | |
305 | * no dirty lines are lost in the process of shutting down the CPU. | |
306 | */ | |
307 | cpu_ops[cpu]->cpu_die(cpu); | |
308 | ||
309 | BUG(); | |
310 | } | |
311 | #endif | |
312 | ||
08e875c1 CM |
313 | void __init smp_cpus_done(unsigned int max_cpus) |
314 | { | |
326b16db | 315 | pr_info("SMP: Total of %d processors activated.\n", num_online_cpus()); |
137650aa | 316 | do_post_cpus_up_work(); |
08e875c1 CM |
317 | } |
318 | ||
319 | void __init smp_prepare_boot_cpu(void) | |
320 | { | |
71586276 | 321 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
08e875c1 CM |
322 | } |
323 | ||
0f078336 LP |
324 | static u64 __init of_get_cpu_mpidr(struct device_node *dn) |
325 | { | |
326 | const __be32 *cell; | |
327 | u64 hwid; | |
328 | ||
329 | /* | |
330 | * A cpu node with missing "reg" property is | |
331 | * considered invalid to build a cpu_logical_map | |
332 | * entry. | |
333 | */ | |
334 | cell = of_get_property(dn, "reg", NULL); | |
335 | if (!cell) { | |
336 | pr_err("%s: missing reg property\n", dn->full_name); | |
337 | return INVALID_HWID; | |
338 | } | |
339 | ||
340 | hwid = of_read_number(cell, of_n_addr_cells(dn)); | |
341 | /* | |
342 | * Non affinity bits must be set to 0 in the DT | |
343 | */ | |
344 | if (hwid & ~MPIDR_HWID_BITMASK) { | |
345 | pr_err("%s: invalid reg property\n", dn->full_name); | |
346 | return INVALID_HWID; | |
347 | } | |
348 | return hwid; | |
349 | } | |
350 | ||
351 | /* | |
352 | * Duplicate MPIDRs are a recipe for disaster. Scan all initialized | |
353 | * entries and check for duplicates. If any is found just ignore the | |
354 | * cpu. cpu_logical_map was initialized to INVALID_HWID to avoid | |
355 | * matching valid MPIDR values. | |
356 | */ | |
357 | static bool __init is_mpidr_duplicate(unsigned int cpu, u64 hwid) | |
358 | { | |
359 | unsigned int i; | |
360 | ||
361 | for (i = 1; (i < cpu) && (i < NR_CPUS); i++) | |
362 | if (cpu_logical_map(i) == hwid) | |
363 | return true; | |
364 | return false; | |
365 | } | |
366 | ||
819a8826 LP |
367 | /* |
368 | * Initialize cpu operations for a logical cpu and | |
369 | * set it in the possible mask on success | |
370 | */ | |
371 | static int __init smp_cpu_setup(int cpu) | |
372 | { | |
373 | if (cpu_read_ops(cpu)) | |
374 | return -ENODEV; | |
375 | ||
376 | if (cpu_ops[cpu]->cpu_init(cpu)) | |
377 | return -ENODEV; | |
378 | ||
379 | set_cpu_possible(cpu, true); | |
380 | ||
381 | return 0; | |
382 | } | |
383 | ||
0f078336 LP |
384 | static bool bootcpu_valid __initdata; |
385 | static unsigned int cpu_count = 1; | |
386 | ||
387 | #ifdef CONFIG_ACPI | |
388 | /* | |
389 | * acpi_map_gic_cpu_interface - parse processor MADT entry | |
390 | * | |
391 | * Carry out sanity checks on MADT processor entry and initialize | |
392 | * cpu_logical_map on success | |
393 | */ | |
394 | static void __init | |
395 | acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor) | |
396 | { | |
397 | u64 hwid = processor->arm_mpidr; | |
398 | ||
399 | if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) { | |
400 | pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid); | |
401 | return; | |
402 | } | |
403 | ||
404 | if (!(processor->flags & ACPI_MADT_ENABLED)) { | |
405 | pr_err("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid); | |
406 | return; | |
407 | } | |
408 | ||
409 | if (is_mpidr_duplicate(cpu_count, hwid)) { | |
410 | pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid); | |
411 | return; | |
412 | } | |
413 | ||
414 | /* Check if GICC structure of boot CPU is available in the MADT */ | |
415 | if (cpu_logical_map(0) == hwid) { | |
416 | if (bootcpu_valid) { | |
417 | pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n", | |
418 | hwid); | |
419 | return; | |
420 | } | |
421 | bootcpu_valid = true; | |
422 | return; | |
423 | } | |
424 | ||
425 | if (cpu_count >= NR_CPUS) | |
426 | return; | |
427 | ||
428 | /* map the logical cpu id to cpu MPIDR */ | |
429 | cpu_logical_map(cpu_count) = hwid; | |
430 | ||
431 | cpu_count++; | |
432 | } | |
433 | ||
434 | static int __init | |
435 | acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header, | |
436 | const unsigned long end) | |
437 | { | |
438 | struct acpi_madt_generic_interrupt *processor; | |
439 | ||
440 | processor = (struct acpi_madt_generic_interrupt *)header; | |
441 | if (BAD_MADT_ENTRY(processor, end)) | |
442 | return -EINVAL; | |
443 | ||
444 | acpi_table_print_madt_entry(header); | |
445 | ||
446 | acpi_map_gic_cpu_interface(processor); | |
447 | ||
448 | return 0; | |
449 | } | |
450 | #else | |
451 | #define acpi_table_parse_madt(...) do { } while (0) | |
452 | #endif | |
453 | ||
08e875c1 | 454 | /* |
4c7aa002 JM |
455 | * Enumerate the possible CPU set from the device tree and build the |
456 | * cpu logical map array containing MPIDR values related to logical | |
457 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
08e875c1 | 458 | */ |
0f078336 | 459 | void __init of_parse_and_init_cpus(void) |
08e875c1 | 460 | { |
08e875c1 | 461 | struct device_node *dn = NULL; |
08e875c1 CM |
462 | |
463 | while ((dn = of_find_node_by_type(dn, "cpu"))) { | |
0f078336 | 464 | u64 hwid = of_get_cpu_mpidr(dn); |
4c7aa002 | 465 | |
0f078336 | 466 | if (hwid == INVALID_HWID) |
4c7aa002 | 467 | goto next; |
4c7aa002 | 468 | |
0f078336 LP |
469 | if (is_mpidr_duplicate(cpu_count, hwid)) { |
470 | pr_err("%s: duplicate cpu reg properties in the DT\n", | |
471 | dn->full_name); | |
4c7aa002 JM |
472 | goto next; |
473 | } | |
474 | ||
4c7aa002 JM |
475 | /* |
476 | * The numbering scheme requires that the boot CPU | |
477 | * must be assigned logical id 0. Record it so that | |
478 | * the logical map built from DT is validated and can | |
479 | * be used. | |
480 | */ | |
481 | if (hwid == cpu_logical_map(0)) { | |
482 | if (bootcpu_valid) { | |
483 | pr_err("%s: duplicate boot cpu reg property in DT\n", | |
484 | dn->full_name); | |
485 | goto next; | |
486 | } | |
487 | ||
488 | bootcpu_valid = true; | |
489 | ||
490 | /* | |
491 | * cpu_logical_map has already been | |
492 | * initialized and the boot cpu doesn't need | |
493 | * the enable-method so continue without | |
494 | * incrementing cpu. | |
495 | */ | |
496 | continue; | |
497 | } | |
498 | ||
0f078336 | 499 | if (cpu_count >= NR_CPUS) |
08e875c1 CM |
500 | goto next; |
501 | ||
4c7aa002 | 502 | pr_debug("cpu logical map 0x%llx\n", hwid); |
0f078336 | 503 | cpu_logical_map(cpu_count) = hwid; |
08e875c1 | 504 | next: |
0f078336 | 505 | cpu_count++; |
08e875c1 | 506 | } |
0f078336 LP |
507 | } |
508 | ||
509 | /* | |
510 | * Enumerate the possible CPU set from the device tree or ACPI and build the | |
511 | * cpu logical map array containing MPIDR values related to logical | |
512 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
513 | */ | |
514 | void __init smp_init_cpus(void) | |
515 | { | |
516 | int i; | |
517 | ||
518 | if (acpi_disabled) | |
519 | of_parse_and_init_cpus(); | |
520 | else | |
521 | /* | |
522 | * do a walk of MADT to determine how many CPUs | |
523 | * we have including disabled CPUs, and get information | |
524 | * we need for SMP init | |
525 | */ | |
526 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
527 | acpi_parse_gic_cpu_interface, 0); | |
08e875c1 | 528 | |
0f078336 LP |
529 | if (cpu_count > NR_CPUS) |
530 | pr_warn("no. of cores (%d) greater than configured maximum of %d - clipping\n", | |
531 | cpu_count, NR_CPUS); | |
4c7aa002 JM |
532 | |
533 | if (!bootcpu_valid) { | |
0f078336 | 534 | pr_err("missing boot CPU MPIDR, not enabling secondaries\n"); |
4c7aa002 JM |
535 | return; |
536 | } | |
537 | ||
538 | /* | |
819a8826 LP |
539 | * We need to set the cpu_logical_map entries before enabling |
540 | * the cpus so that cpu processor description entries (DT cpu nodes | |
541 | * and ACPI MADT entries) can be retrieved by matching the cpu hwid | |
542 | * with entries in cpu_logical_map while initializing the cpus. | |
543 | * If the cpu set-up fails, invalidate the cpu_logical_map entry. | |
4c7aa002 | 544 | */ |
819a8826 LP |
545 | for (i = 1; i < NR_CPUS; i++) { |
546 | if (cpu_logical_map(i) != INVALID_HWID) { | |
547 | if (smp_cpu_setup(i)) | |
548 | cpu_logical_map(i) = INVALID_HWID; | |
549 | } | |
550 | } | |
08e875c1 CM |
551 | } |
552 | ||
553 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
554 | { | |
cd1aebf5 MR |
555 | int err; |
556 | unsigned int cpu, ncores = num_possible_cpus(); | |
08e875c1 | 557 | |
f6e763b9 MB |
558 | init_cpu_topology(); |
559 | ||
560 | smp_store_cpu_info(smp_processor_id()); | |
561 | ||
08e875c1 CM |
562 | /* |
563 | * are we trying to boot more cores than exist? | |
564 | */ | |
565 | if (max_cpus > ncores) | |
566 | max_cpus = ncores; | |
567 | ||
d329de3f MZ |
568 | /* Don't bother if we're effectively UP */ |
569 | if (max_cpus <= 1) | |
570 | return; | |
571 | ||
08e875c1 CM |
572 | /* |
573 | * Initialise the present map (which describes the set of CPUs | |
574 | * actually populated at the present time) and release the | |
575 | * secondaries from the bootloader. | |
d329de3f MZ |
576 | * |
577 | * Make sure we online at most (max_cpus - 1) additional CPUs. | |
08e875c1 | 578 | */ |
d329de3f | 579 | max_cpus--; |
08e875c1 CM |
580 | for_each_possible_cpu(cpu) { |
581 | if (max_cpus == 0) | |
582 | break; | |
583 | ||
d329de3f MZ |
584 | if (cpu == smp_processor_id()) |
585 | continue; | |
586 | ||
cd1aebf5 | 587 | if (!cpu_ops[cpu]) |
08e875c1 CM |
588 | continue; |
589 | ||
cd1aebf5 | 590 | err = cpu_ops[cpu]->cpu_prepare(cpu); |
d329de3f MZ |
591 | if (err) |
592 | continue; | |
08e875c1 CM |
593 | |
594 | set_cpu_present(cpu, true); | |
595 | max_cpus--; | |
596 | } | |
08e875c1 CM |
597 | } |
598 | ||
36310736 | 599 | void (*__smp_cross_call)(const struct cpumask *, unsigned int); |
08e875c1 CM |
600 | |
601 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
602 | { | |
45ed695a | 603 | __smp_cross_call = fn; |
08e875c1 CM |
604 | } |
605 | ||
45ed695a NP |
606 | static const char *ipi_types[NR_IPI] __tracepoint_string = { |
607 | #define S(x,s) [x] = s | |
08e875c1 CM |
608 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), |
609 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
08e875c1 | 610 | S(IPI_CPU_STOP, "CPU stop interrupts"), |
1f85008e | 611 | S(IPI_TIMER, "Timer broadcast interrupts"), |
eb631bb5 | 612 | S(IPI_IRQ_WORK, "IRQ work interrupts"), |
08e875c1 CM |
613 | }; |
614 | ||
45ed695a NP |
615 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) |
616 | { | |
617 | trace_ipi_raise(target, ipi_types[ipinr]); | |
618 | __smp_cross_call(target, ipinr); | |
619 | } | |
620 | ||
08e875c1 CM |
621 | void show_ipi_list(struct seq_file *p, int prec) |
622 | { | |
623 | unsigned int cpu, i; | |
624 | ||
625 | for (i = 0; i < NR_IPI; i++) { | |
45ed695a | 626 | seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, |
08e875c1 | 627 | prec >= 4 ? " " : ""); |
67317c26 | 628 | for_each_online_cpu(cpu) |
08e875c1 CM |
629 | seq_printf(p, "%10u ", |
630 | __get_irq_stat(cpu, ipi_irqs[i])); | |
631 | seq_printf(p, " %s\n", ipi_types[i]); | |
632 | } | |
633 | } | |
634 | ||
635 | u64 smp_irq_stat_cpu(unsigned int cpu) | |
636 | { | |
637 | u64 sum = 0; | |
638 | int i; | |
639 | ||
640 | for (i = 0; i < NR_IPI; i++) | |
641 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
642 | ||
643 | return sum; | |
644 | } | |
645 | ||
45ed695a NP |
646 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
647 | { | |
648 | smp_cross_call(mask, IPI_CALL_FUNC); | |
649 | } | |
650 | ||
651 | void arch_send_call_function_single_ipi(int cpu) | |
652 | { | |
0aaf0dae | 653 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); |
45ed695a NP |
654 | } |
655 | ||
656 | #ifdef CONFIG_IRQ_WORK | |
657 | void arch_irq_work_raise(void) | |
658 | { | |
659 | if (__smp_cross_call) | |
660 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); | |
661 | } | |
662 | #endif | |
663 | ||
08e875c1 CM |
664 | static DEFINE_RAW_SPINLOCK(stop_lock); |
665 | ||
666 | /* | |
667 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
668 | */ | |
669 | static void ipi_cpu_stop(unsigned int cpu) | |
670 | { | |
671 | if (system_state == SYSTEM_BOOTING || | |
672 | system_state == SYSTEM_RUNNING) { | |
673 | raw_spin_lock(&stop_lock); | |
674 | pr_crit("CPU%u: stopping\n", cpu); | |
675 | dump_stack(); | |
676 | raw_spin_unlock(&stop_lock); | |
677 | } | |
678 | ||
679 | set_cpu_online(cpu, false); | |
680 | ||
08e875c1 CM |
681 | local_irq_disable(); |
682 | ||
683 | while (1) | |
684 | cpu_relax(); | |
685 | } | |
686 | ||
687 | /* | |
688 | * Main handler for inter-processor interrupts | |
689 | */ | |
690 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
691 | { | |
692 | unsigned int cpu = smp_processor_id(); | |
693 | struct pt_regs *old_regs = set_irq_regs(regs); | |
694 | ||
45ed695a NP |
695 | if ((unsigned)ipinr < NR_IPI) { |
696 | trace_ipi_entry(ipi_types[ipinr]); | |
697 | __inc_irq_stat(cpu, ipi_irqs[ipinr]); | |
698 | } | |
08e875c1 CM |
699 | |
700 | switch (ipinr) { | |
701 | case IPI_RESCHEDULE: | |
702 | scheduler_ipi(); | |
703 | break; | |
704 | ||
705 | case IPI_CALL_FUNC: | |
706 | irq_enter(); | |
707 | generic_smp_call_function_interrupt(); | |
708 | irq_exit(); | |
709 | break; | |
710 | ||
08e875c1 CM |
711 | case IPI_CPU_STOP: |
712 | irq_enter(); | |
713 | ipi_cpu_stop(cpu); | |
714 | irq_exit(); | |
715 | break; | |
716 | ||
1f85008e LP |
717 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
718 | case IPI_TIMER: | |
719 | irq_enter(); | |
720 | tick_receive_broadcast(); | |
721 | irq_exit(); | |
722 | break; | |
723 | #endif | |
724 | ||
eb631bb5 LB |
725 | #ifdef CONFIG_IRQ_WORK |
726 | case IPI_IRQ_WORK: | |
727 | irq_enter(); | |
728 | irq_work_run(); | |
729 | irq_exit(); | |
730 | break; | |
731 | #endif | |
732 | ||
08e875c1 CM |
733 | default: |
734 | pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); | |
735 | break; | |
736 | } | |
45ed695a NP |
737 | |
738 | if ((unsigned)ipinr < NR_IPI) | |
739 | trace_ipi_exit(ipi_types[ipinr]); | |
08e875c1 CM |
740 | set_irq_regs(old_regs); |
741 | } | |
742 | ||
743 | void smp_send_reschedule(int cpu) | |
744 | { | |
745 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); | |
746 | } | |
747 | ||
1f85008e LP |
748 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
749 | void tick_broadcast(const struct cpumask *mask) | |
750 | { | |
751 | smp_cross_call(mask, IPI_TIMER); | |
752 | } | |
753 | #endif | |
754 | ||
08e875c1 CM |
755 | void smp_send_stop(void) |
756 | { | |
757 | unsigned long timeout; | |
758 | ||
759 | if (num_online_cpus() > 1) { | |
760 | cpumask_t mask; | |
761 | ||
762 | cpumask_copy(&mask, cpu_online_mask); | |
434ed7f4 | 763 | cpumask_clear_cpu(smp_processor_id(), &mask); |
08e875c1 CM |
764 | |
765 | smp_cross_call(&mask, IPI_CPU_STOP); | |
766 | } | |
767 | ||
768 | /* Wait up to one second for other CPUs to stop */ | |
769 | timeout = USEC_PER_SEC; | |
770 | while (num_online_cpus() > 1 && timeout--) | |
771 | udelay(1); | |
772 | ||
773 | if (num_online_cpus() > 1) | |
774 | pr_warning("SMP: failed to stop secondary CPUs\n"); | |
775 | } | |
776 | ||
777 | /* | |
778 | * not supported here | |
779 | */ | |
780 | int setup_profiling_timer(unsigned int multiplier) | |
781 | { | |
782 | return -EINVAL; | |
783 | } |