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Merge tag 'kvm-x86-generic-6.8' of https://github.com/kvm-x86/linux into HEAD
[thirdparty/kernel/stable.git] / arch / arm64 / kvm / vgic / vgic.h
CommitLineData
caab277b 1/* SPDX-License-Identifier: GPL-2.0-only */
64a959d6
CD		 2/*
3 * Copyright (C) 2015, 2016 ARM Ltd.
64a959d6
CD		 4 */
5#ifndef __KVM_ARM_VGIC_NEW_H__
6#define __KVM_ARM_VGIC_NEW_H__
7
90977732 8#include <linux/irqchip/arm-gic-common.h>
a23eaf93 9#include <asm/kvm_mmu.h>
90977732 10
2b0cda87
MZ		 11#define PRODUCT_ID_KVM 0x4b /* ASCII code K */
12#define IMPLEMENTER_ARM 0x43b
13
e2c1f9ab
EA		 14#define VGIC_ADDR_UNDEF (-1)
15#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
16
fd59ed3b 17#define INTERRUPT_ID_BITS_SPIS 10
33d3bc95 18#define INTERRUPT_ID_BITS_ITS 16
055658bf
AP		 19#define VGIC_PRI_BITS 5
20
0919e84c
MZ		 21#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
22
94574c94
VK		 23#define VGIC_AFFINITY_0_SHIFT 0
24#define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
25#define VGIC_AFFINITY_1_SHIFT 8
26#define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
27#define VGIC_AFFINITY_2_SHIFT 16
28#define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
29#define VGIC_AFFINITY_3_SHIFT 24
30#define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
31
32#define VGIC_AFFINITY_LEVEL(reg, level) \
33 ((((reg) & VGIC_AFFINITY_## level ##_MASK) \
34 >> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
35
36/*
37 * The Userspace encodes the affinity differently from the MPIDR,
38 * Below macro converts vgic userspace format to MPIDR reg format.
39 */
40#define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \
41 VGIC_AFFINITY_LEVEL(val, 1) | \
42 VGIC_AFFINITY_LEVEL(val, 2) | \
43 VGIC_AFFINITY_LEVEL(val, 3))
44
d017d7b0 45/*
72ef5e52 46 * As per Documentation/virt/kvm/devices/arm-vgic-v3.rst,
d017d7b0
VK		 47 * below macros are defined for CPUREG encoding.
48 */
49#define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK 0x000000000000c000
50#define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT 14
51#define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK 0x0000000000003800
52#define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT 11
53#define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK 0x0000000000000780
54#define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT 7
55#define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK 0x0000000000000078
56#define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT 3
57#define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK 0x0000000000000007
58#define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT 0
59
60#define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \
61 KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \
62 KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \
63 KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \
64 KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)
65
ea1ad53e 66/*
72ef5e52 67 * As per Documentation/virt/kvm/devices/arm-vgic-its.rst,
ea1ad53e
EA		 68 * below macros are defined for ITS table entry encoding.
69 */
70#define KVM_ITS_CTE_VALID_SHIFT 63
71#define KVM_ITS_CTE_VALID_MASK BIT_ULL(63)
72#define KVM_ITS_CTE_RDBASE_SHIFT 16
73#define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0)
eff484e0
EA		 74#define KVM_ITS_ITE_NEXT_SHIFT 48
75#define KVM_ITS_ITE_PINTID_SHIFT 16
76#define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16)
77#define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0)
57a9a117
EA		 78#define KVM_ITS_DTE_VALID_SHIFT 63
79#define KVM_ITS_DTE_VALID_MASK BIT_ULL(63)
80#define KVM_ITS_DTE_NEXT_SHIFT 49
81#define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49)
82#define KVM_ITS_DTE_ITTADDR_SHIFT 5
83#define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5)
84#define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0)
85#define KVM_ITS_L1E_VALID_MASK BIT_ULL(63)
86/* we only support 64 kB translation table page size */
87#define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16)
ea1ad53e 88
04c11093
EA		 89#define KVM_VGIC_V3_RDIST_INDEX_MASK GENMASK_ULL(11, 0)
90#define KVM_VGIC_V3_RDIST_FLAGS_MASK GENMASK_ULL(15, 12)
91#define KVM_VGIC_V3_RDIST_FLAGS_SHIFT 12
92#define KVM_VGIC_V3_RDIST_BASE_MASK GENMASK_ULL(51, 16)
93#define KVM_VGIC_V3_RDIST_COUNT_MASK GENMASK_ULL(63, 52)
94#define KVM_VGIC_V3_RDIST_COUNT_SHIFT 52
95
dc961e53
JH		 96#ifdef CONFIG_DEBUG_SPINLOCK
97#define DEBUG_SPINLOCK_BUG_ON(p) BUG_ON(p)
98#else
99#define DEBUG_SPINLOCK_BUG_ON(p)
100#endif
101
49a1a2c7
MZ		 102static inline u32 vgic_get_implementation_rev(struct kvm_vcpu *vcpu)
103{
104 return vcpu->kvm->arch.vgic.implementation_rev;
105}
106
62b06f8f 107/* Requires the irq_lock to be held by the caller. */
8694e4da
CD		 108static inline bool irq_is_pending(struct vgic_irq *irq)
109{
110 if (irq->config == VGIC_CONFIG_EDGE)
111 return irq->pending_latch;
112 else
113 return irq->pending_latch || irq->line_level;
114}
115
e40cc57b
CD		 116static inline bool vgic_irq_is_mapped_level(struct vgic_irq *irq)
117{
118 return irq->config == VGIC_CONFIG_LEVEL && irq->hw;
119}
120
53692908
MZ		 121static inline int vgic_irq_get_lr_count(struct vgic_irq *irq)
122{
123 /* Account for the active state as an interrupt */
124 if (vgic_irq_is_sgi(irq->intid) && irq->source)
125 return hweight8(irq->source) + irq->active;
126
127 return irq_is_pending(irq) || irq->active;
128}
129
130static inline bool vgic_irq_is_multi_sgi(struct vgic_irq *irq)
131{
132 return vgic_irq_get_lr_count(irq) > 1;
133}
134
a23eaf93
GS		 135static inline int vgic_write_guest_lock(struct kvm *kvm, gpa_t gpa,
136 const void *data, unsigned long len)
137{
138 struct vgic_dist *dist = &kvm->arch.vgic;
139 int ret;
140
141 dist->table_write_in_progress = true;
142 ret = kvm_write_guest_lock(kvm, gpa, data, len);
143 dist->table_write_in_progress = false;
144
145 return ret;
146}
147
6d56111c
CD		 148/*
149 * This struct provides an intermediate representation of the fields contained
150 * in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC
151 * state to userspace can generate either GICv2 or GICv3 CPU interface
152 * registers regardless of the hardware backed GIC used.
153 */
e4823a7a 154struct vgic_vmcr {
28232a43
CD		 155 u32 grpen0;
156 u32 grpen1;
157
158 u32 ackctl;
159 u32 fiqen;
160 u32 cbpr;
161 u32 eoim;
162
e4823a7a
AP		 163 u32 abpr;
164 u32 bpr;
6d56111c
CD		 165 u32 pmr; /* Priority mask field in the GICC_PMR and
166 * ICC_PMR_EL1 priority field format */
e4823a7a
AP		 167};
168
94574c94
VK		 169struct vgic_reg_attr {
170 struct kvm_vcpu *vcpu;
171 gpa_t addr;
172};
173
174int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
175 struct vgic_reg_attr *reg_attr);
176int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
177 struct vgic_reg_attr *reg_attr);
178const struct vgic_register_region *
179vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
180 gpa_t addr, int len);
64a959d6
CD		 181struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
182 u32 intid);
1bb3691d 183void __vgic_put_lpi_locked(struct kvm *kvm, struct vgic_irq *irq);
5dd4b924 184void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
e40cc57b 185bool vgic_get_phys_line_level(struct vgic_irq *irq);
df635c5b 186void vgic_irq_set_phys_pending(struct vgic_irq *irq, bool pending);
e40cc57b 187void vgic_irq_set_phys_active(struct vgic_irq *irq, bool active);
006df0f3
CD		 188bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq,
189 unsigned long flags);
2b0cda87 190void vgic_kick_vcpus(struct kvm *kvm);
3134cc8b
MZ		 191void vgic_irq_handle_resampling(struct vgic_irq *irq,
192 bool lr_deactivated, bool lr_pending);
64a959d6 193
f25c5e4d
RK		 194int vgic_check_iorange(struct kvm *kvm, phys_addr_t ioaddr,
195 phys_addr_t addr, phys_addr_t alignment,
196 phys_addr_t size);
197
140b086d
MZ		 198void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
199void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
200void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
201void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
f94591e2 202int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
c3199f28
CD		 203int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
204 int offset, u32 *val);
878c569e
AP		 205int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
206 int offset, u32 *val);
e4823a7a
AP		 207void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
208void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
ad275b8b 209void vgic_v2_enable(struct kvm_vcpu *vcpu);
90977732 210int vgic_v2_probe(const struct gic_kvm_info *info);
b0442ee2 211int vgic_v2_map_resources(struct kvm *kvm);
fb848db3
AP		 212int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
213 enum vgic_type);
140b086d 214
5b0d2cc2 215void vgic_v2_init_lrs(void);
328e5664
CD		 216void vgic_v2_load(struct kvm_vcpu *vcpu);
217void vgic_v2_put(struct kvm_vcpu *vcpu);
5eeaf10e 218void vgic_v2_vmcr_sync(struct kvm_vcpu *vcpu);
5b0d2cc2 219
75174ba6
CD		 220void vgic_v2_save_state(struct kvm_vcpu *vcpu);
221void vgic_v2_restore_state(struct kvm_vcpu *vcpu);
222
d97594e6
MZ		 223static inline void vgic_get_irq_kref(struct vgic_irq *irq)
224{
225 if (irq->intid < VGIC_MIN_LPI)
226 return;
227
228 kref_get(&irq->refcount);
229}
230
59529f69
MZ		 231void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
232void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
233void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
234void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
e4823a7a
AP		 235void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
236void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
ad275b8b 237void vgic_v3_enable(struct kvm_vcpu *vcpu);
90977732 238int vgic_v3_probe(const struct gic_kvm_info *info);
b0442ee2 239int vgic_v3_map_resources(struct kvm *kvm);
44de9d68 240int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq);
28077125 241int vgic_v3_save_pending_tables(struct kvm *kvm);
04c11093 242int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count);
1aab6f46 243int vgic_register_redist_iodev(struct kvm_vcpu *vcpu);
02e3858f 244void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu);
9a746d75 245bool vgic_v3_check_base(struct kvm *kvm);
7a1ff708 246
328e5664
CD		 247void vgic_v3_load(struct kvm_vcpu *vcpu);
248void vgic_v3_put(struct kvm_vcpu *vcpu);
5eeaf10e 249void vgic_v3_vmcr_sync(struct kvm_vcpu *vcpu);
328e5664 250
59c5ab40 251bool vgic_has_its(struct kvm *kvm);
0e4e82f1 252int kvm_vgic_register_its_device(void);
33d3bc95 253void vgic_enable_lpis(struct kvm_vcpu *vcpu);
96085b94 254void vgic_flush_pending_lpis(struct kvm_vcpu *vcpu);
2891a7df 255int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
94574c94
VK		 256int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
257int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
258 int offset, u32 *val);
259int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
260 int offset, u32 *val);
db25081e
MZ		 261int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu,
262 struct kvm_device_attr *attr, bool is_write);
b61fc085 263int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr);
e96a006c 264int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
38cf0bb7 265 u32 intid, u32 *val);
42c8870f 266int kvm_register_vgic_device(unsigned long type);
5fb247d7
VK		 267void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
268void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
ad275b8b
EA		 269int vgic_lazy_init(struct kvm *kvm);
270int vgic_init(struct kvm *kvm);
c86c7721 271
929f45e3
GKH		 272void vgic_debug_init(struct kvm *kvm);
273void vgic_debug_destroy(struct kvm *kvm);
10f92c4c 274
50f5bd57
CD		 275static inline int vgic_v3_max_apr_idx(struct kvm_vcpu *vcpu)
276{
277 struct vgic_cpu *cpu_if = &vcpu->arch.vgic_cpu;
278
279 /*
280 * num_pri_bits are initialized with HW supported values.
281 * We can rely safely on num_pri_bits even if VM has not
282 * restored ICC_CTLR_EL1 before restoring APnR registers.
283 */
284 switch (cpu_if->num_pri_bits) {
285 case 7: return 3;
286 case 6: return 1;
287 default: return 0;
288 }
289}
290
dc524619
EA		 291static inline bool
292vgic_v3_redist_region_full(struct vgic_redist_region *region)
293{
294 if (!region->count)
295 return false;
296
297 return (region->free_index >= region->count);
298}
299
300struct vgic_redist_region *vgic_v3_rdist_free_slot(struct list_head *rdregs);
301
028bf278
EA		 302static inline size_t
303vgic_v3_rd_region_size(struct kvm *kvm, struct vgic_redist_region *rdreg)
304{
305 if (!rdreg->count)
306 return atomic_read(&kvm->online_vcpus) * KVM_VGIC_V3_REDIST_SIZE;
307 else
308 return rdreg->count * KVM_VGIC_V3_REDIST_SIZE;
309}
04c11093
EA		 310
311struct vgic_redist_region *vgic_v3_rdist_region_from_index(struct kvm *kvm,
312 u32 index);
e5a35635 313void vgic_v3_free_redist_region(struct vgic_redist_region *rdreg);
04c11093 314
028bf278
EA		 315bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size);
316
ccc27bf5
EA		 317static inline bool vgic_dist_overlap(struct kvm *kvm, gpa_t base, size_t size)
318{
319 struct vgic_dist *d = &kvm->arch.vgic;
320
321 return (base + size > d->vgic_dist_base) &&
322 (base < d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE);
323}
324
94828468 325bool vgic_lpis_enabled(struct kvm_vcpu *vcpu);
e294cb3a 326int vgic_copy_lpi_list(struct kvm *kvm, struct kvm_vcpu *vcpu, u32 **intid_ptr);
bebfd2a2
MZ		 327int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its,
328 u32 devid, u32 eventid, struct vgic_irq **irq);
329struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi);
86a7dae8 330int vgic_its_inject_cached_translation(struct kvm *kvm, struct kvm_msi *msi);
24cab82c
MZ		 331void vgic_lpi_translation_cache_init(struct kvm *kvm);
332void vgic_lpi_translation_cache_destroy(struct kvm *kvm);
7d825fd6 333void vgic_its_invalidate_cache(struct kvm *kvm);
bebfd2a2 334
4645d11f
MZ		 335/* GICv4.1 MMIO interface */
336int vgic_its_inv_lpi(struct kvm *kvm, struct vgic_irq *irq);
337int vgic_its_invall(struct kvm_vcpu *vcpu);
338
e7c48059 339bool vgic_supports_direct_msis(struct kvm *kvm);
74fe55dc
MZ		 340int vgic_v4_init(struct kvm *kvm);
341void vgic_v4_teardown(struct kvm *kvm);
bacf2c60 342void vgic_v4_configure_vsgis(struct kvm *kvm);
80317fe4 343void vgic_v4_get_vlpi_state(struct vgic_irq *irq, bool *val);
ef369168 344int vgic_v4_request_vpe_irq(struct kvm_vcpu *vcpu, int irq);
e7c48059 345
64a959d6 346#endif
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git