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72a087e0 WD |
1 | /* |
2 | * Copyright (C) 2005-2006 Atmel Corporation | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
72a087e0 WD |
5 | */ |
6 | #include <common.h> | |
7 | #include <command.h> | |
8 | ||
9 | #include <asm/io.h> | |
10 | #include <asm/sections.h> | |
11 | #include <asm/sysreg.h> | |
12 | ||
df548d3c | 13 | #include <asm/arch/clk.h> |
5d73bc7a | 14 | #include <asm/arch/hardware.h> |
72a087e0 WD |
15 | |
16 | #include "hsmc3.h" | |
df548d3c HS |
17 | |
18 | /* Sanity checks */ | |
6d0f6bcf JCPV |
19 | #if (CONFIG_SYS_CLKDIV_CPU > CONFIG_SYS_CLKDIV_HSB) \ |
20 | || (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBA) \ | |
21 | || (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBB) | |
df548d3c HS |
22 | # error Constraint fCPU >= fHSB >= fPB{A,B} violated |
23 | #endif | |
6d0f6bcf | 24 | #if defined(CONFIG_PLL) && ((CONFIG_SYS_PLL0_MUL < 1) || (CONFIG_SYS_PLL0_DIV < 1)) |
df548d3c HS |
25 | # error Invalid PLL multiplier and/or divider |
26 | #endif | |
72a087e0 WD |
27 | |
28 | DECLARE_GLOBAL_DATA_PTR; | |
29 | ||
aa0ea2a5 | 30 | int arch_cpu_init(void) |
72a087e0 | 31 | { |
72a087e0 | 32 | extern void _evba(void); |
72a087e0 | 33 | |
3d0f8c8f | 34 | gd->arch.cpu_hz = CONFIG_SYS_OSC0_HZ; |
72a087e0 | 35 | |
df548d3c HS |
36 | /* TODO: Move somewhere else, but needs to be run before we |
37 | * increase the clock frequency. */ | |
38 | hsmc3_writel(MODE0, 0x00031103); | |
39 | hsmc3_writel(CYCLE0, 0x000c000d); | |
40 | hsmc3_writel(PULSE0, 0x0b0a0906); | |
41 | hsmc3_writel(SETUP0, 0x00010002); | |
72a087e0 | 42 | |
3ace2527 HS |
43 | clk_init(); |
44 | ||
45 | /* Update the CPU speed according to the PLL configuration */ | |
3d0f8c8f | 46 | gd->arch.cpu_hz = get_cpu_clk_rate(); |
72a087e0 | 47 | |
3ace2527 | 48 | /* Set up the exception handler table and enable exceptions */ |
72a087e0 WD |
49 | sysreg_write(EVBA, (unsigned long)&_evba); |
50 | asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET)); | |
72a087e0 | 51 | |
72a087e0 WD |
52 | return 0; |
53 | } | |
54 | ||
55 | void prepare_to_boot(void) | |
56 | { | |
57 | /* Flush both caches and the write buffer */ | |
58 | asm volatile("cache %0[4], 010\n\t" | |
59 | "cache %0[0], 000\n\t" | |
60 | "sync 0" : : "r"(0) : "memory"); | |
61 | } | |
62 | ||
54841ab5 | 63 | int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
72a087e0 WD |
64 | { |
65 | /* This will reset the CPU core, caches, MMU and all internal busses */ | |
66 | __builtin_mtdr(8, 1 << 13); /* set DC:DBE */ | |
67 | __builtin_mtdr(8, 1 << 30); /* set DC:RES */ | |
68 | ||
69 | /* Flush the pipeline before we declare it a failure */ | |
70 | asm volatile("sub pc, pc, -4"); | |
71 | ||
72 | return -1; | |
73 | } |