[thirdparty/u-boot.git] / arch / avr32 / include / asm / arch-at32ap700x / cacheflush.h

/*
 * Copyright (C) 2006 Atmel Corporation
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __ASM_AVR32_CACHEFLUSH_H
#define __ASM_AVR32_CACHEFLUSH_H

/*
 * Invalidate any cacheline containing virtual address vaddr without
 * writing anything back to memory.
 *
 * Note that this function may corrupt unrelated data structures when
 * applied on buffers that are not cacheline aligned in both ends.
 */
static inline void dcache_invalidate_line(volatile void *vaddr)
{
	asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory");
}

/*
 * Make sure any cacheline containing virtual address vaddr is written
 * to memory.
 */
static inline void dcache_clean_line(volatile void *vaddr)
{
	asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory");
}

/*
 * Make sure any cacheline containing virtual address vaddr is written
 * to memory and then invalidate it.
 */
static inline void dcache_flush_line(volatile void *vaddr)
{
	asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory");
}

/*
 * Invalidate any instruction cacheline containing virtual address
 * vaddr.
 */
static inline void icache_invalidate_line(volatile void *vaddr)
{
	asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory");
}

/*
 * Applies the above functions on all lines that are touched by the
 * specified virtual address range.
 */
void dcache_clean_range(volatile void *start, size_t len);
void icache_invalidate_range(volatile void *start, size_t len);

static inline void dcache_flush_unlocked(void)
{
	asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory");
}

/*
 * Make sure any pending writes are completed before continuing.
 */
#define sync_write_buffer() asm volatile("sync 0" : : : "memory")

#endif /* __ASM_AVR32_CACHEFLUSH_H */
Commit	Line	Data
7b64fef3 WD	1	/*
	2	* Copyright (C) 2006 Atmel Corporation
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
7b64fef3 WD	5	*/
	6	#ifndef __ASM_AVR32_CACHEFLUSH_H
	7	#define __ASM_AVR32_CACHEFLUSH_H
	8
	9	/*
	10	* Invalidate any cacheline containing virtual address vaddr without
	11	* writing anything back to memory.
	12	*
	13	* Note that this function may corrupt unrelated data structures when
	14	* applied on buffers that are not cacheline aligned in both ends.
	15	*/
	16	static inline void dcache_invalidate_line(volatile void *vaddr)
	17	{
	18	asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory");
	19	}
	20
	21	/*
	22	* Make sure any cacheline containing virtual address vaddr is written
	23	* to memory.
	24	*/
	25	static inline void dcache_clean_line(volatile void *vaddr)
	26	{
	27	asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory");
	28	}
	29
	30	/*
	31	* Make sure any cacheline containing virtual address vaddr is written
	32	* to memory and then invalidate it.
	33	*/
	34	static inline void dcache_flush_line(volatile void *vaddr)
	35	{
	36	asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory");
	37	}
	38
	39	/*
	40	* Invalidate any instruction cacheline containing virtual address
	41	* vaddr.
	42	*/
	43	static inline void icache_invalidate_line(volatile void *vaddr)
	44	{
	45	asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory");
	46	}
	47
	48	/*
	49	* Applies the above functions on all lines that are touched by the
	50	* specified virtual address range.
	51	*/
7b64fef3	52	void dcache_clean_range(volatile void *start, size_t len);
7b64fef3 WD	53	void icache_invalidate_range(volatile void *start, size_t len);
	54
	55	static inline void dcache_flush_unlocked(void)
	56	{
	57	asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory");
	58	}
	59
	60	/*
	61	* Make sure any pending writes are completed before continuing.
	62	*/
	63	#define sync_write_buffer() asm volatile("sync 0" : : : "memory")
	64
	65	#endif /* __ASM_AVR32_CACHEFLUSH_H */