[u-boot.git] / arch / avr32 / include / asm / arch-at32ap700x / clk.h

/*
 * Copyright (C) 2006 Atmel Corporation
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __ASM_AVR32_ARCH_CLK_H__
#define __ASM_AVR32_ARCH_CLK_H__

#include <asm/arch/chip-features.h>
#include <asm/arch/portmux.h>

#ifdef CONFIG_PLL
#define PLL0_RATE	((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV)	\
				* CONFIG_SYS_PLL0_MUL)
#define MAIN_CLK_RATE	PLL0_RATE
#else
#define MAIN_CLK_RATE	(CONFIG_SYS_OSC0_HZ)
#endif

static inline unsigned long get_cpu_clk_rate(void)
{
	return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU;
}
static inline unsigned long get_hsb_clk_rate(void)
{
	return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB;
}
static inline unsigned long get_pba_clk_rate(void)
{
	return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA;
}
static inline unsigned long get_pbb_clk_rate(void)
{
	return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB;
}

/* Accessors for specific devices. More will be added as needed. */
static inline unsigned long get_sdram_clk_rate(void)
{
	return get_hsb_clk_rate();
}
#ifdef AT32AP700x_CHIP_HAS_USART
static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
{
	return get_pba_clk_rate();
}
#endif
#ifdef AT32AP700x_CHIP_HAS_MACB
static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
{
	return get_pbb_clk_rate();
}
static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
{
	return get_hsb_clk_rate();
}
#endif
#ifdef AT32AP700x_CHIP_HAS_MMCI
static inline unsigned long get_mci_clk_rate(void)
{
	return get_pbb_clk_rate();
}
#endif
#ifdef AT32AP700x_CHIP_HAS_SPI
static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
{
	return get_pba_clk_rate();
}
#endif
#ifdef AT32AP700x_CHIP_HAS_LCDC
static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
{
	return get_hsb_clk_rate();
}
#endif

extern void clk_init(void);

/* Board code may need the SDRAM base clock as a compile-time constant */
#define SDRAMC_BUS_HZ	(MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB)

/* Generic clock control */
enum gclk_parent {
	GCLK_PARENT_OSC0 = 0,
	GCLK_PARENT_OSC1 = 1,
	GCLK_PARENT_PLL0 = 2,
	GCLK_PARENT_PLL1 = 3,
};

/* Some generic clocks have specific roles */
#define GCLK_DAC_SAMPLE_CLK	6
#define GCLK_LCDC_PIXCLK	7

extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
		unsigned long rate, unsigned long parent_rate);

/**
 * gclk_set_rate - configure and enable a generic clock
 * @id: Which GCLK[id] to enable
 * @parent: Parent clock feeding the GCLK
 * @rate: Target rate of the GCLK in Hz
 *
 * Returns the actual GCLK rate in Hz, after rounding to the nearest
 * supported rate.
 *
 * All three parameters are usually constant, hence the inline.
 */
static inline unsigned long gclk_set_rate(unsigned int id,
		enum gclk_parent parent, unsigned long rate)
{
	unsigned long parent_rate;

	if (id > 7)
		return 0;

	switch (parent) {
	case GCLK_PARENT_OSC0:
		parent_rate = CONFIG_SYS_OSC0_HZ;
		break;
#ifdef CONFIG_SYS_OSC1_HZ
	case GCLK_PARENT_OSC1:
		parent_rate = CONFIG_SYS_OSC1_HZ;
		break;
#endif
#ifdef PLL0_RATE
	case GCLK_PARENT_PLL0:
		parent_rate = PLL0_RATE;
		break;
#endif
#ifdef PLL1_RATE
	case GCLK_PARENT_PLL1:
		parent_rate = PLL1_RATE;
		break;
#endif
	default:
		parent_rate = 0;
		break;
	}

	return __gclk_set_rate(id, parent, rate, parent_rate);
}

/**
 * gclk_enable_output - enable output on a GCLK pin
 * @id: Which GCLK[id] pin to enable
 * @drive_strength: Drive strength of external GCLK pin, if applicable
 */
static inline void gclk_enable_output(unsigned int id,
		unsigned long drive_strength)
{
	switch (id) {
	case 0:
		portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30,
				PORTMUX_FUNC_A, drive_strength);
		break;
	case 1:
		portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31,
				PORTMUX_FUNC_A, drive_strength);
		break;
	case 2:
		portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19,
				PORTMUX_FUNC_A, drive_strength);
		break;
	case 3:
		portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29,
				PORTMUX_FUNC_A, drive_strength);
		break;
	case 4:
		portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30,
				PORTMUX_FUNC_A, drive_strength);
		break;
	}
}

#endif /* __ASM_AVR32_ARCH_CLK_H__ */
Commit	Line	Data
df548d3c HS	1	/*
	2	* Copyright (C) 2006 Atmel Corporation
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
df548d3c HS	5	*/
	6	#ifndef __ASM_AVR32_ARCH_CLK_H__
	7	#define __ASM_AVR32_ARCH_CLK_H__
	8
5fee84a7	9	#include <asm/arch/chip-features.h>
98090cd7	10	#include <asm/arch/portmux.h>
5fee84a7	11
df548d3c	12	#ifdef CONFIG_PLL
cb547320 HS	13	#define PLL0_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) \
cb547320 HS	14	* CONFIG_SYS_PLL0_MUL)
98090cd7	15	#define MAIN_CLK_RATE PLL0_RATE
df548d3c	16	#else
cb547320	17	#define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ)
df548d3c HS	18	#endif
	19
	20	static inline unsigned long get_cpu_clk_rate(void)
	21	{
6d0f6bcf	22	return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU;
df548d3c HS	23	}
	24	static inline unsigned long get_hsb_clk_rate(void)
	25	{
6d0f6bcf	26	return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB;
df548d3c HS	27	}
	28	static inline unsigned long get_pba_clk_rate(void)
	29	{
6d0f6bcf	30	return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA;
df548d3c HS	31	}
	32	static inline unsigned long get_pbb_clk_rate(void)
	33	{
6d0f6bcf	34	return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB;
df548d3c HS	35	}
	36
	37	/* Accessors for specific devices. More will be added as needed. */
	38	static inline unsigned long get_sdram_clk_rate(void)
	39	{
	40	return get_hsb_clk_rate();
	41	}
5fee84a7	42	#ifdef AT32AP700x_CHIP_HAS_USART
df548d3c HS	43	static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
	44	{
	45	return get_pba_clk_rate();
	46	}
5fee84a7	47	#endif
cdd42c0c	48	#ifdef AT32AP700x_CHIP_HAS_MACB
b4ec9c2d HS	49	static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
	50	{
	51	return get_pbb_clk_rate();
	52	}
	53	static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
	54	{
	55	return get_hsb_clk_rate();
	56	}
5fee84a7 HS	57	#endif
5fee84a7 HS	58	#ifdef AT32AP700x_CHIP_HAS_MMCI
05fdab1e HS	59	static inline unsigned long get_mci_clk_rate(void)
	60	{
	61	return get_pbb_clk_rate();
	62	}
5fee84a7	63	#endif
60445cb5 HCE	64	#ifdef AT32AP700x_CHIP_HAS_SPI
	65	static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
	66	{
	67	return get_pba_clk_rate();
	68	}
	69	#endif
716ece1d MJ	70	#ifdef AT32AP700x_CHIP_HAS_LCDC
	71	static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
	72	{
	73	return get_hsb_clk_rate();
	74	}
	75	#endif
df548d3c	76
3ace2527 HS	77	extern void clk_init(void);
3ace2527 HS	78
d38da537	79	/* Board code may need the SDRAM base clock as a compile-time constant */
6d0f6bcf	80	#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB)
d38da537	81
98090cd7 HS	82	/* Generic clock control */
	83	enum gclk_parent {
	84	GCLK_PARENT_OSC0 = 0,
	85	GCLK_PARENT_OSC1 = 1,
	86	GCLK_PARENT_PLL0 = 2,
	87	GCLK_PARENT_PLL1 = 3,
	88	};
	89
	90	/* Some generic clocks have specific roles */
	91	#define GCLK_DAC_SAMPLE_CLK 6
	92	#define GCLK_LCDC_PIXCLK 7
	93
	94	extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
	95	unsigned long rate, unsigned long parent_rate);
	96
	97	/**
	98	* gclk_set_rate - configure and enable a generic clock
	99	* @id: Which GCLK[id] to enable
	100	* @parent: Parent clock feeding the GCLK
	101	* @rate: Target rate of the GCLK in Hz
	102	*
	103	* Returns the actual GCLK rate in Hz, after rounding to the nearest
	104	* supported rate.
	105	*
	106	* All three parameters are usually constant, hence the inline.
	107	*/
	108	static inline unsigned long gclk_set_rate(unsigned int id,
	109	enum gclk_parent parent, unsigned long rate)
	110	{
	111	unsigned long parent_rate;
	112
	113	if (id > 7)
	114	return 0;
	115
	116	switch (parent) {
	117	case GCLK_PARENT_OSC0:
cb547320	118	parent_rate = CONFIG_SYS_OSC0_HZ;
98090cd7	119	break;
cb547320	120	#ifdef CONFIG_SYS_OSC1_HZ
98090cd7	121	case GCLK_PARENT_OSC1:
cb547320	122	parent_rate = CONFIG_SYS_OSC1_HZ;
98090cd7 HS	123	break;
	124	#endif
	125	#ifdef PLL0_RATE
	126	case GCLK_PARENT_PLL0:
	127	parent_rate = PLL0_RATE;
	128	break;
	129	#endif
	130	#ifdef PLL1_RATE
	131	case GCLK_PARENT_PLL1:
	132	parent_rate = PLL1_RATE;
	133	break;
	134	#endif
	135	default:
	136	parent_rate = 0;
	137	break;
	138	}
	139
	140	return __gclk_set_rate(id, parent, rate, parent_rate);
	141	}
	142
	143	/**
	144	* gclk_enable_output - enable output on a GCLK pin
	145	* @id: Which GCLK[id] pin to enable
	146	* @drive_strength: Drive strength of external GCLK pin, if applicable
	147	*/
	148	static inline void gclk_enable_output(unsigned int id,
	149	unsigned long drive_strength)
	150	{
	151	switch (id) {
	152	case 0:
	153	portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30,
	154	PORTMUX_FUNC_A, drive_strength);
	155	break;
	156	case 1:
	157	portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31,
	158	PORTMUX_FUNC_A, drive_strength);
	159	break;
	160	case 2:
	161	portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19,
	162	PORTMUX_FUNC_A, drive_strength);
	163	break;
	164	case 3:
	165	portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29,
	166	PORTMUX_FUNC_A, drive_strength);
	167	break;
	168	case 4:
	169	portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30,
	170	PORTMUX_FUNC_A, drive_strength);
	171	break;
	172	}
	173	}
	174
df548d3c	175	#endif /* __ASM_AVR32_ARCH_CLK_H__ */