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Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze
[people/ms/u-boot.git] / arch / blackfin / cpu / initcode.c
CommitLineData
9171fc81
MF		 1/*
2 * initcode.c - Initialize the processor. This is usually entails things
3 * like external memory, voltage regulators, etc... Note that this file
4 * cannot make any function calls as it may be executed all by itself by
5 * the Blackfin's bootrom in LDR format.
6 *
4150cec3 7 * Copyright (c) 2004-2011 Analog Devices Inc.
9171fc81
MF		 8 *
9 * Licensed under the GPL-2 or later.
10 */
11
dbda2c65
MF		 12#define BFIN_IN_INITCODE
13
9171fc81
MF		 14#include <config.h>
15#include <asm/blackfin.h>
e9a389a1 16#include <asm/mach-common/bits/watchdog.h>
9171fc81 17#include <asm/mach-common/bits/bootrom.h>
74398b23 18#include <asm/mach-common/bits/core.h>
9d803fc8 19#include <asm/serial.h>
9171fc81 20
a2979dcd
SZ		 21#ifndef __ADSPBF60x__
22#include <asm/mach-common/bits/ebiu.h>
23#include <asm/mach-common/bits/pll.h>
24#else /* __ADSPBF60x__ */
25#include <asm/mach-common/bits/cgu.h>
26
27#define CONFIG_BFIN_GET_DCLK_M \
28 ((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000))
29
30#ifndef CONFIG_DMC_DDRCFG
31#if ((CONFIG_BFIN_GET_DCLK_M != 125) && \
32 (CONFIG_BFIN_GET_DCLK_M != 133) && \
33 (CONFIG_BFIN_GET_DCLK_M != 150) && \
34 (CONFIG_BFIN_GET_DCLK_M != 166) && \
35 (CONFIG_BFIN_GET_DCLK_M != 200) && \
36 (CONFIG_BFIN_GET_DCLK_M != 225) && \
37 (CONFIG_BFIN_GET_DCLK_M != 250))
38#error "DDR2 CLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
39#endif
40#endif
41
42/* DMC control bits */
43#define SRREQ 0x8
44
45/* DMC status bits */
46#define IDLE 0x1
47#define MEMINITDONE 0x4
48#define SRACK 0x8
49#define PDACK 0x10
50#define DPDACK 0x20
51#define DLLCALDONE 0x2000
52#define PENDREF 0xF0000
53#define PHYRDPHASE 0xF00000
54#define PHYRDPHASE_OFFSET 20
55
56/* DMC DLL control bits */
57#define DLLCALRDCNT 0xFF
58#define DATACYC_OFFSET 8
59
60struct ddr_config {
61 u32 ddr_clk;
62 u32 dmc_ddrctl;
63 u32 dmc_ddrcfg;
64 u32 dmc_ddrtr0;
65 u32 dmc_ddrtr1;
66 u32 dmc_ddrtr2;
67 u32 dmc_ddrmr;
68 u32 dmc_ddrmr1;
69};
70
71static struct ddr_config ddr_config_table[] = {
72 [0] = {
73 .ddr_clk = 125, /* 125MHz */
74 .dmc_ddrctl = 0x00000904,
75 .dmc_ddrcfg = 0x00000422,
76 .dmc_ddrtr0 = 0x20705212,
77 .dmc_ddrtr1 = 0x201003CF,
78 .dmc_ddrtr2 = 0x00320107,
79 .dmc_ddrmr = 0x00000422,
80 .dmc_ddrmr1 = 0x4,
81 },
82 [1] = {
83 .ddr_clk = 133, /* 133MHz */
84 .dmc_ddrctl = 0x00000904,
85 .dmc_ddrcfg = 0x00000422,
86 .dmc_ddrtr0 = 0x20806313,
87 .dmc_ddrtr1 = 0x2013040D,
88 .dmc_ddrtr2 = 0x00320108,
89 .dmc_ddrmr = 0x00000632,
90 .dmc_ddrmr1 = 0x4,
91 },
92 [2] = {
93 .ddr_clk = 150, /* 150MHz */
94 .dmc_ddrctl = 0x00000904,
95 .dmc_ddrcfg = 0x00000422,
96 .dmc_ddrtr0 = 0x20A07323,
97 .dmc_ddrtr1 = 0x20160492,
98 .dmc_ddrtr2 = 0x00320209,
99 .dmc_ddrmr = 0x00000632,
100 .dmc_ddrmr1 = 0x4,
101 },
102 [3] = {
103 .ddr_clk = 166, /* 166MHz */
104 .dmc_ddrctl = 0x00000904,
105 .dmc_ddrcfg = 0x00000422,
106 .dmc_ddrtr0 = 0x20A07323,
107 .dmc_ddrtr1 = 0x2016050E,
108 .dmc_ddrtr2 = 0x00320209,
109 .dmc_ddrmr = 0x00000632,
110 .dmc_ddrmr1 = 0x4,
111 },
112 [4] = {
113 .ddr_clk = 200, /* 200MHz */
114 .dmc_ddrctl = 0x00000904,
115 .dmc_ddrcfg = 0x00000422,
116 .dmc_ddrtr0 = 0x20a07323,
117 .dmc_ddrtr1 = 0x2016050f,
118 .dmc_ddrtr2 = 0x00320509,
119 .dmc_ddrmr = 0x00000632,
120 .dmc_ddrmr1 = 0x4,
121 },
122 [5] = {
123 .ddr_clk = 225, /* 225MHz */
124 .dmc_ddrctl = 0x00000904,
125 .dmc_ddrcfg = 0x00000422,
126 .dmc_ddrtr0 = 0x20E0A424,
127 .dmc_ddrtr1 = 0x302006DB,
128 .dmc_ddrtr2 = 0x0032020D,
129 .dmc_ddrmr = 0x00000842,
130 .dmc_ddrmr1 = 0x4,
131 },
132 [6] = {
133 .ddr_clk = 250, /* 250MHz */
134 .dmc_ddrctl = 0x00000904,
135 .dmc_ddrcfg = 0x00000422,
136 .dmc_ddrtr0 = 0x20E0A424,
137 .dmc_ddrtr1 = 0x3020079E,
138 .dmc_ddrtr2 = 0x0032050D,
139 .dmc_ddrmr = 0x00000842,
140 .dmc_ddrmr1 = 0x4,
141 },
142};
143#endif /* __ADSPBF60x__ */
144
9171fc81 145__attribute__((always_inline))
f790ef6f 146static inline void serial_init(void)
9171fc81 147{
a2979dcd 148#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
9171fc81
MF		 149# ifdef BFIN_BOOT_UART_USE_RTS
150# define BFIN_UART_USE_RTS 1
151# else
152# define BFIN_UART_USE_RTS 0
153# endif
154 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
ecf9ce21 155 uint32_t uart_base = UART_BASE;
9171fc81
MF		 156 size_t i;
157
158 /* force RTS rather than relying on auto RTS */
a2979dcd 159#if BFIN_UART_HW_VER < 4
f948158f 160 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
a2979dcd
SZ		 161#else
162 bfin_write32(&pUART->control, bfin_read32(&pUART->control) |
163 FCPOL);
164#endif
9171fc81
MF		 165
166 /* Wait for the line to clear up. We cannot rely on UART
167 * registers as none of them reflect the status of the RSR.
168 * Instead, we'll sleep for ~10 bit times at 9600 baud.
169 * We can precalc things here by assuming boot values for
170 * PLL rather than loading registers and calculating.
171 * baud = SCLK / (16 ^ (1 - EDBO) * Divisor)
172 * EDB0 = 0
173 * Divisor = (SCLK / baud) / 16
174 * SCLK = baud * 16 * Divisor
175 * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5
176 * CCLK = (16 * Divisor * 5) * (9600 / 10)
177 * In reality, this will probably be just about 1 second delay,
178 * so assuming 9600 baud is OK (both as a very low and too high
179 * speed as this will buffer things enough).
180 */
181#define _NUMBITS (10) /* how many bits to delay */
182#define _LOWBAUD (9600) /* low baud rate */
183#define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */
184#define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */
185#define _NUMINS (3) /* how many instructions in loop */
186#define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
187 i = _CCLK;
188 while (i--)
189 asm volatile("" : : : "memory");
190 }
191#endif
192
ab80b659 193#if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS
9171fc81 194 if (BFIN_DEBUG_EARLY_SERIAL) {
ecf9ce21
SZ		 195 serial_early_init(UART_BASE);
196 serial_early_set_baud(UART_BASE, CONFIG_BAUDRATE);
9171fc81 197 }
ab80b659 198#endif
9171fc81
MF		 199}
200
201__attribute__((always_inline))
202static inline void serial_deinit(void)
203{
a2979dcd
SZ		 204#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
205 uint32_t uart_base = UART_BASE;
635f330f 206
9171fc81
MF		 207 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
208 /* clear forced RTS rather than relying on auto RTS */
a2979dcd 209#if BFIN_UART_HW_VER < 4
f948158f 210 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
a2979dcd
SZ		 211#else
212 bfin_write32(&pUART->control, bfin_read32(&pUART->control) &
213 ~FCPOL);
214#endif
9171fc81
MF		 215 }
216#endif
217}
218
9171fc81
MF		 219__attribute__((always_inline))
220static inline void serial_putc(char c)
221{
a2979dcd 222 uint32_t uart_base = UART_BASE;
635f330f 223
9171fc81
MF		 224 if (!BFIN_DEBUG_EARLY_SERIAL)
225 return;
226
227 if (c == '\n')
af2c3737 228 serial_putc('\r');
9171fc81 229
a2979dcd 230 bfin_write(&pUART->thr, c);
9171fc81 231
a2979dcd 232 while (!(_lsr_read(pUART) & TEMT))
9171fc81
MF		 233 continue;
234}
235
4150cec3
MF		 236#include "initcode.h"
237
ce53fc66
MF		 238__attribute__((always_inline)) static inline void
239program_nmi_handler(void)
240{
241 u32 tmp1, tmp2;
242
243 /* Older bootroms don't create a dummy NMI handler,
244 * so make one ourselves ASAP in case it fires.
245 */
246 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
247 return;
248
249 asm volatile (
250 "%0 = RETS;" /* Save current RETS */
251 "CALL 1f;" /* Figure out current PC */
252 "RTN;" /* The simple NMI handler */
253 "1:"
254 "%1 = RETS;" /* Load addr of NMI handler */
255 "RETS = %0;" /* Restore RETS */
256 "[%2] = %1;" /* Write NMI handler */
2e2ed3f4
MF		 257 : "=d"(tmp1), "=d"(tmp2)
258 : "ab"(EVT2)
ce53fc66
MF		 259 );
260}
9171fc81 261
97f265f1
MF		 262/* Max SCLK can be 133MHz ... dividing that by (2*4) gives
263 * us a freq of 16MHz for SPI which should generally be
9171fc81
MF		 264 * slow enough for the slow reads the bootrom uses.
265 */
97f265f1
MF		 266#if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
267 ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
268 (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
269# define BOOTROM_SUPPORTS_SPI_FAST_READ 1
270#else
271# define BOOTROM_SUPPORTS_SPI_FAST_READ 0
272#endif
9171fc81 273#ifndef CONFIG_SPI_BAUD_INITBLOCK
97f265f1
MF		 274# define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
275#endif
276#ifdef SPI0_BAUD
277# define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
9171fc81
MF		 278#endif
279
a2979dcd
SZ		 280#ifdef __ADSPBF60x__
281
282#ifndef CONFIG_CGU_CTL_VAL
283# define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF)
284#endif
285
286#ifndef CONFIG_CGU_DIV_VAL
287# define CONFIG_CGU_DIV_VAL \
288 ((CONFIG_CCLK_DIV << CSEL_P) | \
289 (CONFIG_SCLK0_DIV << S0SEL_P) | \
290 (CONFIG_SCLK_DIV << SYSSEL_P) | \
291 (CONFIG_SCLK1_DIV << S1SEL_P) | \
292 (CONFIG_DCLK_DIV << DSEL_P) | \
293 (CONFIG_OCLK_DIV << OSEL_P))
294#endif
295
296#else /* __ADSPBF60x__ */
297
9171fc81
MF		 298/* PLL_DIV defines */
299#ifndef CONFIG_PLL_DIV_VAL
300# if (CONFIG_CCLK_DIV == 1)
301# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
302# elif (CONFIG_CCLK_DIV == 2)
303# define CONFIG_CCLK_ACT_DIV CCLK_DIV2
304# elif (CONFIG_CCLK_DIV == 4)
305# define CONFIG_CCLK_ACT_DIV CCLK_DIV4
306# elif (CONFIG_CCLK_DIV == 8)
307# define CONFIG_CCLK_ACT_DIV CCLK_DIV8
308# else
309# define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
310# endif
311# define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
312#endif
313
314#ifndef CONFIG_PLL_LOCKCNT_VAL
315# define CONFIG_PLL_LOCKCNT_VAL 0x0300
316#endif
317
318#ifndef CONFIG_PLL_CTL_VAL
4f6a3132 319# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
9171fc81
MF		 320#endif
321
9171fc81
MF		 322/* Make sure our voltage value is sane so we don't blow up! */
323#ifndef CONFIG_VR_CTL_VAL
324# define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
325# if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
326# define CCLK_VLEV_120 400000000
327# define CCLK_VLEV_125 533000000
328# elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
329# define CCLK_VLEV_120 401000000
330# define CCLK_VLEV_125 401000000
331# elif defined(__ADSPBF561__)
332# define CCLK_VLEV_120 300000000
333# define CCLK_VLEV_125 501000000
334# endif
335# if BFIN_CCLK < CCLK_VLEV_120
336# define CONFIG_VR_CTL_VLEV VLEV_120
337# elif BFIN_CCLK < CCLK_VLEV_125
338# define CONFIG_VR_CTL_VLEV VLEV_125
339# else
340# define CONFIG_VR_CTL_VLEV VLEV_130
341# endif
342# if defined(__ADSPBF52x__) /* TBD; use default */
343# undef CONFIG_VR_CTL_VLEV
344# define CONFIG_VR_CTL_VLEV VLEV_110
345# elif defined(__ADSPBF54x__) /* TBD; use default */
346# undef CONFIG_VR_CTL_VLEV
347# define CONFIG_VR_CTL_VLEV VLEV_120
622a8dc0
MF		 348# elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
349# undef CONFIG_VR_CTL_VLEV
350# define CONFIG_VR_CTL_VLEV VLEV_125
9171fc81
MF		 351# endif
352
353# ifdef CONFIG_BFIN_MAC
354# define CONFIG_VR_CTL_CLKBUF CLKBUFOE
355# else
356# define CONFIG_VR_CTL_CLKBUF 0
357# endif
358
359# if defined(__ADSPBF52x__)
360# define CONFIG_VR_CTL_FREQ FREQ_1000
361# else
362# define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
363# endif
364
365# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
366#endif
367
d347d572
MF		 368/* some parts do not have an on-chip voltage regulator */
369#if defined(__ADSPBF51x__)
370# define CONFIG_HAS_VR 0
371# undef CONFIG_VR_CTL_VAL
372# define CONFIG_VR_CTL_VAL 0
373#else
374# define CONFIG_HAS_VR 1
375#endif
376
dbda2c65 377#if CONFIG_MEM_SIZE
0d4f24b7
MF		 378#ifndef EBIU_RSTCTL
379/* Blackfin with SDRAM */
380#ifndef CONFIG_EBIU_SDBCTL_VAL
381# if CONFIG_MEM_SIZE == 16
382# define CONFIG_EBSZ_VAL EBSZ_16
383# elif CONFIG_MEM_SIZE == 32
384# define CONFIG_EBSZ_VAL EBSZ_32
385# elif CONFIG_MEM_SIZE == 64
386# define CONFIG_EBSZ_VAL EBSZ_64
387# elif CONFIG_MEM_SIZE == 128
388# define CONFIG_EBSZ_VAL EBSZ_128
389# elif CONFIG_MEM_SIZE == 256
390# define CONFIG_EBSZ_VAL EBSZ_256
391# elif CONFIG_MEM_SIZE == 512
392# define CONFIG_EBSZ_VAL EBSZ_512
393# else
394# error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
395# endif
396# if CONFIG_MEM_ADD_WDTH == 8
397# define CONFIG_EBCAW_VAL EBCAW_8
398# elif CONFIG_MEM_ADD_WDTH == 9
399# define CONFIG_EBCAW_VAL EBCAW_9
400# elif CONFIG_MEM_ADD_WDTH == 10
401# define CONFIG_EBCAW_VAL EBCAW_10
402# elif CONFIG_MEM_ADD_WDTH == 11
403# define CONFIG_EBCAW_VAL EBCAW_11
404# else
405# error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
406# endif
407# define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
408#endif
409#endif
dbda2c65 410#endif
0d4f24b7 411
8ef929af
MF		 412/* Conflicting Column Address Widths Causes SDRAM Errors:
413 * EB2CAW and EB3CAW must be the same
414 */
415#if ANOMALY_05000362
416# if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
417# error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
418# endif
419#endif
420
a2979dcd
SZ		 421#endif /* __ADSPBF60x__ */
422
dbda2c65
MF		 423__attribute__((always_inline)) static inline void
424program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
9171fc81 425{
dbda2c65 426 serial_putc('a');
ad907321 427
f790ef6f 428 /* Save the clock pieces that are used in baud rate calculation */
f790ef6f 429 if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
dbda2c65 430 serial_putc('b');
a2979dcd
SZ		 431#ifdef __ADSPBF60x__
432 *sdivB = bfin_read_CGU_DIV();
433 *sdivB = ((*sdivB >> 8) & 0x1f) * ((*sdivB >> 5) & 0x7);
434 *vcoB = (bfin_read_CGU_CTL() >> 8) & 0x7f;
435#else
dbda2c65
MF		 436 *sdivB = bfin_read_PLL_DIV() & 0xf;
437 *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
a2979dcd 438#endif
dbda2c65
MF		 439 *divB = serial_early_get_div();
440 serial_putc('c');
f790ef6f 441 }
9171fc81 442
dbda2c65 443 serial_putc('d');
ad907321 444
9171fc81
MF		 445#ifdef CONFIG_HW_WATCHDOG
446# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
447# define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
448# endif
449 /* Program the watchdog with an initial timeout of ~20 seconds.
450 * Hopefully that should be long enough to load the u-boot LDR
451 * (from wherever) and then the common u-boot code can take over.
452 * In bypass mode, the start.S would have already set a much lower
453 * timeout, so don't clobber that.
454 */
455 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
dbda2c65 456 serial_putc('e');
49c2da53 457#ifdef __ADSPBF60x__
85f2f8f9 458 /* Reset system event controller */
49c2da53 459 bfin_write_SEC_GCTL(0x2);
85f2f8f9 460 bfin_write_SEC_CCTL(0x2);
49c2da53 461 SSYNC();
85f2f8f9
SZ		 462
463 /* Enable fault event input and system reset action in fault
464 * controller. Route watchdog timeout event to fault interface.
465 */
49c2da53 466 bfin_write_SEC_FCTL(0xc1);
85f2f8f9 467 /* Enable watchdog interrupt source */
49c2da53 468 bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6);
49c2da53 469 SSYNC();
85f2f8f9
SZ		 470
471 /* Enable system event controller */
49c2da53
BL		 472 bfin_write_SEC_GCTL(0x1);
473 bfin_write_SEC_CCTL(0x1);
85f2f8f9 474 SSYNC();
49c2da53 475#endif
e9a389a1
SZ		 476 bfin_write_WDOG_CTL(WDDIS);
477 SSYNC();
9171fc81 478 bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
49c2da53 479#if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART
e9a389a1 480 bfin_write_WDOG_CTL(WDEN);
49c2da53 481#endif
dbda2c65 482 serial_putc('f');
9171fc81
MF		 483 }
484#endif
485
dbda2c65
MF		 486 serial_putc('g');
487
488 /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
489 * fast read, so we need to slow down the SPI clock a lot more during
490 * boot. Once we switch over to u-boot's SPI flash driver, we'll
491 * increase the speed appropriately.
492 */
a2979dcd 493#ifdef SPI_BAUD
dbda2c65
MF		 494 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
495 serial_putc('h');
496 if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
497 bs->dFlags |= BFLAG_FASTREAD;
498 bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
499 serial_putc('i');
500 }
a2979dcd 501#endif
dbda2c65
MF		 502
503 serial_putc('j');
504}
505
506__attribute__((always_inline)) static inline bool
507maybe_self_refresh(ADI_BOOT_DATA *bs)
508{
509 serial_putc('a');
510
511 if (!CONFIG_MEM_SIZE)
512 return false;
74398b23 513
a2979dcd 514#ifdef __ADSPBF60x__
9faf4f08
SM		 515 /* resume from hibernate, return false let ddr initialize */
516 if ((bfin_read32(DPM0_STAT) & 0xF0) == 0x50) {
517 serial_putc('b');
518 return false;
519 }
a2979dcd
SZ		 520
521#else /* __ADSPBF60x__ */
522
74398b23 523 /* If external memory is enabled, put it into self refresh first. */
cca07417 524#if defined(EBIU_RSTCTL)
74398b23 525 if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
dbda2c65 526 serial_putc('b');
74398b23 527 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
dbda2c65 528 return true;
74398b23 529 }
cca07417 530#elif defined(EBIU_SDGCTL)
74398b23 531 if (bfin_read_EBIU_SDBCTL() & EBE) {
dbda2c65 532 serial_putc('b');
74398b23 533 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
dbda2c65 534 return true;
74398b23
MF		 535 }
536#endif
537
a2979dcd 538#endif /* __ADSPBF60x__ */
dbda2c65 539 serial_putc('c');
9171fc81 540
dbda2c65
MF		 541 return false;
542}
9171fc81 543
dbda2c65
MF		 544__attribute__((always_inline)) static inline u16
545program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
546{
ecf9ce21 547 u16 vr_ctl = 0;
dbda2c65
MF		 548
549 serial_putc('a');
550
a2979dcd
SZ		 551#ifdef __ADSPBF60x__
552 if (bfin_read_DMC0_STAT() & MEMINITDONE) {
553 bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
554 SSYNC();
555 while (!(bfin_read_DMC0_STAT() & SRACK))
556 continue;
557 }
558
559 /* Don't set the same value of MSEL and DF to CGU_CTL */
560 if ((bfin_read_CGU_CTL() & (MSEL_MASK | DF_MASK))
561 != CONFIG_CGU_CTL_VAL) {
562 bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL);
563 bfin_write_CGU_CTL(CONFIG_CGU_CTL_VAL);
564 while ((bfin_read_CGU_STAT() & (CLKSALGN | PLLBP)) ||
565 !(bfin_read_CGU_STAT() & PLLLK))
566 continue;
567 }
568
569 bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL | UPDT);
570 while (bfin_read_CGU_STAT() & CLKSALGN)
571 continue;
572
573 if (bfin_read_DMC0_STAT() & MEMINITDONE) {
574 bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
575 SSYNC();
576 while (bfin_read_DMC0_STAT() & SRACK)
577 continue;
578 }
579
580#else /* __ADSPBF60x__ */
581
dbda2c65
MF		 582 vr_ctl = bfin_read_VR_CTL();
583
584 serial_putc('b');
9171fc81 585
74398b23
MF		 586 /* If we're entering self refresh, make sure it has happened. */
587 if (put_into_srfs)
cca07417 588#if defined(EBIU_RSTCTL)
74398b23 589 while (!(bfin_read_EBIU_RSTCTL() & SRACK))
cca07417
MF		 590 continue;
591#elif defined(EBIU_SDGCTL)
74398b23 592 while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
74398b23 593 continue;
cca07417
MF		 594#else
595 ;
596#endif
74398b23 597
dbda2c65 598 serial_putc('c');
9171fc81 599
09dc6b0b
MF		 600 /* With newer bootroms, we use the helper function to set up
601 * the memory controller. Older bootroms lacks such helpers
602 * so we do it ourselves.
603 */
74398b23 604 if (!ANOMALY_05000386) {
dbda2c65 605 serial_putc('d');
9171fc81 606
c2e07449 607 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
09dc6b0b 608 ADI_SYSCTRL_VALUES memory_settings;
5641f34f
MF		 609 uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT;
610 if (!ANOMALY_05000440)
611 actions |= SYSCTRL_PLLDIV;
d347d572
MF		 612 if (CONFIG_HAS_VR) {
613 actions |= SYSCTRL_VRCTL;
614 if (CONFIG_VR_CTL_VAL & FREQ_MASK)
615 actions |= SYSCTRL_INTVOLTAGE;
616 else
617 actions |= SYSCTRL_EXTVOLTAGE;
618 memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
619 } else
620 actions |= SYSCTRL_EXTVOLTAGE;
09dc6b0b
MF		 621 memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
622 memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
623 memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
3986e981
MF		 624#if ANOMALY_05000432
625 bfin_write_SIC_IWR1(0);
626#endif
dbda2c65 627 serial_putc('e');
d347d572 628 bfrom_SysControl(actions, &memory_settings, NULL);
dbda2c65 629 serial_putc('f');
5641f34f
MF		 630 if (ANOMALY_05000440)
631 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
3986e981
MF		 632#if ANOMALY_05000432
633 bfin_write_SIC_IWR1(-1);
ce1fe4ba
MF		 634#endif
635#if ANOMALY_05000171
636 bfin_write_SICA_IWR0(-1);
637 bfin_write_SICA_IWR1(-1);
3986e981 638#endif
dbda2c65 639 serial_putc('g');
09dc6b0b 640 } else {
dbda2c65 641 serial_putc('h');
74398b23
MF		 642
643 /* Disable all peripheral wakeups except for the PLL event. */
644#ifdef SIC_IWR0
645 bfin_write_SIC_IWR0(1);
646 bfin_write_SIC_IWR1(0);
647# ifdef SIC_IWR2
648 bfin_write_SIC_IWR2(0);
649# endif
650#elif defined(SICA_IWR0)
651 bfin_write_SICA_IWR0(1);
652 bfin_write_SICA_IWR1(0);
a2979dcd 653#elif defined(SIC_IWR)
74398b23
MF		 654 bfin_write_SIC_IWR(1);
655#endif
656
dbda2c65 657 serial_putc('i');
9171fc81 658
c2e07449 659 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
09dc6b0b 660 bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
9171fc81 661
dbda2c65 662 serial_putc('j');
9171fc81 663
09dc6b0b
MF		 664 /* Only reprogram when needed to avoid triggering unnecessary
665 * PLL relock sequences.
666 */
74398b23 667 if (vr_ctl != CONFIG_VR_CTL_VAL) {
dbda2c65 668 serial_putc('?');
09dc6b0b
MF		 669 bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
670 asm("idle;");
dbda2c65 671 serial_putc('!');
09dc6b0b 672 }
9171fc81 673
dbda2c65 674 serial_putc('k');
9171fc81 675
09dc6b0b 676 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
9171fc81 677
dbda2c65 678 serial_putc('l');
09dc6b0b
MF		 679
680 /* Only reprogram when needed to avoid triggering unnecessary
681 * PLL relock sequences.
682 */
48ab1509 683 if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
dbda2c65 684 serial_putc('?');
09dc6b0b
MF		 685 bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
686 asm("idle;");
dbda2c65 687 serial_putc('!');
09dc6b0b 688 }
74398b23 689
dbda2c65 690 serial_putc('m');
74398b23
MF		 691
692 /* Restore all peripheral wakeups. */
693#ifdef SIC_IWR0
694 bfin_write_SIC_IWR0(-1);
695 bfin_write_SIC_IWR1(-1);
696# ifdef SIC_IWR2
697 bfin_write_SIC_IWR2(-1);
698# endif
699#elif defined(SICA_IWR0)
700 bfin_write_SICA_IWR0(-1);
701 bfin_write_SICA_IWR1(-1);
a2979dcd 702#elif defined(SIC_IWR)
74398b23
MF		 703 bfin_write_SIC_IWR(-1);
704#endif
dbda2c65
MF		 705
706 serial_putc('n');
9171fc81
MF		 707 }
708
a2979dcd
SZ		 709#endif /* __ADSPBF60x__ */
710
dbda2c65
MF		 711 serial_putc('o');
712
713 return vr_ctl;
714}
715
716__attribute__((always_inline)) static inline void
717update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
718{
9171fc81
MF		 719 /* Since we've changed the SCLK above, we may need to update
720 * the UART divisors (UART baud rates are based on SCLK).
f790ef6f
MF		 721 * Do the division by hand as there are no native instructions
722 * for dividing which means we'd generate a libgcc reference.
9171fc81 723 */
79f2b399 724 unsigned int sdivR, vcoR;
04eeb758
SZ		 725 unsigned int dividend;
726 unsigned int divisor;
79f2b399 727 unsigned int quotient;
a2979dcd 728
79f2b399 729 serial_putc('a');
a2979dcd 730
ecf9ce21
SZ		 731 if (BFIN_DEBUG_EARLY_SERIAL ||
732 CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
a2979dcd 733#ifdef __ADSPBF60x__
79f2b399
SZ		 734 sdivR = bfin_read_CGU_DIV();
735 sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
736 vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
a2979dcd 737#else
79f2b399
SZ		 738 sdivR = bfin_read_PLL_DIV() & 0xf;
739 vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
a2979dcd 740#endif
04eeb758
SZ		 741
742 dividend = sdivB * divB * vcoR;
743 divisor = vcoB * sdivR;
79f2b399
SZ		 744 quotient = early_division(dividend, divisor);
745 serial_early_put_div(quotient - ANOMALY_05000230);
ecf9ce21
SZ		 746 }
747
79f2b399 748 serial_putc('c');
dbda2c65
MF		 749}
750
751__attribute__((always_inline)) static inline void
752program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
753{
754 serial_putc('a');
755
756 if (!CONFIG_MEM_SIZE)
757 return;
758
759 serial_putc('b');
9171fc81 760
a2979dcd
SZ		 761#ifdef __ADSPBF60x__
762 int dlldatacycle;
763 int dll_ctl;
764 int i = 0;
765
766 if (CONFIG_BFIN_GET_DCLK_M == 125)
767 i = 0;
768 else if (CONFIG_BFIN_GET_DCLK_M == 133)
769 i = 1;
770 else if (CONFIG_BFIN_GET_DCLK_M == 150)
771 i = 2;
772 else if (CONFIG_BFIN_GET_DCLK_M == 166)
773 i = 3;
774 else if (CONFIG_BFIN_GET_DCLK_M == 200)
775 i = 4;
776 else if (CONFIG_BFIN_GET_DCLK_M == 225)
777 i = 5;
778 else if (CONFIG_BFIN_GET_DCLK_M == 250)
779 i = 6;
780
781#if 0
782 for (i = 0; i < ARRAY_SIZE(ddr_config_table); i++)
783 if (CONFIG_BFIN_GET_DCLK_M == ddr_config_table[i].ddr_clk)
784 break;
785#endif
786
787#ifndef CONFIG_DMC_DDRCFG
788 bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
789#else
790 bfin_write_DMC0_CFG(CONFIG_DMC_DDRCFG);
791#endif
792#ifndef CONFIG_DMC_DDRTR0
793 bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
794#else
795 bfin_write_DMC0_TR0(CONFIG_DMC_DDRTR0);
796#endif
797#ifndef CONFIG_DMC_DDRTR1
798 bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
799#else
800 bfin_write_DMC0_TR1(CONFIG_DMC_DDRTR1);
801#endif
802#ifndef CONFIG_DMC_DDRTR2
803 bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
804#else
805 bfin_write_DMC0_TR2(CONFIG_DMC_DDRTR2);
806#endif
807#ifndef CONFIG_DMC_DDRMR
808 bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
809#else
810 bfin_write_DMC0_MR(CONFIG_DMC_DDRMR);
811#endif
812#ifndef CONFIG_DMC_DDREMR1
813 bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
814#else
815 bfin_write_DMC0_EMR1(CONFIG_DMC_DDREMR1);
816#endif
817#ifndef CONFIG_DMC_DDRCTL
818 bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
819#else
820 bfin_write_DMC0_CTL(CONFIG_DMC_DDRCTL);
821#endif
822
823 SSYNC();
824 while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
825 continue;
826
827 dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >>
828 PHYRDPHASE_OFFSET;
829 dll_ctl = bfin_read_DMC0_DLLCTL();
830 dll_ctl &= 0x0ff;
831 bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
832
833 SSYNC();
834 while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
835 continue;
836 serial_putc('!');
9faf4f08 837
a2979dcd
SZ		 838#else /* __ADSPBF60x__ */
839
74398b23
MF		 840 /* Program the external memory controller before we come out of
841 * self-refresh. This only works with our SDRAM controller.
842 */
cca07417 843#ifdef EBIU_SDGCTL
dbda2c65 844# ifdef CONFIG_EBIU_SDRRC_VAL
74398b23 845 bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
dbda2c65
MF		 846# endif
847# ifdef CONFIG_EBIU_SDBCTL_VAL
74398b23 848 bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
dbda2c65
MF		 849# endif
850# ifdef CONFIG_EBIU_SDGCTL_VAL
74398b23 851 bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
dbda2c65 852# endif
74398b23 853#endif
9171fc81 854
dbda2c65 855 serial_putc('c');
74398b23
MF		 856
857 /* Now that we've reprogrammed, take things out of self refresh. */
858 if (put_into_srfs)
cca07417 859#if defined(EBIU_RSTCTL)
74398b23 860 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
cca07417 861#elif defined(EBIU_SDGCTL)
74398b23 862 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
9171fc81
MF		 863#endif
864
dbda2c65 865 serial_putc('d');
9171fc81 866
74398b23
MF		 867 /* Our DDR controller sucks and cannot be programmed while in
868 * self-refresh. So we have to pull it out before programming.
869 */
9171fc81 870#ifdef EBIU_RSTCTL
7527feef 871# ifdef CONFIG_EBIU_RSTCTL_VAL
9171fc81 872 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
7527feef
MF		 873# endif
874# ifdef CONFIG_EBIU_DDRCTL0_VAL
9171fc81 875 bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
7527feef
MF		 876# endif
877# ifdef CONFIG_EBIU_DDRCTL1_VAL
9171fc81 878 bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
7527feef
MF		 879# endif
880# ifdef CONFIG_EBIU_DDRCTL2_VAL
9171fc81 881 bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
7527feef 882# endif
9171fc81
MF		 883# ifdef CONFIG_EBIU_DDRCTL3_VAL
884 /* default is disable, so don't need to force this */
885 bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
886# endif
74398b23
MF		 887# ifdef CONFIG_EBIU_DDRQUE_VAL
888 bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
889# endif
9171fc81
MF		 890#endif
891
a2979dcd 892#endif /* __ADSPBF60x__ */
dbda2c65
MF		 893 serial_putc('e');
894}
895
896__attribute__((always_inline)) static inline void
897check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
898{
899 serial_putc('a');
900
901 if (!CONFIG_MEM_SIZE)
902 return;
903
904 serial_putc('b');
9faf4f08
SM		 905#ifdef __ADSPBF60x__
906 if (bfin_read32(DPM0_RESTORE0) != 0) {
907 uint32_t reg = bfin_read_DMC0_CTL();
908 reg &= ~0x8;
909 bfin_write_DMC0_CTL(reg);
910
911 while ((bfin_read_DMC0_STAT() & 0x8))
912 continue;
913 while (!(bfin_read_DMC0_STAT() & 0x1))
914 continue;
9171fc81 915
9faf4f08 916 serial_putc('z');
ecf9ce21
SZ		 917 uint32_t *hibernate_magic =
918 (uint32_t *)bfin_read32(DPM0_RESTORE4);
9faf4f08
SM		 919 SSYNC(); /* make sure memory controller is done */
920 if (hibernate_magic[0] == 0xDEADBEEF) {
921 serial_putc('c');
922 SSYNC();
923 bfin_write_EVT15(hibernate_magic[1]);
924 bfin_write_IMASK(EVT_IVG15);
925 __asm__ __volatile__ (
926 /* load reti early to avoid anomaly 281 */
927 "reti = %2;"
928 /* clear hibernate magic */
929 "[%0] = %1;"
930 /* load stack pointer */
931 "SP = [%0 + 8];"
932 /* lower ourselves from reset ivg to ivg15 */
933 "raise 15;"
934 "nop;nop;nop;"
935 "rti;"
936 :
937 : "p"(hibernate_magic),
938 "d"(0x2000 /* jump.s 0 */),
939 "d"(0xffa00000)
940 );
941 }
942
943
944 }
945#else
74398b23
MF		 946 /* Are we coming out of hibernate (suspend to memory) ?
947 * The memory layout is:
948 * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
949 * 0x4: return address
950 * 0x8: stack pointer
951 *
952 * SCKELOW is unreliable on older parts (anomaly 307)
953 */
954 if (ANOMALY_05000307 || vr_ctl & 0x8000) {
955 uint32_t *hibernate_magic = 0;
a2979dcd
SZ		 956
957 SSYNC();
0060517a 958 /* cppcheck-suppress nullPointer */
74398b23 959 if (hibernate_magic[0] == 0xDEADBEEF) {
dbda2c65 960 serial_putc('c');
74398b23
MF		 961 bfin_write_EVT15(hibernate_magic[1]);
962 bfin_write_IMASK(EVT_IVG15);
963 __asm__ __volatile__ (
964 /* load reti early to avoid anomaly 281 */
965 "reti = %0;"
966 /* clear hibernate magic */
967 "[%0] = %1;"
968 /* load stack pointer */
969 "SP = [%0 + 8];"
970 /* lower ourselves from reset ivg to ivg15 */
971 "raise 15;"
972 "rti;"
973 :
974 : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
975 );
976 }
dbda2c65 977 serial_putc('d');
74398b23 978 }
9faf4f08 979#endif
74398b23 980
dbda2c65
MF		 981 serial_putc('e');
982}
983
dbda2c65
MF		 984BOOTROM_CALLED_FUNC_ATTR
985void initcode(ADI_BOOT_DATA *bs)
986{
987 ADI_BOOT_DATA bootstruct_scratch;
988
ce53fc66
MF		 989 /* Setup NMI handler before anything else */
990 program_nmi_handler();
991
dbda2c65
MF		 992 serial_init();
993
994 serial_putc('A');
995
996 /* If the bootstruct is NULL, then it's because we're loading
997 * dynamically and not via LDR (bootrom). So set the struct to
998 * some scratch space.
999 */
1000 if (!bs)
1001 bs = &bootstruct_scratch;
1002
1003 serial_putc('B');
1004 bool put_into_srfs = maybe_self_refresh(bs);
1005
1006 serial_putc('C');
1007 uint sdivB, divB, vcoB;
1008 program_early_devices(bs, &sdivB, &divB, &vcoB);
1009
1010 serial_putc('D');
1011 u16 vr_ctl = program_clocks(bs, put_into_srfs);
1012
1013 serial_putc('E');
1014 update_serial_clocks(bs, sdivB, divB, vcoB);
1015
1016 serial_putc('F');
1017 program_memory_controller(bs, put_into_srfs);
1018
1019 serial_putc('G');
1020 check_hibernation(bs, vr_ctl, put_into_srfs);
1021
1022 serial_putc('H');
1023 program_async_controller(bs);
74398b23 1024
02778f2f 1025#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
dbda2c65 1026 serial_putc('I');
b30453ac
MF		 1027 /* Tell the bootrom where our entry point is so that it knows
1028 * where to jump to when finishing processing the LDR. This
1029 * allows us to avoid small jump blocks in the LDR, and also
1030 * works around anomaly 05000389 (init address in external
1031 * memory causes bootrom to trigger external addressing IVHW).
1032 */
7e1d212b
MF		 1033 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
1034 bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
02778f2f 1035#endif
7e1d212b 1036
9171fc81
MF		 1037 serial_putc('>');
1038 serial_putc('\n');
1039
1040 serial_deinit();
1041}
"Das U-Boot" Source Tree