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Commit | Line | Data |
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d9a5d113 | 1 | /* |
a187559e | 2 | * U-Boot - u-boot.lds.S |
d9a5d113 | 3 | * |
a3c08363 | 4 | * Copyright (c) 2005-2010 Analog Device Inc. |
d9a5d113 MF |
5 | * |
6 | * (C) Copyright 2000-2004 | |
7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
d9a5d113 MF |
10 | */ |
11 | ||
12 | #include <config.h> | |
13 | #include <asm/blackfin.h> | |
14 | #undef ALIGN | |
15 | #undef ENTRY | |
d9a5d113 | 16 | |
9ff67e5e MF |
17 | #ifndef LDS_BOARD_TEXT |
18 | # define LDS_BOARD_TEXT | |
19 | #endif | |
20 | ||
d9a5d113 MF |
21 | /* If we don't actually load anything into L1 data, this will avoid |
22 | * a syntax error. If we do actually load something into L1 data, | |
23 | * we'll get a linker memory load error (which is what we'd want). | |
24 | * This is here in the first place so we can quickly test building | |
25 | * for different CPU's which may lack non-cache L1 data. | |
26 | */ | |
105be907 MF |
27 | #ifndef L1_DATA_A_SRAM |
28 | # define L1_DATA_A_SRAM 0 | |
29 | # define L1_DATA_A_SRAM_SIZE 0 | |
30 | #endif | |
d9a5d113 | 31 | #ifndef L1_DATA_B_SRAM |
105be907 MF |
32 | # define L1_DATA_B_SRAM L1_DATA_A_SRAM |
33 | # define L1_DATA_B_SRAM_SIZE L1_DATA_A_SRAM_SIZE | |
d9a5d113 MF |
34 | #endif |
35 | ||
f51e0011 MF |
36 | /* The 0xC offset is so we don't clobber the tiny LDR jump block. */ |
37 | #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1 | |
38 | # define L1_CODE_ORIGIN L1_INST_SRAM | |
39 | #else | |
40 | # define L1_CODE_ORIGIN L1_INST_SRAM + 0xC | |
41 | #endif | |
42 | ||
d9a5d113 MF |
43 | OUTPUT_ARCH(bfin) |
44 | ||
45 | MEMORY | |
46 | { | |
7527feef | 47 | #if CONFIG_MEM_SIZE |
d9a5d113 | 48 | ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN |
7527feef MF |
49 | # define ram_code ram |
50 | # define ram_data ram | |
51 | #else | |
52 | # define ram_code l1_code | |
53 | # define ram_data l1_data | |
54 | #endif | |
f51e0011 | 55 | l1_code : ORIGIN = L1_CODE_ORIGIN, LENGTH = L1_INST_SRAM_SIZE |
d9a5d113 MF |
56 | l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE |
57 | } | |
58 | ||
59 | ENTRY(_start) | |
60 | SECTIONS | |
61 | { | |
b1e2c551 | 62 | .text.pre : |
d9a5d113 | 63 | { |
c6fb83d2 | 64 | arch/blackfin/cpu/start.o (.text .text.*) |
9ff67e5e MF |
65 | |
66 | LDS_BOARD_TEXT | |
b1e2c551 | 67 | } >ram_code |
9ff67e5e | 68 | |
b1e2c551 MF |
69 | .text.init : |
70 | { | |
c6fb83d2 | 71 | arch/blackfin/cpu/initcode.o (.text .text.*) |
b1e2c551 MF |
72 | } >ram_code |
73 | __initcode_lma = LOADADDR(.text.init); | |
74 | __initcode_len = SIZEOF(.text.init); | |
9ff67e5e | 75 | |
b1e2c551 MF |
76 | .text : |
77 | { | |
d9a5d113 | 78 | *(.text .text.*) |
7527feef | 79 | } >ram_code |
d9a5d113 MF |
80 | |
81 | .rodata : | |
82 | { | |
83 | . = ALIGN(4); | |
ed912d4d | 84 | *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
d9a5d113 | 85 | . = ALIGN(4); |
7527feef | 86 | } >ram_data |
d9a5d113 MF |
87 | |
88 | .data : | |
89 | { | |
38b9b744 | 90 | . = ALIGN(4); |
d9a5d113 MF |
91 | *(.data .data.*) |
92 | *(.data1) | |
93 | *(.sdata) | |
94 | *(.sdata2) | |
95 | *(.dynamic) | |
96 | CONSTRUCTORS | |
7527feef | 97 | } >ram_data |
d9a5d113 | 98 | |
d9a5d113 | 99 | |
55675142 | 100 | .u_boot_list : { |
ef123c52 | 101 | KEEP(*(SORT(.u_boot_list*))); |
55675142 MV |
102 | } >ram_data |
103 | ||
d9a5d113 MF |
104 | .text_l1 : |
105 | { | |
106 | . = ALIGN(4); | |
107 | __stext_l1 = .; | |
108 | *(.l1.text) | |
109 | . = ALIGN(4); | |
110 | __etext_l1 = .; | |
7527feef | 111 | } >l1_code AT>ram_code |
b1e2c551 MF |
112 | __text_l1_lma = LOADADDR(.text_l1); |
113 | __text_l1_len = SIZEOF(.text_l1); | |
114 | ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!") | |
d9a5d113 MF |
115 | |
116 | .data_l1 : | |
117 | { | |
118 | . = ALIGN(4); | |
119 | __sdata_l1 = .; | |
120 | *(.l1.data) | |
121 | *(.l1.bss) | |
122 | . = ALIGN(4); | |
123 | __edata_l1 = .; | |
7527feef | 124 | } >l1_data AT>ram_data |
b1e2c551 MF |
125 | __data_l1_lma = LOADADDR(.data_l1); |
126 | __data_l1_len = SIZEOF(.data_l1); | |
105be907 | 127 | ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data overflow!") |
d9a5d113 MF |
128 | |
129 | .bss : | |
130 | { | |
131 | . = ALIGN(4); | |
d9a5d113 MF |
132 | *(.sbss) *(.scommon) |
133 | *(.dynbss) | |
134 | *(.bss .bss.*) | |
135 | *(COMMON) | |
49508d4c | 136 | . = ALIGN(4); |
7527feef | 137 | } >ram_data |
c49eabef SZ |
138 | __bss_end = .; |
139 | __bss_start = ADDR(.bss); | |
b1e2c551 | 140 | __bss_len = SIZEOF(.bss); |
c49eabef | 141 | __init_end = .; |
d9a5d113 | 142 | } |