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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
51533b61 MS |
2 | #ifndef __intr_vect_defs_asm_h |
3 | #define __intr_vect_defs_asm_h | |
4 | ||
5 | /* | |
6 | * This file is autogenerated from | |
7 | * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r | |
8 | * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp | |
9 | * last modfied: Mon Apr 11 16:08:03 2005 | |
10 | * | |
11 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r | |
12 | * id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | |
13 | * Any changes here will be lost. | |
14 | * | |
15 | * -*- buffer-read-only: t -*- | |
16 | */ | |
17 | ||
18 | #ifndef REG_FIELD | |
19 | #define REG_FIELD( scope, reg, field, value ) \ | |
20 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | |
21 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | |
22 | #endif | |
23 | ||
24 | #ifndef REG_STATE | |
25 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | |
26 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | |
27 | #define REG_STATE_X_( k, shift ) (k << shift) | |
28 | #endif | |
29 | ||
30 | #ifndef REG_MASK | |
31 | #define REG_MASK( scope, reg, field ) \ | |
32 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | |
33 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | |
34 | #endif | |
35 | ||
36 | #ifndef REG_LSB | |
37 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | |
38 | #endif | |
39 | ||
40 | #ifndef REG_BIT | |
41 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | |
42 | #endif | |
43 | ||
44 | #ifndef REG_ADDR | |
45 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | |
46 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | |
47 | #endif | |
48 | ||
49 | #ifndef REG_ADDR_VECT | |
50 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
51 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | |
52 | STRIDE_##scope##_##reg ) | |
53 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | |
54 | ((inst) + offs + (index) * stride) | |
55 | #endif | |
56 | ||
57 | /* Register rw_mask, scope intr_vect, type rw */ | |
58 | #define reg_intr_vect_rw_mask___memarb___lsb 0 | |
59 | #define reg_intr_vect_rw_mask___memarb___width 1 | |
60 | #define reg_intr_vect_rw_mask___memarb___bit 0 | |
61 | #define reg_intr_vect_rw_mask___gen_io___lsb 1 | |
62 | #define reg_intr_vect_rw_mask___gen_io___width 1 | |
63 | #define reg_intr_vect_rw_mask___gen_io___bit 1 | |
64 | #define reg_intr_vect_rw_mask___iop0___lsb 2 | |
65 | #define reg_intr_vect_rw_mask___iop0___width 1 | |
66 | #define reg_intr_vect_rw_mask___iop0___bit 2 | |
67 | #define reg_intr_vect_rw_mask___iop1___lsb 3 | |
68 | #define reg_intr_vect_rw_mask___iop1___width 1 | |
69 | #define reg_intr_vect_rw_mask___iop1___bit 3 | |
70 | #define reg_intr_vect_rw_mask___iop2___lsb 4 | |
71 | #define reg_intr_vect_rw_mask___iop2___width 1 | |
72 | #define reg_intr_vect_rw_mask___iop2___bit 4 | |
73 | #define reg_intr_vect_rw_mask___iop3___lsb 5 | |
74 | #define reg_intr_vect_rw_mask___iop3___width 1 | |
75 | #define reg_intr_vect_rw_mask___iop3___bit 5 | |
76 | #define reg_intr_vect_rw_mask___dma0___lsb 6 | |
77 | #define reg_intr_vect_rw_mask___dma0___width 1 | |
78 | #define reg_intr_vect_rw_mask___dma0___bit 6 | |
79 | #define reg_intr_vect_rw_mask___dma1___lsb 7 | |
80 | #define reg_intr_vect_rw_mask___dma1___width 1 | |
81 | #define reg_intr_vect_rw_mask___dma1___bit 7 | |
82 | #define reg_intr_vect_rw_mask___dma2___lsb 8 | |
83 | #define reg_intr_vect_rw_mask___dma2___width 1 | |
84 | #define reg_intr_vect_rw_mask___dma2___bit 8 | |
85 | #define reg_intr_vect_rw_mask___dma3___lsb 9 | |
86 | #define reg_intr_vect_rw_mask___dma3___width 1 | |
87 | #define reg_intr_vect_rw_mask___dma3___bit 9 | |
88 | #define reg_intr_vect_rw_mask___dma4___lsb 10 | |
89 | #define reg_intr_vect_rw_mask___dma4___width 1 | |
90 | #define reg_intr_vect_rw_mask___dma4___bit 10 | |
91 | #define reg_intr_vect_rw_mask___dma5___lsb 11 | |
92 | #define reg_intr_vect_rw_mask___dma5___width 1 | |
93 | #define reg_intr_vect_rw_mask___dma5___bit 11 | |
94 | #define reg_intr_vect_rw_mask___dma6___lsb 12 | |
95 | #define reg_intr_vect_rw_mask___dma6___width 1 | |
96 | #define reg_intr_vect_rw_mask___dma6___bit 12 | |
97 | #define reg_intr_vect_rw_mask___dma7___lsb 13 | |
98 | #define reg_intr_vect_rw_mask___dma7___width 1 | |
99 | #define reg_intr_vect_rw_mask___dma7___bit 13 | |
100 | #define reg_intr_vect_rw_mask___dma8___lsb 14 | |
101 | #define reg_intr_vect_rw_mask___dma8___width 1 | |
102 | #define reg_intr_vect_rw_mask___dma8___bit 14 | |
103 | #define reg_intr_vect_rw_mask___dma9___lsb 15 | |
104 | #define reg_intr_vect_rw_mask___dma9___width 1 | |
105 | #define reg_intr_vect_rw_mask___dma9___bit 15 | |
106 | #define reg_intr_vect_rw_mask___ata___lsb 16 | |
107 | #define reg_intr_vect_rw_mask___ata___width 1 | |
108 | #define reg_intr_vect_rw_mask___ata___bit 16 | |
109 | #define reg_intr_vect_rw_mask___sser0___lsb 17 | |
110 | #define reg_intr_vect_rw_mask___sser0___width 1 | |
111 | #define reg_intr_vect_rw_mask___sser0___bit 17 | |
112 | #define reg_intr_vect_rw_mask___sser1___lsb 18 | |
113 | #define reg_intr_vect_rw_mask___sser1___width 1 | |
114 | #define reg_intr_vect_rw_mask___sser1___bit 18 | |
115 | #define reg_intr_vect_rw_mask___ser0___lsb 19 | |
116 | #define reg_intr_vect_rw_mask___ser0___width 1 | |
117 | #define reg_intr_vect_rw_mask___ser0___bit 19 | |
118 | #define reg_intr_vect_rw_mask___ser1___lsb 20 | |
119 | #define reg_intr_vect_rw_mask___ser1___width 1 | |
120 | #define reg_intr_vect_rw_mask___ser1___bit 20 | |
121 | #define reg_intr_vect_rw_mask___ser2___lsb 21 | |
122 | #define reg_intr_vect_rw_mask___ser2___width 1 | |
123 | #define reg_intr_vect_rw_mask___ser2___bit 21 | |
124 | #define reg_intr_vect_rw_mask___ser3___lsb 22 | |
125 | #define reg_intr_vect_rw_mask___ser3___width 1 | |
126 | #define reg_intr_vect_rw_mask___ser3___bit 22 | |
127 | #define reg_intr_vect_rw_mask___p21___lsb 23 | |
128 | #define reg_intr_vect_rw_mask___p21___width 1 | |
129 | #define reg_intr_vect_rw_mask___p21___bit 23 | |
130 | #define reg_intr_vect_rw_mask___eth0___lsb 24 | |
131 | #define reg_intr_vect_rw_mask___eth0___width 1 | |
132 | #define reg_intr_vect_rw_mask___eth0___bit 24 | |
133 | #define reg_intr_vect_rw_mask___eth1___lsb 25 | |
134 | #define reg_intr_vect_rw_mask___eth1___width 1 | |
135 | #define reg_intr_vect_rw_mask___eth1___bit 25 | |
136 | #define reg_intr_vect_rw_mask___timer___lsb 26 | |
137 | #define reg_intr_vect_rw_mask___timer___width 1 | |
138 | #define reg_intr_vect_rw_mask___timer___bit 26 | |
139 | #define reg_intr_vect_rw_mask___bif_arb___lsb 27 | |
140 | #define reg_intr_vect_rw_mask___bif_arb___width 1 | |
141 | #define reg_intr_vect_rw_mask___bif_arb___bit 27 | |
142 | #define reg_intr_vect_rw_mask___bif_dma___lsb 28 | |
143 | #define reg_intr_vect_rw_mask___bif_dma___width 1 | |
144 | #define reg_intr_vect_rw_mask___bif_dma___bit 28 | |
145 | #define reg_intr_vect_rw_mask___ext___lsb 29 | |
146 | #define reg_intr_vect_rw_mask___ext___width 1 | |
147 | #define reg_intr_vect_rw_mask___ext___bit 29 | |
148 | #define reg_intr_vect_rw_mask_offset 0 | |
149 | ||
150 | /* Register r_vect, scope intr_vect, type r */ | |
151 | #define reg_intr_vect_r_vect___memarb___lsb 0 | |
152 | #define reg_intr_vect_r_vect___memarb___width 1 | |
153 | #define reg_intr_vect_r_vect___memarb___bit 0 | |
154 | #define reg_intr_vect_r_vect___gen_io___lsb 1 | |
155 | #define reg_intr_vect_r_vect___gen_io___width 1 | |
156 | #define reg_intr_vect_r_vect___gen_io___bit 1 | |
157 | #define reg_intr_vect_r_vect___iop0___lsb 2 | |
158 | #define reg_intr_vect_r_vect___iop0___width 1 | |
159 | #define reg_intr_vect_r_vect___iop0___bit 2 | |
160 | #define reg_intr_vect_r_vect___iop1___lsb 3 | |
161 | #define reg_intr_vect_r_vect___iop1___width 1 | |
162 | #define reg_intr_vect_r_vect___iop1___bit 3 | |
163 | #define reg_intr_vect_r_vect___iop2___lsb 4 | |
164 | #define reg_intr_vect_r_vect___iop2___width 1 | |
165 | #define reg_intr_vect_r_vect___iop2___bit 4 | |
166 | #define reg_intr_vect_r_vect___iop3___lsb 5 | |
167 | #define reg_intr_vect_r_vect___iop3___width 1 | |
168 | #define reg_intr_vect_r_vect___iop3___bit 5 | |
169 | #define reg_intr_vect_r_vect___dma0___lsb 6 | |
170 | #define reg_intr_vect_r_vect___dma0___width 1 | |
171 | #define reg_intr_vect_r_vect___dma0___bit 6 | |
172 | #define reg_intr_vect_r_vect___dma1___lsb 7 | |
173 | #define reg_intr_vect_r_vect___dma1___width 1 | |
174 | #define reg_intr_vect_r_vect___dma1___bit 7 | |
175 | #define reg_intr_vect_r_vect___dma2___lsb 8 | |
176 | #define reg_intr_vect_r_vect___dma2___width 1 | |
177 | #define reg_intr_vect_r_vect___dma2___bit 8 | |
178 | #define reg_intr_vect_r_vect___dma3___lsb 9 | |
179 | #define reg_intr_vect_r_vect___dma3___width 1 | |
180 | #define reg_intr_vect_r_vect___dma3___bit 9 | |
181 | #define reg_intr_vect_r_vect___dma4___lsb 10 | |
182 | #define reg_intr_vect_r_vect___dma4___width 1 | |
183 | #define reg_intr_vect_r_vect___dma4___bit 10 | |
184 | #define reg_intr_vect_r_vect___dma5___lsb 11 | |
185 | #define reg_intr_vect_r_vect___dma5___width 1 | |
186 | #define reg_intr_vect_r_vect___dma5___bit 11 | |
187 | #define reg_intr_vect_r_vect___dma6___lsb 12 | |
188 | #define reg_intr_vect_r_vect___dma6___width 1 | |
189 | #define reg_intr_vect_r_vect___dma6___bit 12 | |
190 | #define reg_intr_vect_r_vect___dma7___lsb 13 | |
191 | #define reg_intr_vect_r_vect___dma7___width 1 | |
192 | #define reg_intr_vect_r_vect___dma7___bit 13 | |
193 | #define reg_intr_vect_r_vect___dma8___lsb 14 | |
194 | #define reg_intr_vect_r_vect___dma8___width 1 | |
195 | #define reg_intr_vect_r_vect___dma8___bit 14 | |
196 | #define reg_intr_vect_r_vect___dma9___lsb 15 | |
197 | #define reg_intr_vect_r_vect___dma9___width 1 | |
198 | #define reg_intr_vect_r_vect___dma9___bit 15 | |
199 | #define reg_intr_vect_r_vect___ata___lsb 16 | |
200 | #define reg_intr_vect_r_vect___ata___width 1 | |
201 | #define reg_intr_vect_r_vect___ata___bit 16 | |
202 | #define reg_intr_vect_r_vect___sser0___lsb 17 | |
203 | #define reg_intr_vect_r_vect___sser0___width 1 | |
204 | #define reg_intr_vect_r_vect___sser0___bit 17 | |
205 | #define reg_intr_vect_r_vect___sser1___lsb 18 | |
206 | #define reg_intr_vect_r_vect___sser1___width 1 | |
207 | #define reg_intr_vect_r_vect___sser1___bit 18 | |
208 | #define reg_intr_vect_r_vect___ser0___lsb 19 | |
209 | #define reg_intr_vect_r_vect___ser0___width 1 | |
210 | #define reg_intr_vect_r_vect___ser0___bit 19 | |
211 | #define reg_intr_vect_r_vect___ser1___lsb 20 | |
212 | #define reg_intr_vect_r_vect___ser1___width 1 | |
213 | #define reg_intr_vect_r_vect___ser1___bit 20 | |
214 | #define reg_intr_vect_r_vect___ser2___lsb 21 | |
215 | #define reg_intr_vect_r_vect___ser2___width 1 | |
216 | #define reg_intr_vect_r_vect___ser2___bit 21 | |
217 | #define reg_intr_vect_r_vect___ser3___lsb 22 | |
218 | #define reg_intr_vect_r_vect___ser3___width 1 | |
219 | #define reg_intr_vect_r_vect___ser3___bit 22 | |
220 | #define reg_intr_vect_r_vect___p21___lsb 23 | |
221 | #define reg_intr_vect_r_vect___p21___width 1 | |
222 | #define reg_intr_vect_r_vect___p21___bit 23 | |
223 | #define reg_intr_vect_r_vect___eth0___lsb 24 | |
224 | #define reg_intr_vect_r_vect___eth0___width 1 | |
225 | #define reg_intr_vect_r_vect___eth0___bit 24 | |
226 | #define reg_intr_vect_r_vect___eth1___lsb 25 | |
227 | #define reg_intr_vect_r_vect___eth1___width 1 | |
228 | #define reg_intr_vect_r_vect___eth1___bit 25 | |
229 | #define reg_intr_vect_r_vect___timer___lsb 26 | |
230 | #define reg_intr_vect_r_vect___timer___width 1 | |
231 | #define reg_intr_vect_r_vect___timer___bit 26 | |
232 | #define reg_intr_vect_r_vect___bif_arb___lsb 27 | |
233 | #define reg_intr_vect_r_vect___bif_arb___width 1 | |
234 | #define reg_intr_vect_r_vect___bif_arb___bit 27 | |
235 | #define reg_intr_vect_r_vect___bif_dma___lsb 28 | |
236 | #define reg_intr_vect_r_vect___bif_dma___width 1 | |
237 | #define reg_intr_vect_r_vect___bif_dma___bit 28 | |
238 | #define reg_intr_vect_r_vect___ext___lsb 29 | |
239 | #define reg_intr_vect_r_vect___ext___width 1 | |
240 | #define reg_intr_vect_r_vect___ext___bit 29 | |
241 | #define reg_intr_vect_r_vect_offset 4 | |
242 | ||
243 | /* Register r_masked_vect, scope intr_vect, type r */ | |
244 | #define reg_intr_vect_r_masked_vect___memarb___lsb 0 | |
245 | #define reg_intr_vect_r_masked_vect___memarb___width 1 | |
246 | #define reg_intr_vect_r_masked_vect___memarb___bit 0 | |
247 | #define reg_intr_vect_r_masked_vect___gen_io___lsb 1 | |
248 | #define reg_intr_vect_r_masked_vect___gen_io___width 1 | |
249 | #define reg_intr_vect_r_masked_vect___gen_io___bit 1 | |
250 | #define reg_intr_vect_r_masked_vect___iop0___lsb 2 | |
251 | #define reg_intr_vect_r_masked_vect___iop0___width 1 | |
252 | #define reg_intr_vect_r_masked_vect___iop0___bit 2 | |
253 | #define reg_intr_vect_r_masked_vect___iop1___lsb 3 | |
254 | #define reg_intr_vect_r_masked_vect___iop1___width 1 | |
255 | #define reg_intr_vect_r_masked_vect___iop1___bit 3 | |
256 | #define reg_intr_vect_r_masked_vect___iop2___lsb 4 | |
257 | #define reg_intr_vect_r_masked_vect___iop2___width 1 | |
258 | #define reg_intr_vect_r_masked_vect___iop2___bit 4 | |
259 | #define reg_intr_vect_r_masked_vect___iop3___lsb 5 | |
260 | #define reg_intr_vect_r_masked_vect___iop3___width 1 | |
261 | #define reg_intr_vect_r_masked_vect___iop3___bit 5 | |
262 | #define reg_intr_vect_r_masked_vect___dma0___lsb 6 | |
263 | #define reg_intr_vect_r_masked_vect___dma0___width 1 | |
264 | #define reg_intr_vect_r_masked_vect___dma0___bit 6 | |
265 | #define reg_intr_vect_r_masked_vect___dma1___lsb 7 | |
266 | #define reg_intr_vect_r_masked_vect___dma1___width 1 | |
267 | #define reg_intr_vect_r_masked_vect___dma1___bit 7 | |
268 | #define reg_intr_vect_r_masked_vect___dma2___lsb 8 | |
269 | #define reg_intr_vect_r_masked_vect___dma2___width 1 | |
270 | #define reg_intr_vect_r_masked_vect___dma2___bit 8 | |
271 | #define reg_intr_vect_r_masked_vect___dma3___lsb 9 | |
272 | #define reg_intr_vect_r_masked_vect___dma3___width 1 | |
273 | #define reg_intr_vect_r_masked_vect___dma3___bit 9 | |
274 | #define reg_intr_vect_r_masked_vect___dma4___lsb 10 | |
275 | #define reg_intr_vect_r_masked_vect___dma4___width 1 | |
276 | #define reg_intr_vect_r_masked_vect___dma4___bit 10 | |
277 | #define reg_intr_vect_r_masked_vect___dma5___lsb 11 | |
278 | #define reg_intr_vect_r_masked_vect___dma5___width 1 | |
279 | #define reg_intr_vect_r_masked_vect___dma5___bit 11 | |
280 | #define reg_intr_vect_r_masked_vect___dma6___lsb 12 | |
281 | #define reg_intr_vect_r_masked_vect___dma6___width 1 | |
282 | #define reg_intr_vect_r_masked_vect___dma6___bit 12 | |
283 | #define reg_intr_vect_r_masked_vect___dma7___lsb 13 | |
284 | #define reg_intr_vect_r_masked_vect___dma7___width 1 | |
285 | #define reg_intr_vect_r_masked_vect___dma7___bit 13 | |
286 | #define reg_intr_vect_r_masked_vect___dma8___lsb 14 | |
287 | #define reg_intr_vect_r_masked_vect___dma8___width 1 | |
288 | #define reg_intr_vect_r_masked_vect___dma8___bit 14 | |
289 | #define reg_intr_vect_r_masked_vect___dma9___lsb 15 | |
290 | #define reg_intr_vect_r_masked_vect___dma9___width 1 | |
291 | #define reg_intr_vect_r_masked_vect___dma9___bit 15 | |
292 | #define reg_intr_vect_r_masked_vect___ata___lsb 16 | |
293 | #define reg_intr_vect_r_masked_vect___ata___width 1 | |
294 | #define reg_intr_vect_r_masked_vect___ata___bit 16 | |
295 | #define reg_intr_vect_r_masked_vect___sser0___lsb 17 | |
296 | #define reg_intr_vect_r_masked_vect___sser0___width 1 | |
297 | #define reg_intr_vect_r_masked_vect___sser0___bit 17 | |
298 | #define reg_intr_vect_r_masked_vect___sser1___lsb 18 | |
299 | #define reg_intr_vect_r_masked_vect___sser1___width 1 | |
300 | #define reg_intr_vect_r_masked_vect___sser1___bit 18 | |
301 | #define reg_intr_vect_r_masked_vect___ser0___lsb 19 | |
302 | #define reg_intr_vect_r_masked_vect___ser0___width 1 | |
303 | #define reg_intr_vect_r_masked_vect___ser0___bit 19 | |
304 | #define reg_intr_vect_r_masked_vect___ser1___lsb 20 | |
305 | #define reg_intr_vect_r_masked_vect___ser1___width 1 | |
306 | #define reg_intr_vect_r_masked_vect___ser1___bit 20 | |
307 | #define reg_intr_vect_r_masked_vect___ser2___lsb 21 | |
308 | #define reg_intr_vect_r_masked_vect___ser2___width 1 | |
309 | #define reg_intr_vect_r_masked_vect___ser2___bit 21 | |
310 | #define reg_intr_vect_r_masked_vect___ser3___lsb 22 | |
311 | #define reg_intr_vect_r_masked_vect___ser3___width 1 | |
312 | #define reg_intr_vect_r_masked_vect___ser3___bit 22 | |
313 | #define reg_intr_vect_r_masked_vect___p21___lsb 23 | |
314 | #define reg_intr_vect_r_masked_vect___p21___width 1 | |
315 | #define reg_intr_vect_r_masked_vect___p21___bit 23 | |
316 | #define reg_intr_vect_r_masked_vect___eth0___lsb 24 | |
317 | #define reg_intr_vect_r_masked_vect___eth0___width 1 | |
318 | #define reg_intr_vect_r_masked_vect___eth0___bit 24 | |
319 | #define reg_intr_vect_r_masked_vect___eth1___lsb 25 | |
320 | #define reg_intr_vect_r_masked_vect___eth1___width 1 | |
321 | #define reg_intr_vect_r_masked_vect___eth1___bit 25 | |
322 | #define reg_intr_vect_r_masked_vect___timer___lsb 26 | |
323 | #define reg_intr_vect_r_masked_vect___timer___width 1 | |
324 | #define reg_intr_vect_r_masked_vect___timer___bit 26 | |
325 | #define reg_intr_vect_r_masked_vect___bif_arb___lsb 27 | |
326 | #define reg_intr_vect_r_masked_vect___bif_arb___width 1 | |
327 | #define reg_intr_vect_r_masked_vect___bif_arb___bit 27 | |
328 | #define reg_intr_vect_r_masked_vect___bif_dma___lsb 28 | |
329 | #define reg_intr_vect_r_masked_vect___bif_dma___width 1 | |
330 | #define reg_intr_vect_r_masked_vect___bif_dma___bit 28 | |
331 | #define reg_intr_vect_r_masked_vect___ext___lsb 29 | |
332 | #define reg_intr_vect_r_masked_vect___ext___width 1 | |
333 | #define reg_intr_vect_r_masked_vect___ext___bit 29 | |
334 | #define reg_intr_vect_r_masked_vect_offset 8 | |
335 | ||
336 | /* Register r_nmi, scope intr_vect, type r */ | |
337 | #define reg_intr_vect_r_nmi___ext___lsb 0 | |
338 | #define reg_intr_vect_r_nmi___ext___width 1 | |
339 | #define reg_intr_vect_r_nmi___ext___bit 0 | |
340 | #define reg_intr_vect_r_nmi___watchdog___lsb 1 | |
341 | #define reg_intr_vect_r_nmi___watchdog___width 1 | |
342 | #define reg_intr_vect_r_nmi___watchdog___bit 1 | |
343 | #define reg_intr_vect_r_nmi_offset 12 | |
344 | ||
345 | /* Register r_guru, scope intr_vect, type r */ | |
346 | #define reg_intr_vect_r_guru___jtag___lsb 0 | |
347 | #define reg_intr_vect_r_guru___jtag___width 1 | |
348 | #define reg_intr_vect_r_guru___jtag___bit 0 | |
349 | #define reg_intr_vect_r_guru_offset 16 | |
350 | ||
351 | ||
352 | /* Constants */ | |
353 | #define regk_intr_vect_off 0x00000000 | |
354 | #define regk_intr_vect_on 0x00000001 | |
355 | #define regk_intr_vect_rw_mask_default 0x00000000 | |
356 | #endif /* __intr_vect_defs_asm_h */ |