[people/arne_f/kernel.git] / arch / cris / include / arch-v32 / arch / hwregs / iop / asm / iop_mpu_defs_asm.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __iop_mpu_defs_asm_h
#define __iop_mpu_defs_asm_h

/*
 * This file is autogenerated from
 *   file:           ../../inst/io_proc/rtl/iop_mpu.r
 *     id:           iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp
 *     last modfied: Mon Apr 11 16:08:45 2005
 *
 *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r
 *      id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */

#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif

#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif

#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif

#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif

#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
			 STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
                          ((inst) + offs + (index) * stride)
#endif

#define STRIDE_iop_mpu_rw_r 4
/* Register rw_r, scope iop_mpu, type rw */
#define reg_iop_mpu_rw_r_offset 0

/* Register rw_ctrl, scope iop_mpu, type rw */
#define reg_iop_mpu_rw_ctrl___en___lsb 0
#define reg_iop_mpu_rw_ctrl___en___width 1
#define reg_iop_mpu_rw_ctrl___en___bit 0
#define reg_iop_mpu_rw_ctrl_offset 128

/* Register r_pc, scope iop_mpu, type r */
#define reg_iop_mpu_r_pc___addr___lsb 0
#define reg_iop_mpu_r_pc___addr___width 12
#define reg_iop_mpu_r_pc_offset 132

/* Register r_stat, scope iop_mpu, type r */
#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0
#define reg_iop_mpu_r_stat___instr_reg_busy___width 1
#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0
#define reg_iop_mpu_r_stat___intr_busy___lsb 1
#define reg_iop_mpu_r_stat___intr_busy___width 1
#define reg_iop_mpu_r_stat___intr_busy___bit 1
#define reg_iop_mpu_r_stat___intr_vect___lsb 2
#define reg_iop_mpu_r_stat___intr_vect___width 16
#define reg_iop_mpu_r_stat_offset 136

/* Register rw_instr, scope iop_mpu, type rw */
#define reg_iop_mpu_rw_instr_offset 140

/* Register rw_immediate, scope iop_mpu, type rw */
#define reg_iop_mpu_rw_immediate_offset 144

/* Register r_trace, scope iop_mpu, type r */
#define reg_iop_mpu_r_trace___intr_vect___lsb 0
#define reg_iop_mpu_r_trace___intr_vect___width 16
#define reg_iop_mpu_r_trace___pc___lsb 16
#define reg_iop_mpu_r_trace___pc___width 12
#define reg_iop_mpu_r_trace___en___lsb 28
#define reg_iop_mpu_r_trace___en___width 1
#define reg_iop_mpu_r_trace___en___bit 28
#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29
#define reg_iop_mpu_r_trace___instr_reg_busy___width 1
#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29
#define reg_iop_mpu_r_trace___intr_busy___lsb 30
#define reg_iop_mpu_r_trace___intr_busy___width 1
#define reg_iop_mpu_r_trace___intr_busy___bit 30
#define reg_iop_mpu_r_trace_offset 148

/* Register r_wr_stat, scope iop_mpu, type r */
#define reg_iop_mpu_r_wr_stat___r0___lsb 0
#define reg_iop_mpu_r_wr_stat___r0___width 1
#define reg_iop_mpu_r_wr_stat___r0___bit 0
#define reg_iop_mpu_r_wr_stat___r1___lsb 1
#define reg_iop_mpu_r_wr_stat___r1___width 1
#define reg_iop_mpu_r_wr_stat___r1___bit 1
#define reg_iop_mpu_r_wr_stat___r2___lsb 2
#define reg_iop_mpu_r_wr_stat___r2___width 1
#define reg_iop_mpu_r_wr_stat___r2___bit 2
#define reg_iop_mpu_r_wr_stat___r3___lsb 3
#define reg_iop_mpu_r_wr_stat___r3___width 1
#define reg_iop_mpu_r_wr_stat___r3___bit 3
#define reg_iop_mpu_r_wr_stat___r4___lsb 4
#define reg_iop_mpu_r_wr_stat___r4___width 1
#define reg_iop_mpu_r_wr_stat___r4___bit 4
#define reg_iop_mpu_r_wr_stat___r5___lsb 5
#define reg_iop_mpu_r_wr_stat___r5___width 1
#define reg_iop_mpu_r_wr_stat___r5___bit 5
#define reg_iop_mpu_r_wr_stat___r6___lsb 6
#define reg_iop_mpu_r_wr_stat___r6___width 1
#define reg_iop_mpu_r_wr_stat___r6___bit 6
#define reg_iop_mpu_r_wr_stat___r7___lsb 7
#define reg_iop_mpu_r_wr_stat___r7___width 1
#define reg_iop_mpu_r_wr_stat___r7___bit 7
#define reg_iop_mpu_r_wr_stat___r8___lsb 8
#define reg_iop_mpu_r_wr_stat___r8___width 1
#define reg_iop_mpu_r_wr_stat___r8___bit 8
#define reg_iop_mpu_r_wr_stat___r9___lsb 9
#define reg_iop_mpu_r_wr_stat___r9___width 1
#define reg_iop_mpu_r_wr_stat___r9___bit 9
#define reg_iop_mpu_r_wr_stat___r10___lsb 10
#define reg_iop_mpu_r_wr_stat___r10___width 1
#define reg_iop_mpu_r_wr_stat___r10___bit 10
#define reg_iop_mpu_r_wr_stat___r11___lsb 11
#define reg_iop_mpu_r_wr_stat___r11___width 1
#define reg_iop_mpu_r_wr_stat___r11___bit 11
#define reg_iop_mpu_r_wr_stat___r12___lsb 12
#define reg_iop_mpu_r_wr_stat___r12___width 1
#define reg_iop_mpu_r_wr_stat___r12___bit 12
#define reg_iop_mpu_r_wr_stat___r13___lsb 13
#define reg_iop_mpu_r_wr_stat___r13___width 1
#define reg_iop_mpu_r_wr_stat___r13___bit 13
#define reg_iop_mpu_r_wr_stat___r14___lsb 14
#define reg_iop_mpu_r_wr_stat___r14___width 1
#define reg_iop_mpu_r_wr_stat___r14___bit 14
#define reg_iop_mpu_r_wr_stat___r15___lsb 15
#define reg_iop_mpu_r_wr_stat___r15___width 1
#define reg_iop_mpu_r_wr_stat___r15___bit 15
#define reg_iop_mpu_r_wr_stat_offset 152

#define STRIDE_iop_mpu_rw_thread 4
/* Register rw_thread, scope iop_mpu, type rw */
#define reg_iop_mpu_rw_thread___addr___lsb 0
#define reg_iop_mpu_rw_thread___addr___width 12
#define reg_iop_mpu_rw_thread_offset 156

#define STRIDE_iop_mpu_rw_intr 4
/* Register rw_intr, scope iop_mpu, type rw */
#define reg_iop_mpu_rw_intr___addr___lsb 0
#define reg_iop_mpu_rw_intr___addr___width 12
#define reg_iop_mpu_rw_intr_offset 196


/* Constants */
#define regk_iop_mpu_no                           0x00000000
#define regk_iop_mpu_r_pc_default                 0x00000000
#define regk_iop_mpu_rw_ctrl_default              0x00000000
#define regk_iop_mpu_rw_intr_size                 0x00000010
#define regk_iop_mpu_rw_r_size                    0x00000010
#define regk_iop_mpu_rw_thread_default            0x00000000
#define regk_iop_mpu_rw_thread_size               0x00000004
#define regk_iop_mpu_yes                          0x00000001
#endif /* __iop_mpu_defs_asm_h */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
51533b61 MS	2	#ifndef __iop_mpu_defs_asm_h
	3	#define __iop_mpu_defs_asm_h
	4
	5	/*
	6	* This file is autogenerated from
	7	* file: ../../inst/io_proc/rtl/iop_mpu.r
	8	* id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp
	9	* last modfied: Mon Apr 11 16:08:45 2005
	10	*
	11	* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r
	12	* id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
	13	* Any changes here will be lost.
	14	*
	15	* -- buffer-read-only: t --
	16	*/
	17
	18	#ifndef REG_FIELD
	19	#define REG_FIELD( scope, reg, field, value ) \
	20	REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
	21	#define REG_FIELD_X_( value, shift ) ((value) << shift)
	22	#endif
	23
	24	#ifndef REG_STATE
	25	#define REG_STATE( scope, reg, field, symbolic_value ) \
	26	REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
	27	#define REG_STATE_X_( k, shift ) (k << shift)
	28	#endif
	29
	30	#ifndef REG_MASK
	31	#define REG_MASK( scope, reg, field ) \
	32	REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
	33	#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
	34	#endif
	35
	36	#ifndef REG_LSB
	37	#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
	38	#endif
	39
	40	#ifndef REG_BIT
	41	#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
	42	#endif
	43
	44	#ifndef REG_ADDR
	45	#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
	46	#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
	47	#endif
	48
	49	#ifndef REG_ADDR_VECT
	50	#define REG_ADDR_VECT( scope, inst, reg, index ) \
	51	REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
	52	STRIDE_##scope##_##reg )
	53	#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
	54	((inst) + offs + (index) * stride)
	55	#endif
	56
	57	#define STRIDE_iop_mpu_rw_r 4
	58	/* Register rw_r, scope iop_mpu, type rw */
	59	#define reg_iop_mpu_rw_r_offset 0
	60
	61	/* Register rw_ctrl, scope iop_mpu, type rw */
	62	#define reg_iop_mpu_rw_ctrl___en___lsb 0
	63	#define reg_iop_mpu_rw_ctrl___en___width 1
	64	#define reg_iop_mpu_rw_ctrl___en___bit 0
	65	#define reg_iop_mpu_rw_ctrl_offset 128
66
67	/* Register r_pc, scope iop_mpu, type r */
68	#define reg_iop_mpu_r_pc___addr___lsb 0
69	#define reg_iop_mpu_r_pc___addr___width 12
70	#define reg_iop_mpu_r_pc_offset 132
71
72	/* Register r_stat, scope iop_mpu, type r */
73	#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0
74	#define reg_iop_mpu_r_stat___instr_reg_busy___width 1
75	#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0
76	#define reg_iop_mpu_r_stat___intr_busy___lsb 1
77	#define reg_iop_mpu_r_stat___intr_busy___width 1
78	#define reg_iop_mpu_r_stat___intr_busy___bit 1
79	#define reg_iop_mpu_r_stat___intr_vect___lsb 2
80	#define reg_iop_mpu_r_stat___intr_vect___width 16
81	#define reg_iop_mpu_r_stat_offset 136
82
83	/* Register rw_instr, scope iop_mpu, type rw */
84	#define reg_iop_mpu_rw_instr_offset 140
85
86	/* Register rw_immediate, scope iop_mpu, type rw */
87	#define reg_iop_mpu_rw_immediate_offset 144
88
89	/* Register r_trace, scope iop_mpu, type r */
90	#define reg_iop_mpu_r_trace___intr_vect___lsb 0
91	#define reg_iop_mpu_r_trace___intr_vect___width 16
92	#define reg_iop_mpu_r_trace___pc___lsb 16
93	#define reg_iop_mpu_r_trace___pc___width 12
94	#define reg_iop_mpu_r_trace___en___lsb 28
95	#define reg_iop_mpu_r_trace___en___width 1
96	#define reg_iop_mpu_r_trace___en___bit 28
97	#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29
98	#define reg_iop_mpu_r_trace___instr_reg_busy___width 1
99	#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29
100	#define reg_iop_mpu_r_trace___intr_busy___lsb 30
101	#define reg_iop_mpu_r_trace___intr_busy___width 1
102	#define reg_iop_mpu_r_trace___intr_busy___bit 30
103	#define reg_iop_mpu_r_trace_offset 148
104
105	/* Register r_wr_stat, scope iop_mpu, type r */
106	#define reg_iop_mpu_r_wr_stat___r0___lsb 0
107	#define reg_iop_mpu_r_wr_stat___r0___width 1
108	#define reg_iop_mpu_r_wr_stat___r0___bit 0
109	#define reg_iop_mpu_r_wr_stat___r1___lsb 1
110	#define reg_iop_mpu_r_wr_stat___r1___width 1
111	#define reg_iop_mpu_r_wr_stat___r1___bit 1
112	#define reg_iop_mpu_r_wr_stat___r2___lsb 2
113	#define reg_iop_mpu_r_wr_stat___r2___width 1
114	#define reg_iop_mpu_r_wr_stat___r2___bit 2
115	#define reg_iop_mpu_r_wr_stat___r3___lsb 3
116	#define reg_iop_mpu_r_wr_stat___r3___width 1
117	#define reg_iop_mpu_r_wr_stat___r3___bit 3
118	#define reg_iop_mpu_r_wr_stat___r4___lsb 4
119	#define reg_iop_mpu_r_wr_stat___r4___width 1
120	#define reg_iop_mpu_r_wr_stat___r4___bit 4
121	#define reg_iop_mpu_r_wr_stat___r5___lsb 5
122	#define reg_iop_mpu_r_wr_stat___r5___width 1
123	#define reg_iop_mpu_r_wr_stat___r5___bit 5
124	#define reg_iop_mpu_r_wr_stat___r6___lsb 6
125	#define reg_iop_mpu_r_wr_stat___r6___width 1
126	#define reg_iop_mpu_r_wr_stat___r6___bit 6
127	#define reg_iop_mpu_r_wr_stat___r7___lsb 7
128	#define reg_iop_mpu_r_wr_stat___r7___width 1
129	#define reg_iop_mpu_r_wr_stat___r7___bit 7
130	#define reg_iop_mpu_r_wr_stat___r8___lsb 8
131	#define reg_iop_mpu_r_wr_stat___r8___width 1
132	#define reg_iop_mpu_r_wr_stat___r8___bit 8
133	#define reg_iop_mpu_r_wr_stat___r9___lsb 9
134	#define reg_iop_mpu_r_wr_stat___r9___width 1
135	#define reg_iop_mpu_r_wr_stat___r9___bit 9
136	#define reg_iop_mpu_r_wr_stat___r10___lsb 10
137	#define reg_iop_mpu_r_wr_stat___r10___width 1
138	#define reg_iop_mpu_r_wr_stat___r10___bit 10
139	#define reg_iop_mpu_r_wr_stat___r11___lsb 11
140	#define reg_iop_mpu_r_wr_stat___r11___width 1
141	#define reg_iop_mpu_r_wr_stat___r11___bit 11
142	#define reg_iop_mpu_r_wr_stat___r12___lsb 12
143	#define reg_iop_mpu_r_wr_stat___r12___width 1
144	#define reg_iop_mpu_r_wr_stat___r12___bit 12
145	#define reg_iop_mpu_r_wr_stat___r13___lsb 13
146	#define reg_iop_mpu_r_wr_stat___r13___width 1
147	#define reg_iop_mpu_r_wr_stat___r13___bit 13
148	#define reg_iop_mpu_r_wr_stat___r14___lsb 14
149	#define reg_iop_mpu_r_wr_stat___r14___width 1
150	#define reg_iop_mpu_r_wr_stat___r14___bit 14
151	#define reg_iop_mpu_r_wr_stat___r15___lsb 15
152	#define reg_iop_mpu_r_wr_stat___r15___width 1
153	#define reg_iop_mpu_r_wr_stat___r15___bit 15
154	#define reg_iop_mpu_r_wr_stat_offset 152
155
156	#define STRIDE_iop_mpu_rw_thread 4
157	/* Register rw_thread, scope iop_mpu, type rw */
158	#define reg_iop_mpu_rw_thread___addr___lsb 0
159	#define reg_iop_mpu_rw_thread___addr___width 12
160	#define reg_iop_mpu_rw_thread_offset 156
161
162	#define STRIDE_iop_mpu_rw_intr 4
163	/* Register rw_intr, scope iop_mpu, type rw */
164	#define reg_iop_mpu_rw_intr___addr___lsb 0
165	#define reg_iop_mpu_rw_intr___addr___width 12
166	#define reg_iop_mpu_rw_intr_offset 196
167
168
169	/* Constants */
170	#define regk_iop_mpu_no 0x00000000
171	#define regk_iop_mpu_r_pc_default 0x00000000
172	#define regk_iop_mpu_rw_ctrl_default 0x00000000
173	#define regk_iop_mpu_rw_intr_size 0x00000010
174	#define regk_iop_mpu_rw_r_size 0x00000010
175	#define regk_iop_mpu_rw_thread_default 0x00000000
176	#define regk_iop_mpu_rw_thread_size 0x00000004
177	#define regk_iop_mpu_yes 0x00000001
178	#endif /* __iop_mpu_defs_asm_h */