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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
58d08319 JN |
2 | #ifndef __clkgen_defs_asm_h |
3 | #define __clkgen_defs_asm_h | |
4 | ||
5 | /* | |
6 | * This file is autogenerated from | |
7 | * file: clkgen.r | |
8 | * | |
9 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r | |
10 | * Any changes here will be lost. | |
11 | * | |
12 | * -*- buffer-read-only: t -*- | |
13 | */ | |
14 | ||
15 | #ifndef REG_FIELD | |
16 | #define REG_FIELD( scope, reg, field, value ) \ | |
17 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | |
18 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | |
19 | #endif | |
20 | ||
21 | #ifndef REG_STATE | |
22 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | |
23 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | |
24 | #define REG_STATE_X_( k, shift ) (k << shift) | |
25 | #endif | |
26 | ||
27 | #ifndef REG_MASK | |
28 | #define REG_MASK( scope, reg, field ) \ | |
29 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | |
30 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | |
31 | #endif | |
32 | ||
33 | #ifndef REG_LSB | |
34 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | |
35 | #endif | |
36 | ||
37 | #ifndef REG_BIT | |
38 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | |
39 | #endif | |
40 | ||
41 | #ifndef REG_ADDR | |
42 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | |
43 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | |
44 | #endif | |
45 | ||
46 | #ifndef REG_ADDR_VECT | |
47 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
48 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | |
49 | STRIDE_##scope##_##reg ) | |
50 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | |
51 | ((inst) + offs + (index) * stride) | |
52 | #endif | |
53 | ||
54 | /* Register r_bootsel, scope clkgen, type r */ | |
55 | #define reg_clkgen_r_bootsel___boot_mode___lsb 0 | |
56 | #define reg_clkgen_r_bootsel___boot_mode___width 5 | |
57 | #define reg_clkgen_r_bootsel___intern_main_clk___lsb 5 | |
58 | #define reg_clkgen_r_bootsel___intern_main_clk___width 1 | |
59 | #define reg_clkgen_r_bootsel___intern_main_clk___bit 5 | |
60 | #define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6 | |
61 | #define reg_clkgen_r_bootsel___extern_usb2_clk___width 1 | |
62 | #define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6 | |
63 | #define reg_clkgen_r_bootsel_offset 0 | |
64 | ||
65 | /* Register rw_clk_ctrl, scope clkgen, type rw */ | |
66 | #define reg_clkgen_rw_clk_ctrl___pll___lsb 0 | |
67 | #define reg_clkgen_rw_clk_ctrl___pll___width 1 | |
68 | #define reg_clkgen_rw_clk_ctrl___pll___bit 0 | |
69 | #define reg_clkgen_rw_clk_ctrl___cpu___lsb 1 | |
70 | #define reg_clkgen_rw_clk_ctrl___cpu___width 1 | |
71 | #define reg_clkgen_rw_clk_ctrl___cpu___bit 1 | |
72 | #define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2 | |
73 | #define reg_clkgen_rw_clk_ctrl___iop_usb___width 1 | |
74 | #define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2 | |
75 | #define reg_clkgen_rw_clk_ctrl___vin___lsb 3 | |
76 | #define reg_clkgen_rw_clk_ctrl___vin___width 1 | |
77 | #define reg_clkgen_rw_clk_ctrl___vin___bit 3 | |
78 | #define reg_clkgen_rw_clk_ctrl___sclr___lsb 4 | |
79 | #define reg_clkgen_rw_clk_ctrl___sclr___width 1 | |
80 | #define reg_clkgen_rw_clk_ctrl___sclr___bit 4 | |
81 | #define reg_clkgen_rw_clk_ctrl___h264___lsb 5 | |
82 | #define reg_clkgen_rw_clk_ctrl___h264___width 1 | |
83 | #define reg_clkgen_rw_clk_ctrl___h264___bit 5 | |
84 | #define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6 | |
85 | #define reg_clkgen_rw_clk_ctrl___ddr2___width 1 | |
86 | #define reg_clkgen_rw_clk_ctrl___ddr2___bit 6 | |
87 | #define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7 | |
88 | #define reg_clkgen_rw_clk_ctrl___vout_hist___width 1 | |
89 | #define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7 | |
90 | #define reg_clkgen_rw_clk_ctrl___eth___lsb 8 | |
91 | #define reg_clkgen_rw_clk_ctrl___eth___width 1 | |
92 | #define reg_clkgen_rw_clk_ctrl___eth___bit 8 | |
93 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9 | |
94 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1 | |
95 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9 | |
96 | #define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10 | |
97 | #define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1 | |
98 | #define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10 | |
99 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11 | |
100 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1 | |
101 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11 | |
102 | #define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12 | |
103 | #define reg_clkgen_rw_clk_ctrl___jpeg___width 1 | |
104 | #define reg_clkgen_rw_clk_ctrl___jpeg___bit 12 | |
105 | #define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13 | |
106 | #define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1 | |
107 | #define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13 | |
108 | #define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14 | |
109 | #define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1 | |
110 | #define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14 | |
111 | #define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15 | |
112 | #define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1 | |
113 | #define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15 | |
114 | #define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16 | |
115 | #define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1 | |
116 | #define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16 | |
117 | #define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17 | |
118 | #define reg_clkgen_rw_clk_ctrl___dma9_11___width 1 | |
119 | #define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17 | |
120 | #define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18 | |
121 | #define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1 | |
122 | #define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18 | |
123 | #define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19 | |
124 | #define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1 | |
125 | #define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19 | |
126 | #define reg_clkgen_rw_clk_ctrl_offset 4 | |
127 | ||
128 | ||
129 | /* Constants */ | |
130 | #define regk_clkgen_eth1000_rx 0x0000000c | |
131 | #define regk_clkgen_eth1000_tx 0x0000000e | |
132 | #define regk_clkgen_eth100_rx 0x0000001d | |
133 | #define regk_clkgen_eth100_rx_half 0x0000001c | |
134 | #define regk_clkgen_eth100_tx 0x0000001f | |
135 | #define regk_clkgen_eth100_tx_half 0x0000001e | |
136 | #define regk_clkgen_nand_3_2 0x00000000 | |
137 | #define regk_clkgen_nand_3_2_0x30 0x00000002 | |
138 | #define regk_clkgen_nand_3_2_0x30_pll 0x00000012 | |
139 | #define regk_clkgen_nand_3_2_pll 0x00000010 | |
140 | #define regk_clkgen_nand_3_3 0x00000001 | |
141 | #define regk_clkgen_nand_3_3_0x30 0x00000003 | |
142 | #define regk_clkgen_nand_3_3_0x30_pll 0x00000013 | |
143 | #define regk_clkgen_nand_3_3_pll 0x00000011 | |
144 | #define regk_clkgen_nand_4_2 0x00000004 | |
145 | #define regk_clkgen_nand_4_2_0x30 0x00000006 | |
146 | #define regk_clkgen_nand_4_2_0x30_pll 0x00000016 | |
147 | #define regk_clkgen_nand_4_2_pll 0x00000014 | |
148 | #define regk_clkgen_nand_4_3 0x00000005 | |
149 | #define regk_clkgen_nand_4_3_0x30 0x00000007 | |
150 | #define regk_clkgen_nand_4_3_0x30_pll 0x00000017 | |
151 | #define regk_clkgen_nand_4_3_pll 0x00000015 | |
152 | #define regk_clkgen_nand_5_2 0x00000008 | |
153 | #define regk_clkgen_nand_5_2_0x30 0x0000000a | |
154 | #define regk_clkgen_nand_5_2_0x30_pll 0x0000001a | |
155 | #define regk_clkgen_nand_5_2_pll 0x00000018 | |
156 | #define regk_clkgen_nand_5_3 0x00000009 | |
157 | #define regk_clkgen_nand_5_3_0x30 0x0000000b | |
158 | #define regk_clkgen_nand_5_3_0x30_pll 0x0000001b | |
159 | #define regk_clkgen_nand_5_3_pll 0x00000019 | |
160 | #define regk_clkgen_no 0x00000000 | |
161 | #define regk_clkgen_rw_clk_ctrl_default 0x00000002 | |
162 | #define regk_clkgen_ser 0x0000000d | |
163 | #define regk_clkgen_ser_pll 0x0000000f | |
164 | #define regk_clkgen_yes 0x00000001 | |
165 | #endif /* __clkgen_defs_asm_h */ |