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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
a3af54ff JN |
2 | #ifndef _ASM_ARCH_CRIS_DMA_H |
3 | #define _ASM_ARCH_CRIS_DMA_H | |
4 | ||
5 | /* Defines for using and allocating dma channels. */ | |
6 | ||
7 | #define MAX_DMA_CHANNELS 10 | |
8 | ||
9 | #define NETWORK_ETH0_TX_DMA_NBR 0 /* Ethernet 0 out. */ | |
10 | #define NETWORK_ETH0 RX_DMA_NBR 1 /* Ethernet 0 in. */ | |
11 | ||
12 | #define IO_PROC_DMA0_TX_DMA_NBR 2 /* IO processor DMA0 out. */ | |
13 | #define IO_PROC_DMA0_RX_DMA_NBR 3 /* IO processor DMA0 in. */ | |
14 | ||
15 | #define ATA_TX_DMA_NBR 2 /* ATA interface out. */ | |
16 | #define ATA_RX_DMA_NBR 3 /* ATA interface in. */ | |
17 | ||
18 | #define ASYNC_SER2_TX_DMA_NBR 2 /* Asynchronous serial port 2 out. */ | |
19 | #define ASYNC_SER2_RX_DMA_NBR 3 /* Asynchronous serial port 2 in. */ | |
20 | ||
21 | #define IO_PROC_DMA1_TX_DMA_NBR 4 /* IO processor DMA1 out. */ | |
22 | #define IO_PROC_DMA1_RX_DMA_NBR 5 /* IO processor DMA1 in. */ | |
23 | ||
24 | #define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */ | |
25 | #define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */ | |
26 | ||
27 | #define SYNC_SER0_TX_DMA_NBR 4 /* Synchronous serial port 0 out. */ | |
28 | #define SYNC_SER0_RX_DMA_NBR 5 /* Synchronous serial port 0 in. */ | |
29 | ||
30 | #define EXTDMA0_TX_DMA_NBR 6 /* External DMA 0 out. */ | |
31 | #define EXTDMA1_RX_DMA_NBR 7 /* External DMA 1 in. */ | |
32 | ||
33 | #define ASYNC_SER0_TX_DMA_NBR 6 /* Asynchronous serial port 0 out. */ | |
34 | #define ASYNC_SER0_RX_DMA_NBR 7 /* Asynchronous serial port 0 in. */ | |
35 | ||
36 | #define SYNC_SER1_TX_DMA_NBR 6 /* Synchronous serial port 1 out. */ | |
37 | #define SYNC_SER1_RX_DMA_NBR 7 /* Synchronous serial port 1 in. */ | |
38 | ||
39 | #define NETWORK_ETH1_TX_DMA_NBR 6 /* Ethernet 1 out. */ | |
40 | #define NETWORK_ETH1_RX_DMA_NBR 7 /* Ethernet 1 in. */ | |
41 | ||
42 | #define EXTDMA2_TX_DMA_NBR 8 /* External DMA 2 out. */ | |
43 | #define EXTDMA3_RX_DMA_NBR 9 /* External DMA 3 in. */ | |
44 | ||
45 | #define STRCOP_TX_DMA_NBR 8 /* Stream co-processor out. */ | |
46 | #define STRCOP_RX_DMA_NBR 9 /* Stream co-processor in. */ | |
47 | ||
48 | #define ASYNC_SER3_TX_DMA_NBR 8 /* Asynchronous serial port 3 out. */ | |
49 | #define ASYNC_SER3_RX_DMA_NBR 9 /* Asynchronous serial port 3 in. */ | |
50 | ||
51 | enum dma_owner { | |
52 | dma_eth0, | |
53 | dma_eth1, | |
54 | dma_iop0, | |
55 | dma_iop1, | |
56 | dma_ser0, | |
57 | dma_ser1, | |
58 | dma_ser2, | |
59 | dma_ser3, | |
60 | dma_sser0, | |
61 | dma_sser1, | |
62 | dma_ata, | |
63 | dma_strp, | |
64 | dma_ext0, | |
65 | dma_ext1, | |
66 | dma_ext2, | |
67 | dma_ext3 | |
68 | }; | |
69 | ||
70 | int crisv32_request_dma(unsigned int dmanr, const char *device_id, | |
71 | unsigned options, unsigned bandwidth, | |
72 | enum dma_owner owner); | |
73 | void crisv32_free_dma(unsigned int dmanr); | |
74 | ||
75 | /* Masks used by crisv32_request_dma options: */ | |
76 | #define DMA_VERBOSE_ON_ERROR 1 | |
77 | #define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) | |
78 | #define DMA_INT_MEM 4 | |
79 | ||
80 | #endif /* _ASM_ARCH_CRIS_DMA_H */ |