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081860b9 GR |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. | |
3 | ||
4 | #ifndef __ASM_CSKY_ENTRY_H | |
5 | #define __ASM_CSKY_ENTRY_H | |
6 | ||
7 | #include <asm/setup.h> | |
8 | #include <abi/regdef.h> | |
9 | ||
10 | #define LSAVE_PC 8 | |
11 | #define LSAVE_PSR 12 | |
12 | #define LSAVE_A0 24 | |
13 | #define LSAVE_A1 28 | |
14 | #define LSAVE_A2 32 | |
15 | #define LSAVE_A3 36 | |
16 | ||
081860b9 GR |
17 | #define KSPTOUSP |
18 | #define USPTOKSP | |
19 | ||
20 | #define usp cr<14, 1> | |
21 | ||
081860b9 GR |
22 | .macro SAVE_ALL epc_inc |
23 | subi sp, 152 | |
24 | stw tls, (sp, 0) | |
25 | stw lr, (sp, 4) | |
26 | ||
27 | mfcr lr, epc | |
28 | movi tls, \epc_inc | |
29 | add lr, tls | |
30 | stw lr, (sp, 8) | |
31 | ||
32 | mfcr lr, epsr | |
33 | stw lr, (sp, 12) | |
f8e17c17 GR |
34 | btsti lr, 31 |
35 | bf 1f | |
36 | addi lr, sp, 152 | |
37 | br 2f | |
38 | 1: | |
081860b9 | 39 | mfcr lr, usp |
f8e17c17 | 40 | 2: |
081860b9 GR |
41 | stw lr, (sp, 16) |
42 | ||
43 | stw a0, (sp, 20) | |
44 | stw a0, (sp, 24) | |
45 | stw a1, (sp, 28) | |
46 | stw a2, (sp, 32) | |
47 | stw a3, (sp, 36) | |
48 | ||
49 | addi sp, 40 | |
50 | stm r4-r13, (sp) | |
51 | ||
52 | addi sp, 40 | |
53 | stm r16-r30, (sp) | |
54 | #ifdef CONFIG_CPU_HAS_HILO | |
55 | mfhi lr | |
56 | stw lr, (sp, 60) | |
57 | mflo lr | |
58 | stw lr, (sp, 64) | |
789154c2 GR |
59 | mfcr lr, cr14 |
60 | stw lr, (sp, 68) | |
081860b9 GR |
61 | #endif |
62 | subi sp, 80 | |
63 | .endm | |
64 | ||
65 | .macro RESTORE_ALL | |
66 | psrclr ie | |
67 | ldw tls, (sp, 0) | |
68 | ldw lr, (sp, 4) | |
69 | ldw a0, (sp, 8) | |
70 | mtcr a0, epc | |
71 | ldw a0, (sp, 12) | |
72 | mtcr a0, epsr | |
f8e17c17 | 73 | btsti a0, 31 |
081860b9 GR |
74 | ldw a0, (sp, 16) |
75 | mtcr a0, usp | |
f8e17c17 | 76 | mtcr a0, ss0 |
081860b9 GR |
77 | |
78 | #ifdef CONFIG_CPU_HAS_HILO | |
79 | ldw a0, (sp, 140) | |
80 | mthi a0 | |
81 | ldw a0, (sp, 144) | |
82 | mtlo a0 | |
789154c2 GR |
83 | ldw a0, (sp, 148) |
84 | mtcr a0, cr14 | |
081860b9 GR |
85 | #endif |
86 | ||
87 | ldw a0, (sp, 24) | |
88 | ldw a1, (sp, 28) | |
89 | ldw a2, (sp, 32) | |
90 | ldw a3, (sp, 36) | |
91 | ||
92 | addi sp, 40 | |
93 | ldm r4-r13, (sp) | |
94 | addi sp, 40 | |
95 | ldm r16-r30, (sp) | |
96 | addi sp, 72 | |
f8e17c17 GR |
97 | bf 1f |
98 | mfcr sp, ss0 | |
99 | 1: | |
081860b9 GR |
100 | rte |
101 | .endm | |
102 | ||
89a3927a GR |
103 | .macro SAVE_REGS_FTRACE |
104 | subi sp, 152 | |
105 | stw tls, (sp, 0) | |
106 | stw lr, (sp, 4) | |
107 | ||
108 | mfcr lr, psr | |
109 | stw lr, (sp, 12) | |
110 | ||
111 | addi lr, sp, 152 | |
112 | stw lr, (sp, 16) | |
113 | ||
114 | stw a0, (sp, 20) | |
115 | stw a0, (sp, 24) | |
116 | stw a1, (sp, 28) | |
117 | stw a2, (sp, 32) | |
118 | stw a3, (sp, 36) | |
119 | ||
120 | addi sp, 40 | |
121 | stm r4-r13, (sp) | |
122 | ||
123 | addi sp, 40 | |
124 | stm r16-r30, (sp) | |
125 | #ifdef CONFIG_CPU_HAS_HILO | |
126 | mfhi lr | |
127 | stw lr, (sp, 60) | |
128 | mflo lr | |
129 | stw lr, (sp, 64) | |
130 | mfcr lr, cr14 | |
131 | stw lr, (sp, 68) | |
132 | #endif | |
133 | subi sp, 80 | |
134 | .endm | |
135 | ||
136 | .macro RESTORE_REGS_FTRACE | |
137 | ldw tls, (sp, 0) | |
138 | ldw a0, (sp, 16) | |
139 | mtcr a0, ss0 | |
140 | ||
141 | #ifdef CONFIG_CPU_HAS_HILO | |
142 | ldw a0, (sp, 140) | |
143 | mthi a0 | |
144 | ldw a0, (sp, 144) | |
145 | mtlo a0 | |
146 | ldw a0, (sp, 148) | |
147 | mtcr a0, cr14 | |
148 | #endif | |
149 | ||
150 | ldw a0, (sp, 24) | |
151 | ldw a1, (sp, 28) | |
152 | ldw a2, (sp, 32) | |
153 | ldw a3, (sp, 36) | |
154 | ||
155 | addi sp, 40 | |
156 | ldm r4-r13, (sp) | |
157 | addi sp, 40 | |
158 | ldm r16-r30, (sp) | |
159 | addi sp, 72 | |
160 | mfcr sp, ss0 | |
161 | .endm | |
162 | ||
081860b9 | 163 | .macro SAVE_SWITCH_STACK |
789154c2 | 164 | subi sp, 64 |
081860b9 | 165 | stm r4-r11, (sp) |
789154c2 | 166 | stw lr, (sp, 32) |
081860b9 GR |
167 | stw r16, (sp, 36) |
168 | stw r17, (sp, 40) | |
169 | stw r26, (sp, 44) | |
170 | stw r27, (sp, 48) | |
171 | stw r28, (sp, 52) | |
172 | stw r29, (sp, 56) | |
173 | stw r30, (sp, 60) | |
789154c2 GR |
174 | #ifdef CONFIG_CPU_HAS_HILO |
175 | subi sp, 16 | |
176 | mfhi lr | |
177 | stw lr, (sp, 0) | |
178 | mflo lr | |
179 | stw lr, (sp, 4) | |
180 | mfcr lr, cr14 | |
181 | stw lr, (sp, 8) | |
182 | #endif | |
081860b9 GR |
183 | .endm |
184 | ||
185 | .macro RESTORE_SWITCH_STACK | |
789154c2 GR |
186 | #ifdef CONFIG_CPU_HAS_HILO |
187 | ldw lr, (sp, 0) | |
188 | mthi lr | |
189 | ldw lr, (sp, 4) | |
190 | mtlo lr | |
191 | ldw lr, (sp, 8) | |
192 | mtcr lr, cr14 | |
193 | addi sp, 16 | |
194 | #endif | |
081860b9 | 195 | ldm r4-r11, (sp) |
789154c2 | 196 | ldw lr, (sp, 32) |
081860b9 GR |
197 | ldw r16, (sp, 36) |
198 | ldw r17, (sp, 40) | |
199 | ldw r26, (sp, 44) | |
200 | ldw r27, (sp, 48) | |
201 | ldw r28, (sp, 52) | |
202 | ldw r29, (sp, 56) | |
203 | ldw r30, (sp, 60) | |
204 | addi sp, 64 | |
205 | .endm | |
206 | ||
207 | /* MMU registers operators. */ | |
208 | .macro RD_MIR rx | |
209 | mfcr \rx, cr<0, 15> | |
210 | .endm | |
211 | ||
212 | .macro RD_MEH rx | |
213 | mfcr \rx, cr<4, 15> | |
214 | .endm | |
215 | ||
216 | .macro RD_MCIR rx | |
217 | mfcr \rx, cr<8, 15> | |
218 | .endm | |
219 | ||
220 | .macro RD_PGDR rx | |
221 | mfcr \rx, cr<29, 15> | |
222 | .endm | |
223 | ||
224 | .macro RD_PGDR_K rx | |
225 | mfcr \rx, cr<28, 15> | |
226 | .endm | |
227 | ||
228 | .macro WR_MEH rx | |
229 | mtcr \rx, cr<4, 15> | |
230 | .endm | |
231 | ||
232 | .macro WR_MCIR rx | |
233 | mtcr \rx, cr<8, 15> | |
234 | .endm | |
235 | ||
205353fa GR |
236 | .macro SETUP_MMU |
237 | /* Init psr and enable ee */ | |
238 | lrw r6, DEFAULT_PSR_VALUE | |
239 | mtcr r6, psr | |
240 | psrset ee | |
241 | ||
242 | /* Invalid I/Dcache BTB BHT */ | |
243 | movi r6, 7 | |
244 | lsli r6, 16 | |
245 | addi r6, (1<<4) | 3 | |
246 | mtcr r6, cr17 | |
247 | ||
248 | /* Invalid all TLB */ | |
249 | bgeni r6, 26 | |
250 | mtcr r6, cr<8, 15> /* Set MCIR */ | |
251 | ||
252 | /* Check MMU on/off */ | |
253 | mfcr r6, cr18 | |
254 | btsti r6, 0 | |
f62e3162 | 255 | bt 1f |
205353fa GR |
256 | |
257 | /* MMU off: setup mapping tlb entry */ | |
258 | movi r6, 0 | |
259 | mtcr r6, cr<6, 15> /* Set MPR with 4K page size */ | |
260 | ||
261 | grs r6, 1f /* Get current pa by PC */ | |
262 | bmaski r7, (PAGE_SHIFT + 1) /* r7 = 0x1fff */ | |
263 | andn r6, r7 | |
264 | mtcr r6, cr<4, 15> /* Set MEH */ | |
265 | ||
266 | mov r8, r6 | |
267 | movi r7, 0x00000006 | |
268 | or r8, r7 | |
269 | mtcr r8, cr<2, 15> /* Set MEL0 */ | |
270 | movi r7, 0x00001006 | |
271 | or r8, r7 | |
272 | mtcr r8, cr<3, 15> /* Set MEL1 */ | |
273 | ||
274 | bgeni r8, 28 | |
275 | mtcr r8, cr<8, 15> /* Set MCIR to write TLB */ | |
276 | ||
f62e3162 GR |
277 | br 2f |
278 | 1: | |
279 | /* | |
205353fa GR |
280 | * MMU on: use origin MSA value from bootloader |
281 | * | |
282 | * cr<30/31, 15> MSA register format: | |
f62e3162 GR |
283 | * 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
284 | * BA Reserved SH WA B SO SEC C D V | |
285 | */ | |
205353fa | 286 | mfcr r6, cr<30, 15> /* Get MSA0 */ |
f62e3162 | 287 | 2: |
165f2d28 LY |
288 | lsri r6, 29 |
289 | lsli r6, 29 | |
205353fa GR |
290 | addi r6, 0x1ce |
291 | mtcr r6, cr<30, 15> /* Set MSA0 */ | |
292 | ||
aefd9461 GR |
293 | movi r6, 0 |
294 | mtcr r6, cr<31, 15> /* Clr MSA1 */ | |
205353fa GR |
295 | |
296 | /* enable MMU */ | |
297 | mfcr r6, cr18 | |
298 | bseti r6, 0 | |
299 | mtcr r6, cr18 | |
300 | ||
301 | jmpi 3f /* jump to va */ | |
302 | 3: | |
081860b9 | 303 | .endm |
2f7932b0 GR |
304 | |
305 | .macro ANDI_R3 rx, imm | |
306 | lsri \rx, 3 | |
307 | andi \rx, (\imm >> 3) | |
308 | .endm | |
081860b9 | 309 | #endif /* __ASM_CSKY_ENTRY_H */ |