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1da177e4 LT |
1 | /* irq.c: FRV IRQ handling |
2 | * | |
1bcbba30 | 3 | * Copyright (C) 2003, 2004, 2006 Red Hat, Inc. All Rights Reserved. |
1da177e4 LT |
4 | * Written by David Howells (dhowells@redhat.com) |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
1da177e4 LT |
12 | #include <linux/ptrace.h> |
13 | #include <linux/errno.h> | |
14 | #include <linux/signal.h> | |
15 | #include <linux/sched.h> | |
16 | #include <linux/ioport.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/timex.h> | |
1da177e4 | 19 | #include <linux/random.h> |
1da177e4 LT |
20 | #include <linux/init.h> |
21 | #include <linux/kernel_stat.h> | |
22 | #include <linux/irq.h> | |
23 | #include <linux/proc_fs.h> | |
24 | #include <linux/seq_file.h> | |
40234401 | 25 | #include <linux/module.h> |
1977f032 | 26 | #include <linux/bitops.h> |
1da177e4 LT |
27 | |
28 | #include <asm/atomic.h> | |
29 | #include <asm/io.h> | |
30 | #include <asm/smp.h> | |
31 | #include <asm/system.h> | |
1da177e4 LT |
32 | #include <asm/uaccess.h> |
33 | #include <asm/pgalloc.h> | |
34 | #include <asm/delay.h> | |
35 | #include <asm/irq.h> | |
36 | #include <asm/irc-regs.h> | |
1da177e4 LT |
37 | #include <asm/gdb-stub.h> |
38 | ||
1bcbba30 | 39 | #define set_IRR(N,A,B,C,D) __set_IRR(N, (A << 28) | (B << 24) | (C << 20) | (D << 16)) |
1da177e4 | 40 | |
1bcbba30 DH |
41 | extern void __init fpga_init(void); |
42 | #ifdef CONFIG_FUJITSU_MB93493 | |
43 | extern void __init mb93493_init(void); | |
44 | #endif | |
1da177e4 | 45 | |
1bcbba30 | 46 | #define __reg16(ADDR) (*(volatile unsigned short *)(ADDR)) |
1da177e4 LT |
47 | |
48 | atomic_t irq_err_count; | |
49 | ||
50 | /* | |
51 | * Generic, controller-independent functions: | |
52 | */ | |
53 | int show_interrupts(struct seq_file *p, void *v) | |
54 | { | |
1bcbba30 DH |
55 | int i = *(loff_t *) v, cpu; |
56 | struct irqaction * action; | |
1da177e4 | 57 | unsigned long flags; |
1da177e4 | 58 | |
1bcbba30 DH |
59 | if (i == 0) { |
60 | char cpuname[12]; | |
1da177e4 | 61 | |
1bcbba30 DH |
62 | seq_printf(p, " "); |
63 | for_each_present_cpu(cpu) { | |
64 | sprintf(cpuname, "CPU%d", cpu); | |
65 | seq_printf(p, " %10s", cpuname); | |
66 | } | |
1da177e4 | 67 | seq_putc(p, '\n'); |
1bcbba30 | 68 | } |
1da177e4 | 69 | |
1bcbba30 | 70 | if (i < NR_IRQS) { |
239007b8 | 71 | raw_spin_lock_irqsave(&irq_desc[i].lock, flags); |
1bcbba30 DH |
72 | action = irq_desc[i].action; |
73 | if (action) { | |
74 | seq_printf(p, "%3d: ", i); | |
75 | for_each_present_cpu(cpu) | |
dee4102a | 76 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); |
1bcbba30 DH |
77 | seq_printf(p, " %10s", irq_desc[i].chip->name ? : "-"); |
78 | seq_printf(p, " %s", action->name); | |
79 | for (action = action->next; | |
80 | action; | |
81 | action = action->next) | |
82 | seq_printf(p, ", %s", action->name); | |
83 | ||
84 | seq_putc(p, '\n'); | |
85 | } | |
1da177e4 | 86 | |
239007b8 | 87 | raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); |
1bcbba30 DH |
88 | } else if (i == NR_IRQS) { |
89 | seq_printf(p, "Err: %10u\n", atomic_read(&irq_err_count)); | |
1da177e4 LT |
90 | } |
91 | ||
92 | return 0; | |
93 | } | |
94 | ||
1da177e4 | 95 | /* |
1bcbba30 | 96 | * on-CPU PIC operations |
1da177e4 | 97 | */ |
1bcbba30 | 98 | static void frv_cpupic_ack(unsigned int irqlevel) |
1da177e4 | 99 | { |
1bcbba30 DH |
100 | __clr_RC(irqlevel); |
101 | __clr_IRL(); | |
102 | } | |
1da177e4 | 103 | |
1bcbba30 DH |
104 | static void frv_cpupic_mask(unsigned int irqlevel) |
105 | { | |
106 | __set_MASK(irqlevel); | |
107 | } | |
1da177e4 | 108 | |
1bcbba30 DH |
109 | static void frv_cpupic_mask_ack(unsigned int irqlevel) |
110 | { | |
111 | __set_MASK(irqlevel); | |
112 | __clr_RC(irqlevel); | |
113 | __clr_IRL(); | |
114 | } | |
1da177e4 | 115 | |
1bcbba30 DH |
116 | static void frv_cpupic_unmask(unsigned int irqlevel) |
117 | { | |
118 | __clr_MASK(irqlevel); | |
119 | } | |
1da177e4 | 120 | |
1bcbba30 DH |
121 | static void frv_cpupic_end(unsigned int irqlevel) |
122 | { | |
123 | __clr_MASK(irqlevel); | |
1da177e4 LT |
124 | } |
125 | ||
1bcbba30 DH |
126 | static struct irq_chip frv_cpu_pic = { |
127 | .name = "cpu", | |
1bcbba30 DH |
128 | .ack = frv_cpupic_ack, |
129 | .mask = frv_cpupic_mask, | |
130 | .mask_ack = frv_cpupic_mask_ack, | |
131 | .unmask = frv_cpupic_unmask, | |
132 | .end = frv_cpupic_end, | |
133 | }; | |
40234401 | 134 | |
1da177e4 | 135 | /* |
761a7e35 | 136 | * handles all normal device IRQs |
1da177e4 LT |
137 | * - registers are referred to by the __frame variable (GR28) |
138 | * - IRQ distribution is complicated in this arch because of the many PICs, the | |
139 | * way they work and the way they cascade | |
140 | */ | |
141 | asmlinkage void do_IRQ(void) | |
142 | { | |
28baebae | 143 | irq_enter(); |
7d12e780 | 144 | generic_handle_irq(__get_IRL()); |
28baebae | 145 | irq_exit(); |
1bcbba30 | 146 | } |
1da177e4 | 147 | |
1da177e4 LT |
148 | /* |
149 | * handles all NMIs when not co-opted by the debugger | |
150 | * - registers are referred to by the __frame variable (GR28) | |
151 | */ | |
152 | asmlinkage void do_NMI(void) | |
153 | { | |
1da177e4 LT |
154 | } |
155 | ||
1da177e4 | 156 | /* |
1bcbba30 | 157 | * initialise the interrupt system |
1da177e4 | 158 | */ |
1bcbba30 | 159 | void __init init_IRQ(void) |
1da177e4 | 160 | { |
1bcbba30 | 161 | int level; |
1da177e4 | 162 | |
1bcbba30 DH |
163 | for (level = 1; level <= 14; level++) |
164 | set_irq_chip_and_handler(level, &frv_cpu_pic, | |
165 | handle_level_irq); | |
1da177e4 | 166 | |
1bcbba30 | 167 | set_irq_handler(IRQ_CPU_TIMER0, handle_edge_irq); |
1da177e4 | 168 | |
1bcbba30 DH |
169 | /* set the trigger levels for internal interrupt sources |
170 | * - timers all falling-edge | |
171 | * - ERR0 is rising-edge | |
172 | * - all others are high-level | |
1da177e4 | 173 | */ |
1bcbba30 DH |
174 | __set_IITMR(0, 0x003f0000); /* DMA0-3, TIMER0-2 */ |
175 | __set_IITMR(1, 0x20000000); /* ERR0-1, UART0-1, DMA4-7 */ | |
176 | ||
177 | /* route internal interrupts */ | |
178 | set_IRR(4, IRQ_DMA3_LEVEL, IRQ_DMA2_LEVEL, IRQ_DMA1_LEVEL, | |
179 | IRQ_DMA0_LEVEL); | |
180 | set_IRR(5, 0, IRQ_TIMER2_LEVEL, IRQ_TIMER1_LEVEL, IRQ_TIMER0_LEVEL); | |
181 | set_IRR(6, IRQ_GDBSTUB_LEVEL, IRQ_GDBSTUB_LEVEL, | |
182 | IRQ_UART1_LEVEL, IRQ_UART0_LEVEL); | |
183 | set_IRR(7, IRQ_DMA7_LEVEL, IRQ_DMA6_LEVEL, IRQ_DMA5_LEVEL, | |
184 | IRQ_DMA4_LEVEL); | |
185 | ||
186 | /* route external interrupts */ | |
187 | set_IRR(2, IRQ_XIRQ7_LEVEL, IRQ_XIRQ6_LEVEL, IRQ_XIRQ5_LEVEL, | |
188 | IRQ_XIRQ4_LEVEL); | |
189 | set_IRR(3, IRQ_XIRQ3_LEVEL, IRQ_XIRQ2_LEVEL, IRQ_XIRQ1_LEVEL, | |
190 | IRQ_XIRQ0_LEVEL); | |
191 | ||
192 | #if defined(CONFIG_MB93091_VDK) | |
193 | __set_TM1(0x55550000); /* XIRQ7-0 all active low */ | |
194 | #elif defined(CONFIG_MB93093_PDK) | |
195 | __set_TM1(0x15550000); /* XIRQ7 active high, 6-0 all active low */ | |
196 | #else | |
197 | #error dont know external IRQ trigger levels for this setup | |
198 | #endif | |
1da177e4 | 199 | |
1da177e4 LT |
200 | fpga_init(); |
201 | #ifdef CONFIG_FUJITSU_MB93493 | |
1bcbba30 | 202 | mb93493_init(); |
1da177e4 | 203 | #endif |
1bcbba30 | 204 | } |