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1a59d1b8 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
e92e8c68 | 2 | /****************************************************************************** |
7f30491c | 3 | * arch/ia64/include/asm/native/inst.h |
e92e8c68 IY |
4 | * |
5 | * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp> | |
6 | * VA Linux Systems Japan K.K. | |
e92e8c68 IY |
7 | */ |
8 | ||
02e32e36 IY |
9 | #define DO_SAVE_MIN IA64_NATIVE_DO_SAVE_MIN |
10 | ||
e92e8c68 IY |
11 | #define MOV_FROM_IFA(reg) \ |
12 | mov reg = cr.ifa | |
13 | ||
14 | #define MOV_FROM_ITIR(reg) \ | |
15 | mov reg = cr.itir | |
16 | ||
17 | #define MOV_FROM_ISR(reg) \ | |
18 | mov reg = cr.isr | |
19 | ||
20 | #define MOV_FROM_IHA(reg) \ | |
21 | mov reg = cr.iha | |
22 | ||
23 | #define MOV_FROM_IPSR(pred, reg) \ | |
24 | (pred) mov reg = cr.ipsr | |
25 | ||
26 | #define MOV_FROM_IIM(reg) \ | |
27 | mov reg = cr.iim | |
28 | ||
29 | #define MOV_FROM_IIP(reg) \ | |
30 | mov reg = cr.iip | |
31 | ||
32 | #define MOV_FROM_IVR(reg, clob) \ | |
e55645ec | 33 | mov reg = cr.ivr |
e92e8c68 IY |
34 | |
35 | #define MOV_FROM_PSR(pred, reg, clob) \ | |
e55645ec | 36 | (pred) mov reg = psr |
e92e8c68 | 37 | |
94752a79 | 38 | #define MOV_FROM_ITC(pred, pred_clob, reg, clob) \ |
e55645ec | 39 | (pred) mov reg = ar.itc |
94752a79 | 40 | |
e92e8c68 | 41 | #define MOV_TO_IFA(reg, clob) \ |
e55645ec | 42 | mov cr.ifa = reg |
e92e8c68 IY |
43 | |
44 | #define MOV_TO_ITIR(pred, reg, clob) \ | |
e55645ec | 45 | (pred) mov cr.itir = reg |
e92e8c68 IY |
46 | |
47 | #define MOV_TO_IHA(pred, reg, clob) \ | |
e55645ec | 48 | (pred) mov cr.iha = reg |
e92e8c68 IY |
49 | |
50 | #define MOV_TO_IPSR(pred, reg, clob) \ | |
e55645ec | 51 | (pred) mov cr.ipsr = reg |
e92e8c68 IY |
52 | |
53 | #define MOV_TO_IFS(pred, reg, clob) \ | |
e55645ec | 54 | (pred) mov cr.ifs = reg |
e92e8c68 IY |
55 | |
56 | #define MOV_TO_IIP(reg, clob) \ | |
e55645ec | 57 | mov cr.iip = reg |
e92e8c68 IY |
58 | |
59 | #define MOV_TO_KR(kr, reg, clob0, clob1) \ | |
e55645ec | 60 | mov IA64_KR(kr) = reg |
e92e8c68 IY |
61 | |
62 | #define ITC_I(pred, reg, clob) \ | |
e55645ec | 63 | (pred) itc.i reg |
e92e8c68 IY |
64 | |
65 | #define ITC_D(pred, reg, clob) \ | |
e55645ec | 66 | (pred) itc.d reg |
e92e8c68 IY |
67 | |
68 | #define ITC_I_AND_D(pred_i, pred_d, reg, clob) \ | |
69 | (pred_i) itc.i reg; \ | |
e55645ec | 70 | (pred_d) itc.d reg |
e92e8c68 IY |
71 | |
72 | #define THASH(pred, reg0, reg1, clob) \ | |
e55645ec | 73 | (pred) thash reg0 = reg1 |
e92e8c68 IY |
74 | |
75 | #define SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(clob0, clob1) \ | |
76 | ssm psr.ic | PSR_DEFAULT_BITS \ | |
e92e8c68 IY |
77 | ;; \ |
78 | srlz.i /* guarantee that interruption collectin is on */ \ | |
79 | ;; | |
80 | ||
81 | #define SSM_PSR_IC_AND_SRLZ_D(clob0, clob1) \ | |
82 | ssm psr.ic \ | |
e92e8c68 IY |
83 | ;; \ |
84 | srlz.d | |
85 | ||
86 | #define RSM_PSR_IC(clob) \ | |
e55645ec | 87 | rsm psr.ic |
e92e8c68 IY |
88 | |
89 | #define SSM_PSR_I(pred, pred_clob, clob) \ | |
e55645ec | 90 | (pred) ssm psr.i |
e92e8c68 IY |
91 | |
92 | #define RSM_PSR_I(pred, clob0, clob1) \ | |
e55645ec | 93 | (pred) rsm psr.i |
e92e8c68 IY |
94 | |
95 | #define RSM_PSR_I_IC(clob0, clob1, clob2) \ | |
e55645ec | 96 | rsm psr.i | psr.ic |
e92e8c68 IY |
97 | |
98 | #define RSM_PSR_DT \ | |
99 | rsm psr.dt | |
100 | ||
c4312511 | 101 | #define RSM_PSR_BE_I(clob0, clob1) \ |
e55645ec | 102 | rsm psr.be | psr.i |
c4312511 | 103 | |
e92e8c68 IY |
104 | #define SSM_PSR_DT_AND_SRLZ_I \ |
105 | ssm psr.dt \ | |
106 | ;; \ | |
107 | srlz.i | |
108 | ||
109 | #define BSW_0(clob0, clob1, clob2) \ | |
e55645ec | 110 | bsw.0 |
e92e8c68 IY |
111 | |
112 | #define BSW_1(clob0, clob1) \ | |
e55645ec | 113 | bsw.1 |
e92e8c68 IY |
114 | |
115 | #define COVER \ | |
116 | cover | |
117 | ||
118 | #define RFI \ | |
119 | rfi |