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License cleanup: add SPDX GPL-2.0 license identifier to files with no license
[people/arne_f/kernel.git] / arch / ia64 / include / asm / pci.h
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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
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2#ifndef _ASM_IA64_PCI_H
3#define _ASM_IA64_PCI_H
4
5#include <linux/mm.h>
6#include <linux/slab.h>
7#include <linux/spinlock.h>
8#include <linux/string.h>
9#include <linux/types.h>
84be456f 10#include <linux/scatterlist.h>
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11
12#include <asm/io.h>
8621235b 13#include <asm/hw_irq.h>
1da177e4 14
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15struct pci_vector_struct {
16 __u16 segment; /* PCI Segment number */
17 __u16 bus; /* PCI Bus number */
18 __u32 pci_id; /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
19 __u8 pin; /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
20 __u32 irq; /* IRQ assigned */
21};
22
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23/*
24 * Can be used to override the logic in pci_scan_bus for skipping already-configured bus
25 * numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
26 * loader.
27 */
28#define pcibios_assign_all_busses() 0
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29
30#define PCIBIOS_MIN_IO 0x1000
31#define PCIBIOS_MIN_MEM 0x10000000
32
33void pcibios_config_init(void);
34
35struct pci_dev;
36
37/*
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38 * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct
39 * correspondence between device bus addresses and CPU physical addresses.
40 * Platforms with a hardware I/O MMU _must_ turn this off to suppress the
41 * bounce buffer handling code in the block and network device layers.
42 * Platforms with separate bus address spaces _must_ turn this off and provide
43 * a device DMA mapping implementation that takes care of the necessary
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44 * address translation.
45 *
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46 * For now, the ia64 platforms which may have separate/multiple bus address
47 * spaces all have I/O MMUs which support the merging of physically
48 * discontiguous buffers, so we can use that as the sole factor to determine
49 * the setting of PCI_DMA_BUS_IS_PHYS.
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50 */
51extern unsigned long ia64_max_iommu_merge_mask;
52#define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL)
53
1da177e4 54#define HAVE_PCI_MMAP
d9c102de 55#define ARCH_GENERIC_PCI_MMAP_RESOURCE
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56#define arch_can_pci_mmap_wc() 1
57
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58#define HAVE_PCI_LEGACY
59extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
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60 struct vm_area_struct *vma,
61 enum pci_mmap_state mmap_state);
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62
63#define pci_get_legacy_mem platform_pci_get_legacy_mem
64#define pci_legacy_read platform_pci_legacy_read
65#define pci_legacy_write platform_pci_legacy_write
66
1da177e4 67struct pci_controller {
7b199811 68 struct acpi_device *companion;
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69 void *iommu;
70 int segment;
b1e9cee7 71 int node; /* nearest node with memory or NUMA_NO_NODE for global allocation */
1da177e4 72
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73 void *platform_data;
74};
75
5cd7595d 76
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77#define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
78#define pci_domain_nr(busdev) (PCI_CONTROLLER(busdev)->segment)
79
80extern struct pci_ops pci_root_ops;
81
82static inline int pci_proc_domain(struct pci_bus *bus)
83{
84 return (pci_domain_nr(bus) != 0);
85}
86
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87#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
88static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
89{
8621235b 90 return channel ? isa_irq_to_vector(15) : isa_irq_to_vector(14);
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91}
92
d3f13810 93#ifdef CONFIG_INTEL_IOMMU
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94extern void pci_iommu_alloc(void);
95#endif
1da177e4 96#endif /* _ASM_IA64_PCI_H */