[people/ms/u-boot.git] / arch / m68k / cpu / mcf5227x / cpu_init.c

/*
 *
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>

#include <asm/immap.h>
#include <asm/io.h>
#include <asm/rtc.h>

/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f(void)
{
	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
	pll_t *pll = (pll_t *)MMAP_PLL;

#if !defined(CONFIG_CF_SBF)
	/* Workaround, must place before fbcs */
	out_be32(&pll->psr, 0x12);

	out_be32(&scm1->mpr, 0x77777777);
	out_be32(&scm1->pacra, 0);
	out_be32(&scm1->pacrb, 0);
	out_be32(&scm1->pacrc, 0);
	out_be32(&scm1->pacrd, 0);
	out_be32(&scm1->pacre, 0);
	out_be32(&scm1->pacrf, 0);
	out_be32(&scm1->pacrg, 0);
	out_be32(&scm1->pacri, 0);

#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
     && defined(CONFIG_SYS_CS0_CTRL))
	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif
#endif				/* CONFIG_CF_SBF */

#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
     && defined(CONFIG_SYS_CS1_CTRL))
	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif

#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
     && defined(CONFIG_SYS_CS2_CTRL))
	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif

#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
     && defined(CONFIG_SYS_CS3_CTRL))
	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif

#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
     && defined(CONFIG_SYS_CS4_CTRL))
	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif

#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
     && defined(CONFIG_SYS_CS5_CTRL))
	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif

#ifdef CONFIG_FSL_I2C
	out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
#endif

	icache_enable();
}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r(void)
{
#ifdef CONFIG_MCFRTC
	rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
	rtcex_t *rtcex = (rtcex_t *)&rtc->extended;

	out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
	out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
#endif

	return (0);
}

void uart_port_conf(int port)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Setup Ports: */
	switch (port) {
	case 0:
		clrbits_be16(&gpio->par_uart,
			~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
		break;
	case 1:
		clrbits_be16(&gpio->par_uart,
			~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
		break;
	case 2:
		clrbits_8(&gpio->par_dspi,
			~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
		out_8(&gpio->par_dspi,
			GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
		break;
	}
}

#ifdef CONFIG_CF_DSPI
void cfspi_port_conf(void)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	out_8(&gpio->par_dspi,
		GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
		GPIO_PAR_DSPI_SCK_SCK);
}

int cfspi_claim_bus(uint bus, uint cs)
{
	dspi_t *dspi = (dspi_t *) MMAP_DSPI;
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
		return -1;

	/* Clear FIFO and resume transfer */
	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);

	switch (cs) {
	case 0:
		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
		break;
	case 2:
		clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
		setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
		break;
	}

	return 0;
}

void cfspi_release_bus(uint bus, uint cs)
{
	dspi_t *dspi = (dspi_t *) MMAP_DSPI;
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Clear FIFO */
	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);

	switch (cs) {
	case 0:
		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
		break;
	case 2:
		clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
		break;
	}
}
#endif
Commit	Line	Data
c8758102 TL	1	/*
	2	*
	3	* (C) Copyright 2000-2003
	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	5	*
849fc424	6	* (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
c8758102 TL	7	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <common.h>
	29	#include <watchdog.h>
	30
	31	#include <asm/immap.h>
849fc424	32	#include <asm/io.h>
c8758102 TL	33	#include <asm/rtc.h>
	34
	35	/*
	36	* Breath some life into the CPU...
	37	*
	38	* Set up the memory map,
	39	* initialize a bunch of registers,
	40	* initialize the UPM's
	41	*/
	42	void cpu_init_f(void)
	43	{
849fc424 AW	44	scm1_t scm1 = (scm1_t ) MMAP_SCM1;
	45	gpio_t gpio = (gpio_t ) MMAP_GPIO;
	46	fbcs_t fbcs = (fbcs_t ) MMAP_FBCS;
	47	pll_t pll = (pll_t )MMAP_PLL;
c8758102	48
a21d0c2c	49	#if !defined(CONFIG_CF_SBF)
c8758102	50	/* Workaround, must place before fbcs */
849fc424 AW	51	out_be32(&pll->psr, 0x12);
	52
	53	out_be32(&scm1->mpr, 0x77777777);
	54	out_be32(&scm1->pacra, 0);
	55	out_be32(&scm1->pacrb, 0);
	56	out_be32(&scm1->pacrc, 0);
	57	out_be32(&scm1->pacrd, 0);
	58	out_be32(&scm1->pacre, 0);
	59	out_be32(&scm1->pacrf, 0);
	60	out_be32(&scm1->pacrg, 0);
	61	out_be32(&scm1->pacri, 0);
c8758102	62
a21d0c2c TL	63	#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
a21d0c2c TL	64	&& defined(CONFIG_SYS_CS0_CTRL))
849fc424 AW	65	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
	66	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
	67	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
c8758102	68	#endif
a21d0c2c	69	#endif /* CONFIG_CF_SBF */
c8758102	70
a21d0c2c TL	71	#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
a21d0c2c TL	72	&& defined(CONFIG_SYS_CS1_CTRL))
849fc424 AW	73	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
	74	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
	75	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
c8758102 TL	76	#endif
c8758102 TL	77
a21d0c2c TL	78	#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
a21d0c2c TL	79	&& defined(CONFIG_SYS_CS2_CTRL))
849fc424 AW	80	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
	81	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
	82	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
c8758102 TL	83	#endif
c8758102 TL	84
a21d0c2c TL	85	#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
a21d0c2c TL	86	&& defined(CONFIG_SYS_CS3_CTRL))
849fc424 AW	87	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
	88	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
	89	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
c8758102 TL	90	#endif
c8758102 TL	91
a21d0c2c TL	92	#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
a21d0c2c TL	93	&& defined(CONFIG_SYS_CS4_CTRL))
849fc424 AW	94	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
	95	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
	96	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
c8758102 TL	97	#endif
c8758102 TL	98
a21d0c2c TL	99	#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
a21d0c2c TL	100	&& defined(CONFIG_SYS_CS5_CTRL))
849fc424 AW	101	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
	102	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
	103	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
c8758102 TL	104	#endif
	105
	106	#ifdef CONFIG_FSL_I2C
849fc424	107	out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL \| GPIO_PAR_I2C_SDA_SDA);
c8758102 TL	108	#endif
	109
	110	icache_enable();
	111	}
	112
	113	/*
	114	* initialize higher level parts of CPU like timers
	115	*/
	116	int cpu_init_r(void)
	117	{
bc3ccb13	118	#ifdef CONFIG_MCFRTC
849fc424 AW	119	rtc_t rtc = (rtc_t )(CONFIG_SYS_MCFRTC_BASE);
849fc424 AW	120	rtcex_t rtcex = (rtcex_t )&rtc->extended;
c8758102	121
849fc424 AW	122	out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
849fc424 AW	123	out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
c8758102 TL	124	#endif
	125
	126	return (0);
	127	}
	128
52affe04	129	void uart_port_conf(int port)
c8758102	130	{
849fc424	131	gpio_t gpio = (gpio_t ) MMAP_GPIO;
c8758102 TL	132
c8758102 TL	133	/* Setup Ports: */
52affe04	134	switch (port) {
c8758102	135	case 0:
849fc424 AW	136	clrbits_be16(&gpio->par_uart,
	137	~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
	138	setbits_be16(&gpio->par_uart,
	139	GPIO_PAR_UART_U0TXD_U0TXD \| GPIO_PAR_UART_U0RXD_U0RXD);
c8758102 TL	140	break;
c8758102 TL	141	case 1:
849fc424 AW	142	clrbits_be16(&gpio->par_uart,
	143	~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
	144	setbits_be16(&gpio->par_uart,
	145	GPIO_PAR_UART_U1TXD_U1TXD \| GPIO_PAR_UART_U1RXD_U1RXD);
c8758102 TL	146	break;
c8758102 TL	147	case 2:
849fc424 AW	148	clrbits_8(&gpio->par_dspi,
	149	~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
	150	out_8(&gpio->par_dspi,
	151	GPIO_PAR_DSPI_SIN_U2RXD \| GPIO_PAR_DSPI_SOUT_U2TXD);
c8758102 TL	152	break;
	153	}
	154	}
ee0a8462 TL	155
	156	#ifdef CONFIG_CF_DSPI
	157	void cfspi_port_conf(void)
	158	{
849fc424	159	gpio_t gpio = (gpio_t ) MMAP_GPIO;
ee0a8462	160
849fc424 AW	161	out_8(&gpio->par_dspi,
	162	GPIO_PAR_DSPI_SIN_SIN \| GPIO_PAR_DSPI_SOUT_SOUT \|
	163	GPIO_PAR_DSPI_SCK_SCK);
ee0a8462 TL	164	}
	165
	166	int cfspi_claim_bus(uint bus, uint cs)
	167	{
849fc424 AW	168	dspi_t dspi = (dspi_t ) MMAP_DSPI;
849fc424 AW	169	gpio_t gpio = (gpio_t ) MMAP_GPIO;
ee0a8462	170
849fc424	171	if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
ee0a8462 TL	172	return -1;
	173
	174	/* Clear FIFO and resume transfer */
849fc424	175	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF \| DSPI_MCR_CRXF);
ee0a8462 TL	176
	177	switch (cs) {
	178	case 0:
849fc424 AW	179	clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
849fc424 AW	180	setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
ee0a8462 TL	181	break;
ee0a8462 TL	182	case 2:
849fc424 AW	183	clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
849fc424 AW	184	setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
ee0a8462 TL	185	break;
	186	}
	187
	188	return 0;
	189	}
	190
	191	void cfspi_release_bus(uint bus, uint cs)
	192	{
849fc424 AW	193	dspi_t dspi = (dspi_t ) MMAP_DSPI;
849fc424 AW	194	gpio_t gpio = (gpio_t ) MMAP_GPIO;
ee0a8462	195
849fc424 AW	196	/* Clear FIFO */
849fc424 AW	197	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF \| DSPI_MCR_CRXF);
ee0a8462 TL	198
	199	switch (cs) {
	200	case 0:
849fc424	201	clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
ee0a8462 TL	202	break;
ee0a8462 TL	203	case 2:
849fc424	204	clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
ee0a8462 TL	205	break;
	206	}
	207	}
	208	#endif