[thirdparty/u-boot.git] / arch / m68k / cpu / mcf532x / cpu_init.c

/*
 *
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004-2008, 2012 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>
#include <asm/io.h>

#if defined(CONFIG_CMD_NET)
#include <config.h>
#include <net.h>
#include <asm/fec.h>
#endif

#ifdef CONFIG_MCF5301x
void cpu_init_f(void)
{
	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;

	out_be32(&scm1->mpr, 0x77777777);
	out_be32(&scm1->pacra, 0);
	out_be32(&scm1->pacrb, 0);
	out_be32(&scm1->pacrc, 0);
	out_be32(&scm1->pacrd, 0);
	out_be32(&scm1->pacre, 0);
	out_be32(&scm1->pacrf, 0);
	out_be32(&scm1->pacrg, 0);

#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
     && defined(CONFIG_SYS_CS0_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0);
	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif

#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
     && defined(CONFIG_SYS_CS1_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1);
	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif

#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
     && defined(CONFIG_SYS_CS2_CTRL))
	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif

#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
     && defined(CONFIG_SYS_CS3_CTRL))
	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif

#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
     && defined(CONFIG_SYS_CS4_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif

#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
     && defined(CONFIG_SYS_CS5_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif

#ifdef CONFIG_FSL_I2C
	out_8(&gpio->par_feci2c,
		GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL);
#endif

	icache_enable();
}

/* initialize higher level parts of CPU like timers */
int cpu_init_r(void)
{
#ifdef CONFIG_MCFFEC
	ccm_t *ccm = (ccm_t *) MMAP_CCM;
#endif
#ifdef CONFIG_MCFRTC
	rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
	rtcex_t *rtcex = (rtcex_t *) &rtc->extended;

	out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT);
	out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP);

#endif
#ifdef CONFIG_MCFFEC
	if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
		setbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
	else
		clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
#endif

	return (0);
}

void uart_port_conf(int port)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Setup Ports: */
	switch (port) {
	case 0:
		clrbits_8(&gpio->par_uart,
			GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
		setbits_8(&gpio->par_uart,
			GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
		break;
	case 1:
#ifdef CONFIG_SYS_UART1_ALT1_GPIO
		clrbits_8(&gpio->par_simp1h,
			GPIO_PAR_SIMP1H_DATA1_UNMASK |
			GPIO_PAR_SIMP1H_VEN1_UNMASK);
		setbits_8(&gpio->par_simp1h,
			GPIO_PAR_SIMP1H_DATA1_U1TXD |
			GPIO_PAR_SIMP1H_VEN1_U1RXD);
#elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
		clrbits_8(&gpio->par_ssih,
			GPIO_PAR_SSIH_RXD_UNMASK |
			GPIO_PAR_SSIH_TXD_UNMASK);
		setbits_8(&gpio->par_ssih,
			GPIO_PAR_SSIH_RXD_U1RXD |
			GPIO_PAR_SSIH_TXD_U1TXD);
#endif
		break;
	case 2:
#ifdef CONFIG_SYS_UART2_PRI_GPIO
		setbits_8(&gpio->par_uart,
			GPIO_PAR_UART_U2TXD |
			GPIO_PAR_UART_U2RXD);
#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
		clrbits_8(&gpio->par_dspih,
			GPIO_PAR_DSPIH_SIN_UNMASK |
			GPIO_PAR_DSPIH_SOUT_UNMASK);
		setbits_8(&gpio->par_dspih,
			GPIO_PAR_DSPIH_SIN_U2RXD |
			GPIO_PAR_DSPIH_SOUT_U2TXD);
#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
		clrbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_SDA_UNMASK |
			GPIO_PAR_FECI2C_SCL_UNMASK);
		setbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_SDA_U2TXD |
			GPIO_PAR_FECI2C_SCL_U2RXD);
#endif
		break;
	}
}

#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
	struct fec_info_s *info = (struct fec_info_s *)dev->priv;

	if (setclear) {
		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
			setbits_8(&gpio->par_fec,
				GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
			setbits_8(&gpio->par_feci2c,
				GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0);
		} else {
			setbits_8(&gpio->par_fec,
				GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
			setbits_8(&gpio->par_feci2c,
				GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1);
		}
	} else {
		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
			clrbits_8(&gpio->par_fec,
				GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
			clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK);
		} else {
			clrbits_8(&gpio->par_fec,
				GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
			clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII1_UNMASK);
		}
	}
	return 0;
}
#endif				/* CONFIG_CMD_NET */
#endif				/* CONFIG_MCF5301x */

#ifdef CONFIG_MCF532x
void cpu_init_f(void)
{
	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
	scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
	wdog_t *wdog = (wdog_t *) MMAP_WDOG;

	/* watchdog is enabled by default - disable the watchdog */
#ifndef CONFIG_WATCHDOG
	out_be16(&wdog->cr, 0);
#endif

	out_be32(&scm1->mpr0, 0x77777777);
	out_be32(&scm2->pacra, 0);
	out_be32(&scm2->pacrb, 0);
	out_be32(&scm2->pacrc, 0);
	out_be32(&scm2->pacrd, 0);
	out_be32(&scm2->pacre, 0);
	out_be32(&scm2->pacrf, 0);
	out_be32(&scm2->pacrg, 0);
	out_be32(&scm1->pacrh, 0);

	/* Port configuration */
	out_8(&gpio->par_cs, 0);

#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
     && defined(CONFIG_SYS_CS0_CTRL))
	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif

#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
     && defined(CONFIG_SYS_CS1_CTRL))
	/* Latch chipselect */
	setbits_8(&gpio->par_cs, GPIO_PAR_CS1);
	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif

#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
     && defined(CONFIG_SYS_CS2_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS2);
	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif

#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
     && defined(CONFIG_SYS_CS3_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS3);
	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif

#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
     && defined(CONFIG_SYS_CS4_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif

#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
     && defined(CONFIG_SYS_CS5_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif

#ifdef CONFIG_FSL_I2C
	out_8(&gpio->par_feci2c,
		GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
#endif

	icache_enable();
}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r(void)
{
	return (0);
}

void uart_port_conf(int port)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Setup Ports: */
	switch (port) {
	case 0:
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
		break;
	case 1:
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
		break;
	case 2:
#ifdef CONFIG_SYS_UART2_ALT1_GPIO
		clrbits_8(&gpio->par_timer, 0xf0);
		setbits_8(&gpio->par_timer,
			GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
		clrbits_8(&gpio->par_feci2c, 0x00ff);
		setbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
#elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
		clrbits_be16(&gpio->par_ssi, 0x0f00);
		setbits_be16(&gpio->par_ssi,
			GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
#endif
		break;
	}
}

#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	if (setclear) {
		setbits_8(&gpio->par_fec,
			GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
		setbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
	} else {
		clrbits_8(&gpio->par_fec,
			GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
		clrbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
	}
	return 0;
}
#endif
#endif				/* CONFIG_MCF532x */
Commit	Line	Data
8e585f02 TL	1	/*
	2	*
	3	* (C) Copyright 2000-2003
	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	5	*
aa0d99fc	6	* (C) Copyright 2004-2008, 2012 Freescale Semiconductor, Inc.
8e585f02 TL	7	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8e585f02 TL	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
8e585f02 TL	10	*/
	11
	12	#include <common.h>
	13	#include <watchdog.h>
84a015b5	14	#include <asm/immap.h>
aa0d99fc	15	#include <asm/io.h>
8e585f02	16
f3962d3f TL	17	#if defined(CONFIG_CMD_NET)
	18	#include <config.h>
	19	#include <net.h>
	20	#include <asm/fec.h>
	21	#endif
	22
536e7dac TL	23	#ifdef CONFIG_MCF5301x
	24	void cpu_init_f(void)
	25	{
aa0d99fc AW	26	scm1_t scm1 = (scm1_t ) MMAP_SCM1;
	27	gpio_t gpio = (gpio_t ) MMAP_GPIO;
	28	fbcs_t fbcs = (fbcs_t ) MMAP_FBCS;
	29
	30	out_be32(&scm1->mpr, 0x77777777);
	31	out_be32(&scm1->pacra, 0);
	32	out_be32(&scm1->pacrb, 0);
	33	out_be32(&scm1->pacrc, 0);
	34	out_be32(&scm1->pacrd, 0);
	35	out_be32(&scm1->pacre, 0);
	36	out_be32(&scm1->pacrf, 0);
	37	out_be32(&scm1->pacrg, 0);
536e7dac TL	38
	39	#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
	40	&& defined(CONFIG_SYS_CS0_CTRL))
aa0d99fc AW	41	setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0);
	42	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
	43	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
	44	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
536e7dac TL	45	#endif
	46
	47	#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
	48	&& defined(CONFIG_SYS_CS1_CTRL))
aa0d99fc AW	49	setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1);
	50	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
	51	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
	52	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
536e7dac TL	53	#endif
	54
	55	#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
	56	&& defined(CONFIG_SYS_CS2_CTRL))
aa0d99fc AW	57	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
	58	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
	59	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
536e7dac TL	60	#endif
	61
	62	#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
	63	&& defined(CONFIG_SYS_CS3_CTRL))
aa0d99fc AW	64	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
	65	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
	66	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
536e7dac TL	67	#endif
	68
	69	#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
	70	&& defined(CONFIG_SYS_CS4_CTRL))
aa0d99fc AW	71	setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
	72	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
	73	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
	74	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
536e7dac TL	75	#endif
	76
	77	#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
	78	&& defined(CONFIG_SYS_CS5_CTRL))
aa0d99fc AW	79	setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
	80	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
	81	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
	82	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
536e7dac TL	83	#endif
	84
	85	#ifdef CONFIG_FSL_I2C
aa0d99fc AW	86	out_8(&gpio->par_feci2c,
aa0d99fc AW	87	GPIO_PAR_FECI2C_SDA_SDA \| GPIO_PAR_FECI2C_SCL_SCL);
536e7dac TL	88	#endif
	89
	90	icache_enable();
	91	}
	92
	93	/* initialize higher level parts of CPU like timers */
	94	int cpu_init_r(void)
	95	{
	96	#ifdef CONFIG_MCFFEC
aa0d99fc	97	ccm_t ccm = (ccm_t ) MMAP_CCM;
536e7dac TL	98	#endif
536e7dac TL	99	#ifdef CONFIG_MCFRTC
aa0d99fc AW	100	rtc_t rtc = (rtc_t ) (CONFIG_SYS_MCFRTC_BASE);
aa0d99fc AW	101	rtcex_t rtcex = (rtcex_t ) &rtc->extended;
536e7dac	102
aa0d99fc AW	103	out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT);
aa0d99fc AW	104	out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP);
536e7dac TL	105
	106	#endif
	107	#ifdef CONFIG_MCFFEC
	108	if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
aa0d99fc	109	setbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
536e7dac	110	else
aa0d99fc	111	clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
536e7dac TL	112	#endif
	113
	114	return (0);
	115	}
	116
52affe04	117	void uart_port_conf(int port)
536e7dac	118	{
aa0d99fc	119	gpio_t gpio = (gpio_t ) MMAP_GPIO;
536e7dac TL	120
536e7dac TL	121	/* Setup Ports: */
52affe04	122	switch (port) {
536e7dac	123	case 0:
aa0d99fc AW	124	clrbits_8(&gpio->par_uart,
	125	GPIO_PAR_UART_U0TXD \| GPIO_PAR_UART_U0RXD);
	126	setbits_8(&gpio->par_uart,
	127	GPIO_PAR_UART_U0TXD \| GPIO_PAR_UART_U0RXD);
536e7dac TL	128	break;
	129	case 1:
	130	#ifdef CONFIG_SYS_UART1_ALT1_GPIO
aa0d99fc AW	131	clrbits_8(&gpio->par_simp1h,
	132	GPIO_PAR_SIMP1H_DATA1_UNMASK \|
	133	GPIO_PAR_SIMP1H_VEN1_UNMASK);
	134	setbits_8(&gpio->par_simp1h,
	135	GPIO_PAR_SIMP1H_DATA1_U1TXD \|
	136	GPIO_PAR_SIMP1H_VEN1_U1RXD);
536e7dac	137	#elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
aa0d99fc AW	138	clrbits_8(&gpio->par_ssih,
	139	GPIO_PAR_SSIH_RXD_UNMASK \|
	140	GPIO_PAR_SSIH_TXD_UNMASK);
	141	setbits_8(&gpio->par_ssih,
	142	GPIO_PAR_SSIH_RXD_U1RXD \|
	143	GPIO_PAR_SSIH_TXD_U1TXD);
536e7dac TL	144	#endif
	145	break;
	146	case 2:
	147	#ifdef CONFIG_SYS_UART2_PRI_GPIO
aa0d99fc AW	148	setbits_8(&gpio->par_uart,
	149	GPIO_PAR_UART_U2TXD \|
	150	GPIO_PAR_UART_U2RXD);
536e7dac	151	#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
aa0d99fc AW	152	clrbits_8(&gpio->par_dspih,
	153	GPIO_PAR_DSPIH_SIN_UNMASK \|
	154	GPIO_PAR_DSPIH_SOUT_UNMASK);
	155	setbits_8(&gpio->par_dspih,
	156	GPIO_PAR_DSPIH_SIN_U2RXD \|
	157	GPIO_PAR_DSPIH_SOUT_U2TXD);
536e7dac	158	#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
aa0d99fc AW	159	clrbits_8(&gpio->par_feci2c,
	160	GPIO_PAR_FECI2C_SDA_UNMASK \|
	161	GPIO_PAR_FECI2C_SCL_UNMASK);
	162	setbits_8(&gpio->par_feci2c,
	163	GPIO_PAR_FECI2C_SDA_U2TXD \|
	164	GPIO_PAR_FECI2C_SCL_U2RXD);
536e7dac TL	165	#endif
	166	break;
	167	}
	168	}
	169
	170	#if defined(CONFIG_CMD_NET)
	171	int fecpin_setclear(struct eth_device *dev, int setclear)
	172	{
aa0d99fc	173	gpio_t gpio = (gpio_t ) MMAP_GPIO;
536e7dac TL	174	struct fec_info_s info = (struct fec_info_s )dev->priv;
	175
	176	if (setclear) {
	177	if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
aa0d99fc AW	178	setbits_8(&gpio->par_fec,
	179	GPIO_PAR_FEC0_7W_FEC \| GPIO_PAR_FEC0_RMII_FEC);
	180	setbits_8(&gpio->par_feci2c,
	181	GPIO_PAR_FECI2C_MDC0 \| GPIO_PAR_FECI2C_MDIO0);
536e7dac	182	} else {
aa0d99fc AW	183	setbits_8(&gpio->par_fec,
	184	GPIO_PAR_FEC1_7W_FEC \| GPIO_PAR_FEC1_RMII_FEC);
	185	setbits_8(&gpio->par_feci2c,
	186	GPIO_PAR_FECI2C_MDC1 \| GPIO_PAR_FECI2C_MDIO1);
536e7dac TL	187	}
	188	} else {
	189	if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
aa0d99fc AW	190	clrbits_8(&gpio->par_fec,
	191	GPIO_PAR_FEC0_7W_FEC \| GPIO_PAR_FEC0_RMII_FEC);
	192	clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK);
536e7dac	193	} else {
aa0d99fc AW	194	clrbits_8(&gpio->par_fec,
	195	GPIO_PAR_FEC1_7W_FEC \| GPIO_PAR_FEC1_RMII_FEC);
	196	clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII1_UNMASK);
536e7dac TL	197	}
	198	}
	199	return 0;
	200	}
	201	#endif /* CONFIG_CMD_NET */
	202	#endif /* CONFIG_MCF5301x */
	203
	204	#ifdef CONFIG_MCF532x
8e585f02 TL	205	void cpu_init_f(void)
8e585f02 TL	206	{
aa0d99fc AW	207	scm1_t scm1 = (scm1_t ) MMAP_SCM1;
	208	scm2_t scm2 = (scm2_t ) MMAP_SCM2;
	209	gpio_t gpio = (gpio_t ) MMAP_GPIO;
	210	fbcs_t fbcs = (fbcs_t ) MMAP_FBCS;
	211	wdog_t wdog = (wdog_t ) MMAP_WDOG;
8e585f02 TL	212
	213	/* watchdog is enabled by default - disable the watchdog */
	214	#ifndef CONFIG_WATCHDOG
aa0d99fc	215	out_be16(&wdog->cr, 0);
8e585f02 TL	216	#endif
8e585f02 TL	217
aa0d99fc AW	218	out_be32(&scm1->mpr0, 0x77777777);
	219	out_be32(&scm2->pacra, 0);
	220	out_be32(&scm2->pacrb, 0);
	221	out_be32(&scm2->pacrc, 0);
	222	out_be32(&scm2->pacrd, 0);
	223	out_be32(&scm2->pacre, 0);
	224	out_be32(&scm2->pacrf, 0);
	225	out_be32(&scm2->pacrg, 0);
	226	out_be32(&scm1->pacrh, 0);
8e585f02	227
8e585f02	228	/* Port configuration */
aa0d99fc	229	out_8(&gpio->par_cs, 0);
8e585f02	230
536e7dac TL	231	#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
536e7dac TL	232	&& defined(CONFIG_SYS_CS0_CTRL))
aa0d99fc AW	233	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
	234	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
	235	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
8e585f02 TL	236	#endif
8e585f02 TL	237
536e7dac TL	238	#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
536e7dac TL	239	&& defined(CONFIG_SYS_CS1_CTRL))
8e585f02	240	/* Latch chipselect */
aa0d99fc AW	241	setbits_8(&gpio->par_cs, GPIO_PAR_CS1);
	242	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
	243	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
	244	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
8e585f02 TL	245	#endif
8e585f02 TL	246
536e7dac TL	247	#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
536e7dac TL	248	&& defined(CONFIG_SYS_CS2_CTRL))
aa0d99fc AW	249	setbits_8(&gpio->par_cs, GPIO_PAR_CS2);
	250	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
	251	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
	252	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
8e585f02 TL	253	#endif
8e585f02 TL	254
536e7dac TL	255	#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
536e7dac TL	256	&& defined(CONFIG_SYS_CS3_CTRL))
aa0d99fc AW	257	setbits_8(&gpio->par_cs, GPIO_PAR_CS3);
	258	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
	259	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
	260	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
8e585f02 TL	261	#endif
8e585f02 TL	262
536e7dac TL	263	#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
536e7dac TL	264	&& defined(CONFIG_SYS_CS4_CTRL))
aa0d99fc AW	265	setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
	266	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
	267	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
	268	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
8e585f02 TL	269	#endif
8e585f02 TL	270
536e7dac TL	271	#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
536e7dac TL	272	&& defined(CONFIG_SYS_CS5_CTRL))
aa0d99fc AW	273	setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
	274	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
	275	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
	276	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
8e585f02	277	#endif
0dca874d	278
a41de1f0	279	#ifdef CONFIG_FSL_I2C
aa0d99fc AW	280	out_8(&gpio->par_feci2c,
aa0d99fc AW	281	GPIO_PAR_FECI2C_SCL_SCL \| GPIO_PAR_FECI2C_SDA_SDA);
a41de1f0 TL	282	#endif
a41de1f0 TL	283
0dca874d	284	icache_enable();
8e585f02 TL	285	}
	286
	287	/*
	288	* initialize higher level parts of CPU like timers
	289	*/
	290	int cpu_init_r(void)
	291	{
8e585f02 TL	292	return (0);
8e585f02 TL	293	}
8d1d66af	294
52affe04	295	void uart_port_conf(int port)
8d1d66af	296	{
aa0d99fc	297	gpio_t gpio = (gpio_t ) MMAP_GPIO;
8d1d66af TL	298
8d1d66af TL	299	/* Setup Ports: */
52affe04	300	switch (port) {
8d1d66af	301	case 0:
aa0d99fc AW	302	clrbits_be16(&gpio->par_uart,
	303	GPIO_PAR_UART_TXD0 \| GPIO_PAR_UART_RXD0);
	304	setbits_be16(&gpio->par_uart,
	305	GPIO_PAR_UART_TXD0 \| GPIO_PAR_UART_RXD0);
8d1d66af TL	306	break;
8d1d66af TL	307	case 1:
aa0d99fc AW	308	clrbits_be16(&gpio->par_uart,
	309	GPIO_PAR_UART_TXD1(3) \| GPIO_PAR_UART_RXD1(3));
	310	setbits_be16(&gpio->par_uart,
	311	GPIO_PAR_UART_TXD1(3) \| GPIO_PAR_UART_RXD1(3));
8d1d66af TL	312	break;
8d1d66af TL	313	case 2:
52affe04	314	#ifdef CONFIG_SYS_UART2_ALT1_GPIO
aa0d99fc AW	315	clrbits_8(&gpio->par_timer, 0xf0);
	316	setbits_8(&gpio->par_timer,
	317	GPIO_PAR_TIN3_URXD2 \| GPIO_PAR_TIN2_UTXD2);
52affe04	318	#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
aa0d99fc AW	319	clrbits_8(&gpio->par_feci2c, 0x00ff);
	320	setbits_8(&gpio->par_feci2c,
	321	GPIO_PAR_FECI2C_SCL_UTXD2 \| GPIO_PAR_FECI2C_SDA_URXD2);
52affe04	322	#elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
aa0d99fc AW	323	clrbits_be16(&gpio->par_ssi, 0x0f00);
	324	setbits_be16(&gpio->par_ssi,
	325	GPIO_PAR_SSI_RXD(2) \| GPIO_PAR_SSI_TXD(2));
52affe04	326	#endif
8d1d66af TL	327	break;
	328	}
	329	}
f3962d3f TL	330
	331	#if defined(CONFIG_CMD_NET)
	332	int fecpin_setclear(struct eth_device *dev, int setclear)
	333	{
aa0d99fc	334	gpio_t gpio = (gpio_t ) MMAP_GPIO;
f3962d3f TL	335
f3962d3f TL	336	if (setclear) {
aa0d99fc AW	337	setbits_8(&gpio->par_fec,
	338	GPIO_PAR_FEC_7W_FEC \| GPIO_PAR_FEC_MII_FEC);
	339	setbits_8(&gpio->par_feci2c,
	340	GPIO_PAR_FECI2C_MDC_EMDC \| GPIO_PAR_FECI2C_MDIO_EMDIO);
f3962d3f	341	} else {
aa0d99fc AW	342	clrbits_8(&gpio->par_fec,
	343	GPIO_PAR_FEC_7W_FEC \| GPIO_PAR_FEC_MII_FEC);
	344	clrbits_8(&gpio->par_feci2c,
	345	GPIO_PAR_FECI2C_MDC_EMDC \| GPIO_PAR_FECI2C_MDIO_EMDIO);
f3962d3f TL	346	}
	347	return 0;
	348	}
	349	#endif
536e7dac	350	#endif /* CONFIG_MCF532x */