[people/ms/u-boot.git] / arch / m68k / cpu / mcf532x / speed.c

/*
 *
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>

#include <asm/immap.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

/* PLL min/max specifications */
#define MAX_FVCO	500000	/* KHz */
#define MAX_FSYS	80000	/* KHz */
#define MIN_FSYS	58333	/* KHz */

#ifdef CONFIG_MCF5301x
#define FREF		20000	/* KHz */
#define MAX_MFD		63	/* Multiplier */
#define MIN_MFD		0	/* Multiplier */
#define USBDIV		8

/* Low Power Divider specifications */
#define MIN_LPD		(0)	/* Divider (not encoded) */
#define MAX_LPD		(15)	/* Divider (not encoded) */
#define DEFAULT_LPD	(0)	/* Divider (not encoded) */
#endif

#ifdef CONFIG_MCF532x
#define FREF		16000	/* KHz */
#define MAX_MFD		135	/* Multiplier */
#define MIN_MFD		88	/* Multiplier */

/* Low Power Divider specifications */
#define MIN_LPD		(1 << 0)	/* Divider (not encoded) */
#define MAX_LPD		(1 << 15)	/* Divider (not encoded) */
#define DEFAULT_LPD	(1 << 1)	/* Divider (not encoded) */
#endif

#define BUSDIV		6	/* Divider */

/* Get the value of the current system clock */
int get_sys_clock(void)
{
	ccm_t *ccm = (ccm_t *)(MMAP_CCM);
	pll_t *pll = (pll_t *)(MMAP_PLL);
	int divider;

	/* Test to see if device is in LIMP mode */
	if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) {
		divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF);
#ifdef CONFIG_MCF5301x
		return (FREF / (3 * (1 << divider)));
#endif
#ifdef CONFIG_MCF532x
		return (FREF / (2 << divider));
#endif
	} else {
#ifdef CONFIG_MCF5301x
		u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1;
		u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8));
		u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1;

		return (((FREF * pfdr) / refdiv) / busdiv);
#endif
#ifdef CONFIG_MCF532x
		return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4);
#endif
	}
}

/*
 * Initialize the Low Power Divider circuit
 *
 * Parameters:
 *  div     Desired system frequency divider
 *
 * Return Value:
 *  The resulting output system frequency
 */
int clock_limp(int div)
{
	ccm_t *ccm = (ccm_t *)(MMAP_CCM);
	u32 temp;

	/* Check bounds of divider */
	if (div < MIN_LPD)
		div = MIN_LPD;
	if (div > MAX_LPD)
		div = MAX_LPD;

	/* Save of the current value of the SSIDIV so we don't overwrite the value */
	temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF));

	/* Apply the divider to the system clock */
	out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));

	setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);

	return (FREF / (3 * (1 << div)));
}

/* Exit low power LIMP mode */
int clock_exit_limp(void)
{
	ccm_t *ccm = (ccm_t *)(MMAP_CCM);
	int fout;

	/* Exit LIMP mode */
	clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);

	/* Wait for PLL to lock */
	while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK))
		;

	fout = get_sys_clock();

	return fout;
}

/* Initialize the PLL
 *
 * Parameters:
 *  fref    PLL reference clock frequency in KHz
 *  fsys    Desired PLL output frequency in KHz
 *  flags   Operating parameters
 *
 * Return Value:
 *  The resulting output system frequency
 */
int clock_pll(int fsys, int flags)
{
#ifdef CONFIG_MCF532x
	u32 *sdram_workaround = (u32 *)(MMAP_SDRAM + 0x80);
#endif
	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
	pll_t *pll = (pll_t *)(MMAP_PLL);
	int fref, temp, fout, mfd;
	u32 i;

	fref = FREF;

	if (fsys == 0) {
		/* Return current PLL output */
#ifdef CONFIG_MCF5301x
		u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1;
		mfd = (in_be32(&pll->pcr) & 0x3F) + 1;

		return (fref * mfd) / busdiv;
#endif
#ifdef CONFIG_MCF532x
		mfd = in_8(&pll->pfdr);

		return (fref * mfd / (BUSDIV * 4));
#endif
	}

	/* Check bounds of requested system clock */
	if (fsys > MAX_FSYS)
		fsys = MAX_FSYS;

	if (fsys < MIN_FSYS)
		fsys = MIN_FSYS;

	/*
	 * Multiplying by 100 when calculating the temp value,
	 * and then dividing by 100 to calculate the mfd allows
	 * for exact values without needing to include floating
	 * point libraries.
	 */
	temp = (100 * fsys) / fref;
#ifdef CONFIG_MCF5301x
	mfd = (BUSDIV * temp) / 100;

	/* Determine the output frequency for selected values */
	fout = ((fref * mfd) / BUSDIV);
#endif
#ifdef CONFIG_MCF532x
	mfd = (4 * BUSDIV * temp) / 100;

	/* Determine the output frequency for selected values */
	fout = ((fref * mfd) / (BUSDIV * 4));
#endif

/* must not tamper with SDRAMC if running from SDRAM */
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
	/*
	 * Check to see if the SDRAM has already been initialized.
	 * If it has then the SDRAM needs to be put into self refresh
	 * mode before reprogramming the PLL.
	 */
	if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
		clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);

	/*
	 * Initialize the PLL to generate the new system clock frequency.
	 * The device must be put into LIMP mode to reprogram the PLL.
	 */

	/* Enter LIMP mode */
	clock_limp(DEFAULT_LPD);

#ifdef CONFIG_MCF5301x
	out_be32(&pll->pdr,
		PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
		PLL_PDR_OUTDIV2(BUSDIV - 1)	|
		PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
		PLL_PDR_OUTDIV4(USBDIV - 1));

	clrbits_be32(&pll->pcr, ~PLL_PCR_FBDIV_UNMASK);
	setbits_be32(&pll->pcr, PLL_PCR_FBDIV(mfd - 1));
#endif
#ifdef CONFIG_MCF532x
	/* Reprogram PLL for desired fsys */
	out_8(&pll->podr,
		PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));

	out_8(&pll->pfdr, mfd);
#endif

	/* Exit LIMP mode */
	clock_exit_limp();

	/* Return the SDRAM to normal operation if it is in use. */
	if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
		setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);

#ifdef CONFIG_MCF532x
	/*
	 * software workaround for SDRAM opeartion after exiting LIMP
	 * mode errata
	 */
	out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE);
#endif

	/* wait for DQS logic to relock */
	for (i = 0; i < 0x200; i++) ;
#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */

	return fout;
}

/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
int get_clocks(void)
{
	gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
	gd->cpu_clk = (gd->bus_clk * 3);

#ifdef CONFIG_FSL_I2C
	gd->i2c1_clk = gd->bus_clk;
#endif

	return (0);
}
Commit	Line	Data
8e585f02 TL	1	/*
	2	*
	3	* (C) Copyright 2000-2003
	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	5	*
aa0d99fc	6	* Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
8e585f02 TL	7	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <common.h>
	29	#include <asm/processor.h>
	30
b9bf3de3	31	#include <asm/immap.h>
aa0d99fc	32	#include <asm/io.h>
8e585f02	33
1218abf1 WD	34	DECLARE_GLOBAL_DATA_PTR;
1218abf1 WD	35
8e585f02	36	/* PLL min/max specifications */
b9bf3de3 TL	37	#define MAX_FVCO 500000 /* KHz */
	38	#define MAX_FSYS 80000 /* KHz */
	39	#define MIN_FSYS 58333 /* KHz */
536e7dac TL	40
	41	#ifdef CONFIG_MCF5301x
	42	#define FREF 20000 /* KHz */
	43	#define MAX_MFD 63 /* Multiplier */
	44	#define MIN_MFD 0 /* Multiplier */
	45	#define USBDIV 8
	46
	47	/* Low Power Divider specifications */
	48	#define MIN_LPD (0) /* Divider (not encoded) */
	49	#define MAX_LPD (15) /* Divider (not encoded) */
	50	#define DEFAULT_LPD (0) /* Divider (not encoded) */
	51	#endif
	52
	53	#ifdef CONFIG_MCF532x
b9bf3de3 TL	54	#define FREF 16000 /* KHz */
	55	#define MAX_MFD 135 /* Multiplier */
	56	#define MIN_MFD 88 /* Multiplier */
536e7dac TL	57
536e7dac TL	58	/* Low Power Divider specifications */
b9bf3de3 TL	59	#define MIN_LPD (1 << 0) /* Divider (not encoded) */
	60	#define MAX_LPD (1 << 15) /* Divider (not encoded) */
	61	#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
536e7dac	62	#endif
8e585f02	63
536e7dac TL	64	#define BUSDIV 6 /* Divider */
	65
	66	/* Get the value of the current system clock */
8e585f02 TL	67	int get_sys_clock(void)
8e585f02 TL	68	{
aa0d99fc AW	69	ccm_t ccm = (ccm_t )(MMAP_CCM);
aa0d99fc AW	70	pll_t pll = (pll_t )(MMAP_PLL);
8e585f02 TL	71	int divider;
	72
	73	/* Test to see if device is in LIMP mode */
aa0d99fc AW	74	if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) {
aa0d99fc AW	75	divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF);
536e7dac TL	76	#ifdef CONFIG_MCF5301x
	77	return (FREF / (3 * (1 << divider)));
	78	#endif
	79	#ifdef CONFIG_MCF532x
8e585f02	80	return (FREF / (2 << divider));
536e7dac	81	#endif
8e585f02	82	} else {
536e7dac	83	#ifdef CONFIG_MCF5301x
aa0d99fc AW	84	u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1;
	85	u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8));
	86	u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1;
536e7dac TL	87
	88	return (((FREF * pfdr) / refdiv) / busdiv);
	89	#endif
	90	#ifdef CONFIG_MCF532x
aa0d99fc	91	return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4);
536e7dac	92	#endif
8e585f02 TL	93	}
	94	}
	95
	96	/*
	97	* Initialize the Low Power Divider circuit
	98	*
	99	* Parameters:
	100	* div Desired system frequency divider
	101	*
	102	* Return Value:
	103	* The resulting output system frequency
	104	*/
	105	int clock_limp(int div)
	106	{
aa0d99fc	107	ccm_t ccm = (ccm_t )(MMAP_CCM);
8e585f02 TL	108	u32 temp;
	109
	110	/* Check bounds of divider */
	111	if (div < MIN_LPD)
	112	div = MIN_LPD;
	113	if (div > MAX_LPD)
	114	div = MAX_LPD;
	115
	116	/* Save of the current value of the SSIDIV so we don't overwrite the value */
aa0d99fc	117	temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF));
8e585f02 TL	118
8e585f02 TL	119	/* Apply the divider to the system clock */
aa0d99fc	120	out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) \| CCM_CDR_SSIDIV(temp));
8e585f02	121
aa0d99fc	122	setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
8e585f02 TL	123
	124	return (FREF / (3 * (1 << div)));
	125	}
	126
536e7dac	127	/* Exit low power LIMP mode */
8e585f02 TL	128	int clock_exit_limp(void)
8e585f02 TL	129	{
aa0d99fc	130	ccm_t ccm = (ccm_t )(MMAP_CCM);
8e585f02 TL	131	int fout;
	132
	133	/* Exit LIMP mode */
aa0d99fc	134	clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
8e585f02 TL	135
8e585f02 TL	136	/* Wait for PLL to lock */
aa0d99fc AW	137	while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK))
aa0d99fc AW	138	;
8e585f02 TL	139
	140	fout = get_sys_clock();
	141
	142	return fout;
	143	}
	144
	145	/* Initialize the PLL
	146	*
	147	* Parameters:
	148	* fref PLL reference clock frequency in KHz
	149	* fsys Desired PLL output frequency in KHz
	150	* flags Operating parameters
	151	*
	152	* Return Value:
	153	* The resulting output system frequency
	154	*/
	155	int clock_pll(int fsys, int flags)
	156	{
536e7dac	157	#ifdef CONFIG_MCF532x
aa0d99fc	158	u32 sdram_workaround = (u32 )(MMAP_SDRAM + 0x80);
536e7dac	159	#endif
aa0d99fc AW	160	sdram_t sdram = (sdram_t )(MMAP_SDRAM);
aa0d99fc AW	161	pll_t pll = (pll_t )(MMAP_PLL);
8e585f02 TL	162	int fref, temp, fout, mfd;
	163	u32 i;
	164
	165	fref = FREF;
	166
	167	if (fsys == 0) {
	168	/* Return current PLL output */
536e7dac	169	#ifdef CONFIG_MCF5301x
aa0d99fc AW	170	u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1;
aa0d99fc AW	171	mfd = (in_be32(&pll->pcr) & 0x3F) + 1;
536e7dac TL	172
	173	return (fref * mfd) / busdiv;
	174	#endif
	175	#ifdef CONFIG_MCF532x
aa0d99fc	176	mfd = in_8(&pll->pfdr);
8e585f02 TL	177
8e585f02 TL	178	return (fref * mfd / (BUSDIV * 4));
536e7dac	179	#endif
8e585f02 TL	180	}
	181
	182	/* Check bounds of requested system clock */
	183	if (fsys > MAX_FSYS)
	184	fsys = MAX_FSYS;
	185
	186	if (fsys < MIN_FSYS)
	187	fsys = MIN_FSYS;
	188
536e7dac TL	189	/*
	190	* Multiplying by 100 when calculating the temp value,
	191	* and then dividing by 100 to calculate the mfd allows
	192	* for exact values without needing to include floating
	193	* point libraries.
	194	*/
8e585f02	195	temp = (100 * fsys) / fref;
536e7dac TL	196	#ifdef CONFIG_MCF5301x
	197	mfd = (BUSDIV * temp) / 100;
	198
	199	/* Determine the output frequency for selected values */
	200	fout = ((fref * mfd) / BUSDIV);
	201	#endif
	202	#ifdef CONFIG_MCF532x
8e585f02 TL	203	mfd = (4 * BUSDIV * temp) / 100;
	204
	205	/* Determine the output frequency for selected values */
	206	fout = ((fref * mfd) / (BUSDIV * 4));
536e7dac	207	#endif
8e585f02	208
c7de810c WW	209	/* must not tamper with SDRAMC if running from SDRAM */
c7de810c WW	210	#if !defined(CONFIG_MONITOR_IS_IN_RAM)
8e585f02 TL	211	/*
	212	* Check to see if the SDRAM has already been initialized.
	213	* If it has then the SDRAM needs to be put into self refresh
	214	* mode before reprogramming the PLL.
	215	*/
aa0d99fc AW	216	if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
aa0d99fc AW	217	clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
8e585f02 TL	218
	219	/*
	220	* Initialize the PLL to generate the new system clock frequency.
	221	* The device must be put into LIMP mode to reprogram the PLL.
	222	*/
	223
	224	/* Enter LIMP mode */
	225	clock_limp(DEFAULT_LPD);
	226
536e7dac	227	#ifdef CONFIG_MCF5301x
aa0d99fc AW	228	out_be32(&pll->pdr,
	229	PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) \|
	230	PLL_PDR_OUTDIV2(BUSDIV - 1) \|
	231	PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) \|
	232	PLL_PDR_OUTDIV4(USBDIV - 1));
	233
	234	clrbits_be32(&pll->pcr, ~PLL_PCR_FBDIV_UNMASK);
	235	setbits_be32(&pll->pcr, PLL_PCR_FBDIV(mfd - 1));
536e7dac TL	236	#endif
536e7dac TL	237	#ifdef CONFIG_MCF532x
8e585f02	238	/* Reprogram PLL for desired fsys */
aa0d99fc AW	239	out_8(&pll->podr,
aa0d99fc AW	240	PLL_PODR_CPUDIV(BUSDIV / 3) \| PLL_PODR_BUSDIV(BUSDIV));
8e585f02	241
aa0d99fc	242	out_8(&pll->pfdr, mfd);
536e7dac	243	#endif
8e585f02 TL	244
	245	/* Exit LIMP mode */
	246	clock_exit_limp();
	247
536e7dac	248	/* Return the SDRAM to normal operation if it is in use. */
aa0d99fc AW	249	if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
aa0d99fc AW	250	setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
536e7dac TL	251
536e7dac TL	252	#ifdef CONFIG_MCF532x
8e585f02	253	/*
536e7dac TL	254	* software workaround for SDRAM opeartion after exiting LIMP
536e7dac TL	255	* mode errata
8e585f02	256	*/
aa0d99fc	257	out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE);
536e7dac	258	#endif
b9bf3de3	259
8e585f02 TL	260	/* wait for DQS logic to relock */
8e585f02 TL	261	for (i = 0; i < 0x200; i++) ;
c7de810c	262	#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */
8e585f02 TL	263
	264	return fout;
	265	}
	266
536e7dac	267	/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
8e585f02 TL	268	int get_clocks(void)
8e585f02 TL	269	{
6d0f6bcf	270	gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
8e585f02	271	gd->cpu_clk = (gd->bus_clk * 3);
eec567a6 TL	272
	273	#ifdef CONFIG_FSL_I2C
	274	gd->i2c1_clk = gd->bus_clk;
	275	#endif
	276
8e585f02 TL	277	return (0);
8e585f02 TL	278	}