[thirdparty/u-boot.git] / arch / m68k / cpu / mcf547x_8x / cpu.c

// SPDX-License-Identifier: GPL-2.0+
/*
 *
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 */

#include <common.h>
#include <init.h>
#include <net.h>
#include <vsprintf.h>
#include <watchdog.h>
#include <command.h>
#include <netdev.h>

#include <asm/immap.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);

	out_be16(&gptmr->pre, 10);
	out_be16(&gptmr->cnt, 1);

	/* enable watchdog, set timeout to 0 and wait */
	out_8(&gptmr->mode, GPT_TMS_SGPIO);
	out_8(&gptmr->ctrl, GPT_CTRL_WDEN | GPT_CTRL_CE);

	/* we don't return! */
	return 1;
};

#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
	siu_t *siu = (siu_t *) MMAP_SIU;
	u16 id = 0;

	puts("CPU:   ");

	switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) {
	case 0x0C:
		id = 5485;
		break;
	case 0x0D:
		id = 5484;
		break;
	case 0x0E:
		id = 5483;
		break;
	case 0x0F:
		id = 5482;
		break;
	case 0x10:
		id = 5481;
		break;
	case 0x11:
		id = 5480;
		break;
	case 0x12:
		id = 5475;
		break;
	case 0x13:
		id = 5474;
		break;
	case 0x14:
		id = 5473;
		break;
	case 0x15:
		id = 5472;
		break;
	case 0x16:
		id = 5471;
		break;
	case 0x17:
		id = 5470;
		break;
	}

	if (id) {
		char buf1[32], buf2[32];

		printf("Freescale MCF%d\n", id);
		printf("       CPU CLK %s MHz BUS CLK %s MHz\n",
		       strmhz(buf1, gd->cpu_clk),
		       strmhz(buf2, gd->bus_clk));
	}

	return 0;
};
#endif /* CONFIG_DISPLAY_CPUINFO */

#if defined(CONFIG_HW_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
void hw_watchdog_reset(void)
{
	gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);

	out_8(&gptmr->ocpw, 0xa5);
}

int watchdog_disable(void)
{
	gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);

	/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
	out_8(&gptmr->mode, 0);
	out_8(&gptmr->ctrl, 0);

	puts("WATCHDOG:disabled\n");

	return (0);
}

int watchdog_init(void)
{
	gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);

	out_be16(&gptmr->pre, CONFIG_WATCHDOG_TIMEOUT);
	out_be16(&gptmr->cnt, CONFIG_SYS_TIMER_PRESCALER * 1000);

	out_8(&gptmr->mode, GPT_TMS_SGPIO);
	out_8(&gptmr->ctrl, GPT_CTRL_CE | GPT_CTRL_WDEN);
	puts("WATCHDOG:enabled\n");

	return (0);
}
#endif				/* CONFIG_HW_WATCHDOG */

#if defined(CONFIG_FSLDMAFEC) || defined(CONFIG_MCFFEC)
/* Default initializations for MCFFEC controllers.  To override,
 * create a board-specific function called:
 * 	int board_eth_init(bd_t *bis)
 */

int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSLDMAFEC)
	mcdmafec_initialize(bis);
#endif
#if defined(CONFIG_MCFFEC)
	mcffec_initialize(bis);
#endif
	return 0;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
570c0186 TL	2	/*
	3	*
	4	* (C) Copyright 2000-2003
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
a4110eec	7	* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
570c0186	8	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
570c0186 TL	9	*/
	10
	11	#include <common.h>
691d719d	12	#include <init.h>
90526e9f	13	#include <net.h>
2189d5f1	14	#include <vsprintf.h>
570c0186 TL	15	#include <watchdog.h>
570c0186 TL	16	#include <command.h>
89973f8a	17	#include <netdev.h>
570c0186 TL	18
570c0186 TL	19	#include <asm/immap.h>
a4110eec	20	#include <asm/io.h>
570c0186 TL	21
	22	DECLARE_GLOBAL_DATA_PTR;
	23
09140113	24	int do_reset(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
570c0186	25	{
a4110eec	26	gptmr_t gptmr = (gptmr_t ) (MMAP_GPTMR);
570c0186	27
a4110eec AW	28	out_be16(&gptmr->pre, 10);
a4110eec AW	29	out_be16(&gptmr->cnt, 1);
570c0186 TL	30
570c0186 TL	31	/* enable watchdog, set timeout to 0 and wait */
a4110eec AW	32	out_8(&gptmr->mode, GPT_TMS_SGPIO);
a4110eec AW	33	out_8(&gptmr->ctrl, GPT_CTRL_WDEN \| GPT_CTRL_CE);
570c0186 TL	34
	35	/* we don't return! */
	36	return 1;
	37	};
	38
b9153fe3 AD	39	#if defined(CONFIG_DISPLAY_CPUINFO)
b9153fe3 AD	40	int print_cpuinfo(void)
570c0186	41	{
a4110eec	42	siu_t siu = (siu_t ) MMAP_SIU;
570c0186 TL	43	u16 id = 0;
	44
	45	puts("CPU: ");
	46
a4110eec	47	switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) {
570c0186 TL	48	case 0x0C:
	49	id = 5485;
	50	break;
	51	case 0x0D:
	52	id = 5484;
	53	break;
	54	case 0x0E:
	55	id = 5483;
	56	break;
	57	case 0x0F:
	58	id = 5482;
	59	break;
	60	case 0x10:
	61	id = 5481;
	62	break;
	63	case 0x11:
	64	id = 5480;
	65	break;
	66	case 0x12:
	67	id = 5475;
	68	break;
	69	case 0x13:
	70	id = 5474;
	71	break;
	72	case 0x14:
	73	id = 5473;
	74	break;
	75	case 0x15:
	76	id = 5472;
	77	break;
	78	case 0x16:
	79	id = 5471;
	80	break;
	81	case 0x17:
	82	id = 5470;
	83	break;
	84	}
	85
	86	if (id) {
08ef89ec WD	87	char buf1[32], buf2[32];
08ef89ec WD	88
570c0186	89	printf("Freescale MCF%d\n", id);
08ef89ec WD	90	printf(" CPU CLK %s MHz BUS CLK %s MHz\n",
	91	strmhz(buf1, gd->cpu_clk),
	92	strmhz(buf2, gd->bus_clk));
570c0186 TL	93	}
	94
	95	return 0;
	96	};
b9153fe3	97	#endif /* CONFIG_DISPLAY_CPUINFO */
570c0186 TL	98
	99	#if defined(CONFIG_HW_WATCHDOG)
	100	/* Called by macro WATCHDOG_RESET */
	101	void hw_watchdog_reset(void)
	102	{
a4110eec	103	gptmr_t gptmr = (gptmr_t ) (MMAP_GPTMR);
570c0186	104
a4110eec	105	out_8(&gptmr->ocpw, 0xa5);
570c0186 TL	106	}
	107
	108	int watchdog_disable(void)
	109	{
a4110eec	110	gptmr_t gptmr = (gptmr_t ) (MMAP_GPTMR);
570c0186 TL	111
570c0186 TL	112	/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
a4110eec AW	113	out_8(&gptmr->mode, 0);
a4110eec AW	114	out_8(&gptmr->ctrl, 0);
570c0186 TL	115
	116	puts("WATCHDOG:disabled\n");
	117
	118	return (0);
	119	}
	120
	121	int watchdog_init(void)
	122	{
a4110eec	123	gptmr_t gptmr = (gptmr_t ) (MMAP_GPTMR);
570c0186	124
a4110eec AW	125	out_be16(&gptmr->pre, CONFIG_WATCHDOG_TIMEOUT);
a4110eec AW	126	out_be16(&gptmr->cnt, CONFIG_SYS_TIMER_PRESCALER * 1000);
570c0186	127
a4110eec AW	128	out_8(&gptmr->mode, GPT_TMS_SGPIO);
a4110eec AW	129	out_8(&gptmr->ctrl, GPT_CTRL_CE \| GPT_CTRL_WDEN);
570c0186 TL	130	puts("WATCHDOG:enabled\n");
	131
	132	return (0);
	133	}
	134	#endif /* CONFIG_HW_WATCHDOG */
b31da88b	135
86882b80 BW	136	#if defined(CONFIG_FSLDMAFEC) \|\| defined(CONFIG_MCFFEC)
	137	/* Default initializations for MCFFEC controllers. To override,
	138	* create a board-specific function called:
	139	* int board_eth_init(bd_t *bis)
	140	*/
	141
b31da88b BW	142	int cpu_eth_init(bd_t *bis)
b31da88b BW	143	{
86882b80 BW	144	#if defined(CONFIG_FSLDMAFEC)
	145	mcdmafec_initialize(bis);
	146	#endif
	147	#if defined(CONFIG_MCFFEC)
	148	mcffec_initialize(bis);
	149	#endif
	150	return 0;
b31da88b BW	151	}
b31da88b BW	152	#endif