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570c0186 TL |
1 | /* |
2 | * | |
a4110eec | 3 | * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. |
570c0186 TL |
4 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
570c0186 TL |
7 | */ |
8 | ||
9 | /* CPU specific interrupt routine */ | |
10 | #include <common.h> | |
11 | #include <asm/immap.h> | |
a4110eec | 12 | #include <asm/io.h> |
570c0186 TL |
13 | |
14 | int interrupt_init(void) | |
15 | { | |
a4110eec | 16 | int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); |
570c0186 TL |
17 | |
18 | /* Make sure all interrupts are disabled */ | |
a4110eec AW |
19 | setbits_be32(&intp->imrh0, 0xffffffff); |
20 | setbits_be32(&intp->imrl0, 0xffffffff); | |
570c0186 TL |
21 | |
22 | enable_interrupts(); | |
23 | ||
24 | return 0; | |
25 | } | |
26 | ||
27 | #if defined(CONFIG_SLTTMR) | |
28 | void dtimer_intr_setup(void) | |
29 | { | |
a4110eec | 30 | int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); |
570c0186 | 31 | |
a4110eec AW |
32 | out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); |
33 | clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); | |
570c0186 TL |
34 | } |
35 | #endif |