[thirdparty/u-boot.git] / arch / m68k / include / asm / coldfire / flexcan.h

/*
 * Flex CAN Memory Map
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __FLEXCAN_H__
#define __FLEXCAN_H__

/* FlexCan Message Buffer */
typedef struct can_msgbuf_ctrl {
#ifdef CONFIG_M5282
	u8 tmstamp;		/* 0x00 Timestamp */
	u8 ctrl;		/* 0x01 Control */
	u16 idh;		/* 0x02 ID High */
	u16 idl;		/* 0x04 ID High */
	u8 data[8];		/* 0x06 8 Byte Data Field */
	u16 res;		/* 0x0E */
#else
	u16 ctrl;		/* 0x00 Control/Status */
	u16 tmstamp;		/* 0x02 Timestamp */
	u32 id;			/* 0x04 Identifier */
	u8 data[8];		/* 0x08 8 Byte Data Field */
#endif
} can_msg_t;

#ifdef CONFIG_M5282
/* MSGBUF CTRL */
#define CAN_MSGBUF_CTRL_CODE(x)		(((x) & 0x0F) << 4)
#define CAN_MSGBUF_CTRL_CODE_MASK	(0x0F)
#define CAN_MSGBUF_CTRL_LEN(x)		((x) & 0x0F)
#define CAN_MSGBUF_CTRL_LEN_MASK	(0xF0)

/* MSGBUF ID */
#define CAN_MSGBUF_IDH_STD(x)		(((x) & 0x07FF) << 5)
#define CAN_MSGBUF_IDH_STD_MASK		(0xE003FFFF)
#define CAN_MSGBUF_IDH_SRR		(0x0010)
#define CAN_MSGBUF_IDH_IDE		(0x0080)
#define CAN_MSGBUF_IDH_EXTH(x)		((x) & 0x07)
#define CAN_MSGBUF_IDH_EXTH_MASK	(0xFFF8)
#define CAN_MSGBUF_IDL_EXTL(x)		(((x) & 0x7FFF) << 1)
#define CAN_MSGBUF_IDL_EXTL_MASK		(0xFFFE)
#define CAN_MSGBUF_IDL_RTR		(0x0001)
#else
/* MSGBUF CTRL */
#define CAN_MSGBUF_CTRL_CODE(x)		(((x) & 0x000F) << 8)
#define CAN_MSGBUF_CTRL_CODE_MASK	(0xF0FF)
#define CAN_MSGBUF_CTRL_SRR		(0x0040)
#define CAN_MSGBUF_CTRL_IDE		(0x0020)
#define CAN_MSGBUF_CTRL_RTR		(0x0010)
#define CAN_MSGBUF_CTRL_LEN(x)		((x) & 0x000F)
#define CAN_MSGBUF_CTRL_LEN_MASK	(0xFFF0)

/* MSGBUF ID */
#define CAN_MSGBUF_ID_STD(x)		(((x) & 0x000007FF) << 18)
#define CAN_MSGBUF_ID_STD_MASK		(0xE003FFFF)
#define CAN_MSGBUF_ID_EXT(x)		((x) & 0x0003FFFF)
#define CAN_MSGBUF_ID_EXT_MASK		(0xFFFC0000)
#endif

/* FlexCan module */
typedef struct can_ctrl {
	u32 mcr;		/* 0x00 Module Configuration */
	u32 ctrl;		/* 0x04 Control */
	u32 timer;		/* 0x08 Free Running Timer */
	u32 res1;		/* 0x0C */
	u32 rxgmsk;		/* 0x10 Rx Global Mask */
	u32 rx14msk;		/* 0x14 RxBuffer 14 Mask */
	u32 rx15msk;		/* 0x18 RxBuffer 15 Mask */
#ifdef CONFIG_M5282
	u32 res2;		/* 0x1C */
	u16 errstat;		/* 0x20 Error and status */
	u16 imsk;		/* 0x22 Interrupt Mask */
	u16 iflag;		/* 0x24 Interrupt Flag */
	u16 errcnt;		/* 0x26 Error Counter */
	u32 res3[3];		/* 0x28 - 0x33 */
#else
	u16 res2;		/* 0x1C */
	u16 errcnt;		/* 0x1E Error Counter */
	u16 res3;		/* 0x20 */
	u16 errstat;		/* 0x22 Error and status */
	u32 res4;		/* 0x24 */
	u32 imsk;		/* 0x28 Interrupt Mask */
	u32 res5;		/* 0x2C */
	u16 iflag;		/* 0x30 Interrupt Flag */
#endif
	u32 res6[19];		/* 0x34 - 0x7F */
	void *msgbuf;		/* 0x80 Message Buffer 0-15 */
} can_t;

/* MCR */
#define CAN_MCR_MDIS			(0x80000000)
#define CAN_MCR_FRZ			(0x40000000)
#define CAN_MCR_HALT			(0x10000000)
#define CAN_MCR_NORDY			(0x08000000)
#define CAN_MCF_WAKEMSK			(0x04000000)	/* 5282 */
#define CAN_MCR_SOFTRST			(0x02000000)
#define CAN_MCR_FRZACK			(0x01000000)
#define CAN_MCR_SUPV			(0x00800000)
#define CAN_MCR_SELFWAKE		(0x00400000)	/* 5282 */
#define CAN_MCR_APS			(0x00200000)	/* 5282 */
#define CAN_MCR_LPMACK			(0x00100000)
#define CAN_MCF_BCC			(0x00010000)
#define CAN_MCR_MAXMB(x)		((x) & 0x0F)
#define CAN_MCR_MAXMB_MASK		(0xFFFFFFF0)

/* CTRL */
#define CAN_CTRL_PRESDIV(x)		(((x) & 0xFF) << 24)
#define CAN_CTRL_PRESDIV_MASK		(0x00FFFFFF)
#define CAN_CTRL_RJW(x)			(((x) & 0x03) << 22)
#define CAN_CTRL_RJW_MASK		(0xFF3FFFFF)
#define CAN_CTRL_PSEG1(x)		(((x) & 0x07) << 19)
#define CAN_CTRL_PSEG1_MASK		(0xFFC7FFFF)
#define CAN_CTRL_PSEG2(x)		(((x) & 0x07) << 16)
#define CAN_CTRL_PSEG2_MASK		(0xFFF8FFFF)
#define CAN_CTRL_BOFFMSK		(0x00008000)
#define CAN_CTRL_ERRMSK			(0x00004000)
#define CAN_CTRL_CLKSRC			(0x00002000)
#define CAN_CTRL_LPB			(0x00001000)
#define CAN_CTRL_RXMODE			(0x00000400)	/* 5282 */
#define CAN_CTRL_TXMODE(x)		(((x) & 0x03) << 8)	/* 5282 */
#define CAN_CTRL_TXMODE_MASK		(0xFFFFFCFF)	/* 5282 */
#define CAN_CTRL_TXMODE_CAN0		(0x00000000)	/* 5282 */
#define CAN_CTRL_TXMODE_CAN1		(0x00000100)	/* 5282 */
#define CAN_CTRL_TXMODE_OPEN		(0x00000200)	/* 5282 */
#define CAN_CTRL_SMP			(0x00000080)
#define CAN_CTRL_BOFFREC		(0x00000040)
#define CAN_CTRL_TSYNC			(0x00000020)
#define CAN_CTRL_LBUF			(0x00000010)
#define CAN_CTRL_LOM			(0x00000008)
#define CAN_CTRL_PROPSEG(x)		((x) & 0x07)
#define CAN_CTRL_PROPSEG_MASK		(0xFFFFFFF8)

/* TIMER */
/* Note: PRESDIV, RJW, PSG1, and PSG2 are part of timer in 5282 */
#define CAN_TIMER(x)			((x) & 0xFFFF)
#define CAN_TIMER_MASK			(0xFFFF0000)

/* RXGMASK */
#ifdef CONFIG_M5282
#define CAN_RXGMSK_MI_STD(x)		(((x) & 0x000007FF) << 21)
#define CAN_RXGMSK_MI_STD_MASK		(0x001FFFFF)
#define CAN_RXGMSK_MI_EXT(x)		(((x) & 0x0003FFFF) << 1)
#define CAN_RXGMSK_MI_EXT_MASK		(0xFFF80001)
#else
#define CAN_RXGMSK_MI_STD(x)		(((x) & 0x000007FF) << 18)
#define CAN_RXGMSK_MI_STD_MASK		(0xE003FFFF)
#define CAN_RXGMSK_MI_EXT(x)		((x) & 0x0003FFFF)
#define CAN_RXGMSK_MI_EXT_MASK		(0xFFFC0000)
#endif

/* ERRCNT */
#define CAN_ERRCNT_RXECTR(x)		(((x) & 0xFF) << 8)
#define CAN_ERRCNT_RXECTR_MASK		(0x00FF)
#define CAN_ERRCNT_TXECTR(x)		((x) & 0xFF)
#define CAN_ERRCNT_TXECTR_MASK		(0xFF00)

/* ERRSTAT */
#define CAN_ERRSTAT_BITERR1		(0x8000)
#define CAN_ERRSTAT_BITERR0		(0x4000)
#define CAN_ERRSTAT_ACKERR		(0x2000)
#define CAN_ERRSTAT_CRCERR		(0x1000)
#define CAN_ERRSTAT_FRMERR		(0x0800)
#define CAN_ERRSTAT_STFERR		(0x0400)
#define CAN_ERRSTAT_TXWRN		(0x0200)
#define CAN_ERRSTAT_RXWRN		(0x0100)
#define CAN_ERRSTAT_IDLE		(0x0080)
#define CAN_ERRSTAT_TXRX		(0x0040)
#define CAN_ERRSTAT_FLT_MASK		(0xFFCF)
#define CAN_ERRSTAT_FLT_BUSOFF		(0x0020)
#define CAN_ERRSTAT_FLT_PASSIVE		(0x0010)
#define CAN_ERRSTAT_FLT_ACTIVE		(0x0000)
#ifdef CONFIG_M5282
#define CAN_ERRSTAT_BOFFINT		(0x0004)
#define CAN_ERRSTAT_ERRINT		(0x0002)
#else
#define CAN_ERRSTAT_ERRINT		(0x0004)
#define CAN_ERRSTAT_BOFFINT		(0x0002)
#define CAN_ERRSTAT_WAKEINT		(0x0001)
#endif

/* IMASK */
#ifdef CONFIG_M5253
#define CAN_IMASK_BUFnM(x)		(1 << (x & 0xFFFFFFFF))
#define CAN_IMASK_BUFnM_MASKBIT(x)	~CAN_IMASK_BUFnM(x)
#else
#define CAN_IMASK_BUFnM(x)		(1 << (x & 0xFFFF))
#define CAN_IMASK_BUFnM_MASKBIT(x)	~CAN_IMASK_BUFnM(x)
#endif

/* IFLAG */
#ifdef CONFIG_M5253
#define CAN_IFLAG_BUFnM(x)		(1 << (x & 0xFFFFFFFF))
#define CAN_IFLAG_BUFnM_MASKBIT(x)	~CAN_IFLAG_BUFnM(x)
#else
#define CAN_IFLAG_BUFnM(x)		(1 << (x & 0xFFFF))
#define CAN_IFLAG_BUFnM_MASKBIT(x)	~CAN_IFLAG_BUFnM(x)
#endif

#endif				/* __FLEXCAN_H__ */
Commit	Line	Data
012522fe TL	1	/*
	2	* Flex CAN Memory Map
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
012522fe TL	8	*/
	9
	10	#ifndef __FLEXCAN_H__
	11	#define __FLEXCAN_H__
	12
	13	/* FlexCan Message Buffer */
	14	typedef struct can_msgbuf_ctrl {
	15	#ifdef CONFIG_M5282
	16	u8 tmstamp; /* 0x00 Timestamp */
	17	u8 ctrl; /* 0x01 Control */
	18	u16 idh; /* 0x02 ID High */
	19	u16 idl; /* 0x04 ID High */
	20	u8 data[8]; /* 0x06 8 Byte Data Field */
	21	u16 res; /* 0x0E */
	22	#else
	23	u16 ctrl; /* 0x00 Control/Status */
	24	u16 tmstamp; /* 0x02 Timestamp */
	25	u32 id; /* 0x04 Identifier */
	26	u8 data[8]; /* 0x08 8 Byte Data Field */
	27	#endif
	28	} can_msg_t;
	29
	30	#ifdef CONFIG_M5282
	31	/* MSGBUF CTRL */
	32	#define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x0F) << 4)
	33	#define CAN_MSGBUF_CTRL_CODE_MASK (0x0F)
	34	#define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x0F)
	35	#define CAN_MSGBUF_CTRL_LEN_MASK (0xF0)
	36
	37	/* MSGBUF ID */
	38	#define CAN_MSGBUF_IDH_STD(x) (((x) & 0x07FF) << 5)
	39	#define CAN_MSGBUF_IDH_STD_MASK (0xE003FFFF)
	40	#define CAN_MSGBUF_IDH_SRR (0x0010)
	41	#define CAN_MSGBUF_IDH_IDE (0x0080)
	42	#define CAN_MSGBUF_IDH_EXTH(x) ((x) & 0x07)
	43	#define CAN_MSGBUF_IDH_EXTH_MASK (0xFFF8)
	44	#define CAN_MSGBUF_IDL_EXTL(x) (((x) & 0x7FFF) << 1)
	45	#define CAN_MSGBUF_IDL_EXTL_MASK (0xFFFE)
	46	#define CAN_MSGBUF_IDL_RTR (0x0001)
	47	#else
	48	/* MSGBUF CTRL */
	49	#define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x000F) << 8)
	50	#define CAN_MSGBUF_CTRL_CODE_MASK (0xF0FF)
	51	#define CAN_MSGBUF_CTRL_SRR (0x0040)
	52	#define CAN_MSGBUF_CTRL_IDE (0x0020)
	53	#define CAN_MSGBUF_CTRL_RTR (0x0010)
	54	#define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x000F)
	55	#define CAN_MSGBUF_CTRL_LEN_MASK (0xFFF0)
	56
	57	/* MSGBUF ID */
	58	#define CAN_MSGBUF_ID_STD(x) (((x) & 0x000007FF) << 18)
	59	#define CAN_MSGBUF_ID_STD_MASK (0xE003FFFF)
	60	#define CAN_MSGBUF_ID_EXT(x) ((x) & 0x0003FFFF)
	61	#define CAN_MSGBUF_ID_EXT_MASK (0xFFFC0000)
	62	#endif
	63
	64	/* FlexCan module */
	65	typedef struct can_ctrl {
	66	u32 mcr; /* 0x00 Module Configuration */
	67	u32 ctrl; /* 0x04 Control */
	68	u32 timer; /* 0x08 Free Running Timer */
	69	u32 res1; /* 0x0C */
	70	u32 rxgmsk; /* 0x10 Rx Global Mask */
	71	u32 rx14msk; /* 0x14 RxBuffer 14 Mask */
72	u32 rx15msk; /* 0x18 RxBuffer 15 Mask */
73	#ifdef CONFIG_M5282
74	u32 res2; /* 0x1C */
75	u16 errstat; /* 0x20 Error and status */
76	u16 imsk; /* 0x22 Interrupt Mask */
77	u16 iflag; /* 0x24 Interrupt Flag */
78	u16 errcnt; /* 0x26 Error Counter */
79	u32 res3[3]; /* 0x28 - 0x33 */
80	#else
81	u16 res2; /* 0x1C */
82	u16 errcnt; /* 0x1E Error Counter */
83	u16 res3; /* 0x20 */
84	u16 errstat; /* 0x22 Error and status */
85	u32 res4; /* 0x24 */
86	u32 imsk; /* 0x28 Interrupt Mask */
87	u32 res5; /* 0x2C */
88	u16 iflag; /* 0x30 Interrupt Flag */
89	#endif
90	u32 res6[19]; /* 0x34 - 0x7F */
91	void msgbuf; / 0x80 Message Buffer 0-15 */
92	} can_t;
93
94	/* MCR */
95	#define CAN_MCR_MDIS (0x80000000)
96	#define CAN_MCR_FRZ (0x40000000)
97	#define CAN_MCR_HALT (0x10000000)
98	#define CAN_MCR_NORDY (0x08000000)
99	#define CAN_MCF_WAKEMSK (0x04000000) /* 5282 */
100	#define CAN_MCR_SOFTRST (0x02000000)
101	#define CAN_MCR_FRZACK (0x01000000)
102	#define CAN_MCR_SUPV (0x00800000)
103	#define CAN_MCR_SELFWAKE (0x00400000) /* 5282 */
104	#define CAN_MCR_APS (0x00200000) /* 5282 */
105	#define CAN_MCR_LPMACK (0x00100000)
106	#define CAN_MCF_BCC (0x00010000)
107	#define CAN_MCR_MAXMB(x) ((x) & 0x0F)
108	#define CAN_MCR_MAXMB_MASK (0xFFFFFFF0)
109
110	/* CTRL */
111	#define CAN_CTRL_PRESDIV(x) (((x) & 0xFF) << 24)
112	#define CAN_CTRL_PRESDIV_MASK (0x00FFFFFF)
113	#define CAN_CTRL_RJW(x) (((x) & 0x03) << 22)
114	#define CAN_CTRL_RJW_MASK (0xFF3FFFFF)
115	#define CAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
116	#define CAN_CTRL_PSEG1_MASK (0xFFC7FFFF)
117	#define CAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
118	#define CAN_CTRL_PSEG2_MASK (0xFFF8FFFF)
119	#define CAN_CTRL_BOFFMSK (0x00008000)
120	#define CAN_CTRL_ERRMSK (0x00004000)
121	#define CAN_CTRL_CLKSRC (0x00002000)
122	#define CAN_CTRL_LPB (0x00001000)
123	#define CAN_CTRL_RXMODE (0x00000400) /* 5282 */
124	#define CAN_CTRL_TXMODE(x) (((x) & 0x03) << 8) /* 5282 */
125	#define CAN_CTRL_TXMODE_MASK (0xFFFFFCFF) /* 5282 */
126	#define CAN_CTRL_TXMODE_CAN0 (0x00000000) /* 5282 */
127	#define CAN_CTRL_TXMODE_CAN1 (0x00000100) /* 5282 */
128	#define CAN_CTRL_TXMODE_OPEN (0x00000200) /* 5282 */
129	#define CAN_CTRL_SMP (0x00000080)
130	#define CAN_CTRL_BOFFREC (0x00000040)
131	#define CAN_CTRL_TSYNC (0x00000020)
132	#define CAN_CTRL_LBUF (0x00000010)
133	#define CAN_CTRL_LOM (0x00000008)
134	#define CAN_CTRL_PROPSEG(x) ((x) & 0x07)
135	#define CAN_CTRL_PROPSEG_MASK (0xFFFFFFF8)
136
137	/* TIMER */
138	/* Note: PRESDIV, RJW, PSG1, and PSG2 are part of timer in 5282 */
139	#define CAN_TIMER(x) ((x) & 0xFFFF)
140	#define CAN_TIMER_MASK (0xFFFF0000)
141
142	/* RXGMASK */
143	#ifdef CONFIG_M5282
144	#define CAN_RXGMSK_MI_STD(x) (((x) & 0x000007FF) << 21)
145	#define CAN_RXGMSK_MI_STD_MASK (0x001FFFFF)
146	#define CAN_RXGMSK_MI_EXT(x) (((x) & 0x0003FFFF) << 1)
147	#define CAN_RXGMSK_MI_EXT_MASK (0xFFF80001)
148	#else
149	#define CAN_RXGMSK_MI_STD(x) (((x) & 0x000007FF) << 18)
150	#define CAN_RXGMSK_MI_STD_MASK (0xE003FFFF)
151	#define CAN_RXGMSK_MI_EXT(x) ((x) & 0x0003FFFF)
152	#define CAN_RXGMSK_MI_EXT_MASK (0xFFFC0000)
153	#endif
154
155	/* ERRCNT */
156	#define CAN_ERRCNT_RXECTR(x) (((x) & 0xFF) << 8)
157	#define CAN_ERRCNT_RXECTR_MASK (0x00FF)
158	#define CAN_ERRCNT_TXECTR(x) ((x) & 0xFF)
159	#define CAN_ERRCNT_TXECTR_MASK (0xFF00)
160
161	/* ERRSTAT */
162	#define CAN_ERRSTAT_BITERR1 (0x8000)
163	#define CAN_ERRSTAT_BITERR0 (0x4000)
164	#define CAN_ERRSTAT_ACKERR (0x2000)
165	#define CAN_ERRSTAT_CRCERR (0x1000)
166	#define CAN_ERRSTAT_FRMERR (0x0800)
167	#define CAN_ERRSTAT_STFERR (0x0400)
168	#define CAN_ERRSTAT_TXWRN (0x0200)
169	#define CAN_ERRSTAT_RXWRN (0x0100)
170	#define CAN_ERRSTAT_IDLE (0x0080)
171	#define CAN_ERRSTAT_TXRX (0x0040)
172	#define CAN_ERRSTAT_FLT_MASK (0xFFCF)
173	#define CAN_ERRSTAT_FLT_BUSOFF (0x0020)
174	#define CAN_ERRSTAT_FLT_PASSIVE (0x0010)
175	#define CAN_ERRSTAT_FLT_ACTIVE (0x0000)
176	#ifdef CONFIG_M5282
177	#define CAN_ERRSTAT_BOFFINT (0x0004)
178	#define CAN_ERRSTAT_ERRINT (0x0002)
179	#else
180	#define CAN_ERRSTAT_ERRINT (0x0004)
181	#define CAN_ERRSTAT_BOFFINT (0x0002)
182	#define CAN_ERRSTAT_WAKEINT (0x0001)
183	#endif
184
185	/* IMASK */
186	#ifdef CONFIG_M5253
187	#define CAN_IMASK_BUFnM(x) (1 << (x & 0xFFFFFFFF))
188	#define CAN_IMASK_BUFnM_MASKBIT(x) ~CAN_IMASK_BUFnM(x)
189	#else
190	#define CAN_IMASK_BUFnM(x) (1 << (x & 0xFFFF))
191	#define CAN_IMASK_BUFnM_MASKBIT(x) ~CAN_IMASK_BUFnM(x)
192	#endif
193
194	/* IFLAG */
195	#ifdef CONFIG_M5253
196	#define CAN_IFLAG_BUFnM(x) (1 << (x & 0xFFFFFFFF))
197	#define CAN_IFLAG_BUFnM_MASKBIT(x) ~CAN_IFLAG_BUFnM(x)
198	#else
199	#define CAN_IFLAG_BUFnM(x) (1 << (x & 0xFFFF))
200	#define CAN_IFLAG_BUFnM_MASKBIT(x) ~CAN_IFLAG_BUFnM(x)
201	#endif
202
203	#endif /* __FLEXCAN_H__ */