projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| cd42deeb SR |
1 | /* |
| 2 | * mcf5249.h -- Definitions for Motorola Coldfire 5249 | |
| 3 | * | |
| 4 | * Based on mcf5272sim.h of uCLinux distribution: | |
| 5 | * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) | |
| 6 | * (C) Copyright 2000, Lineo Inc. (www.lineo.com) | |
| 7 | * | |
| 1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
| cd42deeb SR |
9 | */ |
| 10 | ||
| cd42deeb SR |
11 | #ifndef mcf5249_h |
| 12 | #define mcf5249_h | |
| 13 | /****************************************************************************/ | |
| 14 | ||
| 15 | /* | |
| 16 | * useful definitions for reading/writing MBAR offset memory | |
| 17 | */ | |
| 6d0f6bcf JCPV |
18 | #define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) |
| 19 | #define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y | |
| 20 | #define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y | |
| 21 | #define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y | |
| 22 | #define mbar2_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) | |
| 23 | #define mbar2_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) = y | |
| 24 | #define mbar2_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR2 + x)) = y | |
| 25 | #define mbar2_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR2 + x)) = y | |
| cd42deeb SR |
26 | |
| 27 | /* | |
| 28 | * Size of internal RAM | |
| 29 | */ | |
| 30 | ||
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31 | #define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */ |
| 32 | #define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */ | |
| cd42deeb SR |
33 | |
| 34 | /* | |
| 35 | * Define the 5249 SIM register set addresses. | |
| 36 | */ | |
| 37 | ||
| 38 | /***************** | |
| 39 | ***** MBAR1 ***** | |
| 40 | *****************/ | |
| 56115665 TL |
41 | #define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ |
| 42 | #define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */ | |
| 43 | #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ | |
| 44 | #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ | |
| 53677ef1 | 45 | #define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */ |
| 56115665 TL |
46 | |
| 47 | #define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */ | |
| 48 | #define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ | |
| 49 | #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ | |
| 50 | #define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ | |
| 51 | #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ | |
| 52 | #define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ | |
| 53 | #define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ | |
| 54 | #define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ | |
| 55 | #define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ | |
| 56 | #define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ | |
| 57 | #define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ | |
| 58 | #define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ | |
| 59 | #define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ | |
| 60 | ||
| 61 | #define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ | |
| 62 | #define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ | |
| 63 | ||
| 56115665 TL |
64 | #define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ |
| 65 | #define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ | |
| 66 | #define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ | |
| 67 | #define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ | |
| 68 | #define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ | |
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69 | |
| 70 | /***************** | |
| 71 | ***** MBAR2 ***** | |
| 72 | *****************/ | |
| 73 | ||
| 74 | /* GPIO Addresses | |
| 75 | * Note: These are offset from MBAR2! | |
| 76 | */ | |
| 56115665 TL |
77 | #define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */ |
| 78 | #define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w) */ | |
| 79 | #define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w) */ | |
| 80 | #define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */ | |
| 81 | #define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */ | |
| 82 | #define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */ | |
| 83 | #define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */ | |
| 84 | #define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */ | |
| 85 | ||
| 86 | #define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */ | |
| 87 | #define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */ | |
| 88 | #define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */ | |
| 89 | ||
| 90 | #define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */ | |
| 91 | #define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */ | |
| 92 | #define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */ | |
| 93 | ||
| 94 | #define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */ | |
| 95 | #define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */ | |
| 96 | #define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */ | |
| 97 | #define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */ | |
| 98 | #define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */ | |
| 99 | #define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */ | |
| 100 | #define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */ | |
| 101 | #define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */ | |
| 102 | ||
| 103 | #define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */ | |
| 104 | #define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */ | |
| 105 | ||
| 106 | #define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */ | |
| 107 | #define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */ | |
| 108 | ||
| 109 | #define MCFSIM_PLLCR 0x180 /* PLL Control register */ | |
| cd42deeb | 110 | |
| cd42deeb SR |
111 | /* |
| 112 | * Some symbol defines for the above... | |
| 113 | */ | |
| 114 | #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ | |
| 115 | #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ | |
| 116 | #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ | |
| 117 | #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */ | |
| 118 | #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ | |
| 119 | #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ | |
| 120 | /* XXX - If needed, DMA ICRs go here */ | |
| 121 | #define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */ | |
| 122 | ||
| 123 | /* | |
| 124 | * Bit definitions for the ICR family of registers. | |
| 125 | */ | |
| 56115665 TL |
126 | #define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ |
| 127 | #define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ | |
| 128 | #define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ | |
| 129 | #define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ | |
| 130 | #define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ | |
| 131 | #define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ | |
| 132 | #define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ | |
| 133 | #define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ | |
| 134 | #define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ | |
| 135 | ||
| 136 | #define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ | |
| 137 | #define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ | |
| 138 | #define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ | |
| 139 | #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ | |
| cd42deeb SR |
140 | |
| 141 | /* | |
| 142 | * Macros to read/set IMR register. It is 32 bits on the 5249. | |
| 143 | */ | |
| 144 | ||
| 145 | #define mcf_getimr() \ | |
| 146 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) | |
| 147 | ||
| 148 | #define mcf_setimr(imr) \ | |
| 149 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); | |
| 150 | ||
| 56115665 | 151 | #endif /* mcf5249_h */ |