projects / thirdparty / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 1da177e4 LT |
2 | /****************************************************************************/ |
| 3 | ||
| 4 | /* | |
| 5 | * m528xsim.h -- ColdFire 5280/5282 System Integration Module support. | |
| 6 | * | |
| 7 | * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com) | |
| 8 | */ | |
| 9 | ||
| 10 | /****************************************************************************/ | |
| 11 | #ifndef m528xsim_h | |
| 12 | #define m528xsim_h | |
| 13 | /****************************************************************************/ | |
| 14 | ||
| 733f31b7 GU |
15 | #define CPU_NAME "COLDFIRE(m528x)" |
| 16 | #define CPU_INSTR_PER_JIFFY 3 | |
| ce3de78a | 17 | #define MCF_BUSCLK MCF_CLK |
| 1da177e4 | 18 | |
| a12cf0a8 GU |
19 | #include <asm/m52xxacr.h> |
| 20 | ||
| 1da177e4 LT |
21 | /* |
| 22 | * Define the 5280/5282 SIM register set addresses. | |
| 23 | */ | |
| 254eef74 GU |
24 | #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ |
| 25 | #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */ | |
| 26 | ||
| 1da177e4 LT |
27 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
| 28 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ | |
| 29 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ | |
| 30 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ | |
| 31 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ | |
| 32 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ | |
| 33 | #define MCFINTC_IRLR 0x18 /* */ | |
| 34 | #define MCFINTC_IACKL 0x19 /* */ | |
| 35 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ | |
| 36 | ||
| 37 | #define MCFINT_VECBASE 64 /* Vector base number */ | |
| 38 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ | |
| f8bb5327 GU |
39 | #define MCFINT_UART1 14 /* Interrupt number for UART1 */ |
| 40 | #define MCFINT_UART2 15 /* Interrupt number for UART2 */ | |
| 2d24b532 | 41 | #define MCFINT_I2C0 17 /* Interrupt number for I2C */ |
| 91d60417 | 42 | #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ |
| 4f8f9fb8 GU |
43 | #define MCFINT_FECRX0 23 /* Interrupt number for FEC */ |
| 44 | #define MCFINT_FECTX0 27 /* Interrupt number for FEC */ | |
| 45 | #define MCFINT_FECENTC0 29 /* Interrupt number for FEC */ | |
| 1da177e4 LT |
46 | #define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ |
| 47 | ||
| f8bb5327 GU |
48 | #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) |
| 49 | #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) | |
| 50 | #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) | |
| 51 | ||
| 4f8f9fb8 GU |
52 | #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) |
| 53 | #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) | |
| 54 | #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) | |
| 55 | ||
| 3b2039b2 | 56 | #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
| bdee4e26 | 57 | #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) |
| 2d24b532 SK |
58 | #define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0) |
| 59 | ||
| 1da177e4 LT |
60 | /* |
| 61 | * SDRAM configuration registers. | |
| 62 | */ | |
| 6a92e198 GU |
63 | #define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */ |
| 64 | #define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */ | |
| 65 | #define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */ | |
| 66 | #define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */ | |
| 67 | #define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */ | |
| 1da177e4 | 68 | |
| babc08b7 GU |
69 | /* |
| 70 | * DMA unit base addresses. | |
| 71 | */ | |
| 72 | #define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100) | |
| 73 | #define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140) | |
| 74 | #define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180) | |
| 75 | #define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0) | |
| 76 | ||
| 57015421 GU |
77 | /* |
| 78 | * UART module. | |
| 79 | */ | |
| f8bb5327 GU |
80 | #define MCFUART_BASE0 (MCF_IPSBAR + 0x00000200) |
| 81 | #define MCFUART_BASE1 (MCF_IPSBAR + 0x00000240) | |
| 82 | #define MCFUART_BASE2 (MCF_IPSBAR + 0x00000280) | |
| a0ba4332 GU |
83 | |
| 84 | /* | |
| 85 | * FEC ethernet module. | |
| 86 | */ | |
| 4f8f9fb8 GU |
87 | #define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000) |
| 88 | #define MCFFEC_SIZE0 0x800 | |
| 57015421 | 89 | |
| 3b2039b2 GU |
90 | /* |
| 91 | * QSPI module. | |
| 92 | */ | |
| f75b0d07 | 93 | #define MCFQSPI_BASE (MCF_IPSBAR + 0x340) |
| 3b2039b2 GU |
94 | #define MCFQSPI_SIZE 0x40 |
| 95 | ||
| 96 | #define MCFQSPI_CS0 147 | |
| 97 | #define MCFQSPI_CS1 148 | |
| 98 | #define MCFQSPI_CS2 149 | |
| 99 | #define MCFQSPI_CS3 150 | |
| 100 | ||
| 6da6e63c | 101 | /* |
| 102 | * GPIO registers | |
| 103 | */ | |
| c222f5f4 GU |
104 | #define MCFGPIO_PODR_A (MCF_IPSBAR + 0x00100000) |
| 105 | #define MCFGPIO_PODR_B (MCF_IPSBAR + 0x00100001) | |
| 106 | #define MCFGPIO_PODR_C (MCF_IPSBAR + 0x00100002) | |
| 107 | #define MCFGPIO_PODR_D (MCF_IPSBAR + 0x00100003) | |
| 108 | #define MCFGPIO_PODR_E (MCF_IPSBAR + 0x00100004) | |
| 109 | #define MCFGPIO_PODR_F (MCF_IPSBAR + 0x00100005) | |
| 110 | #define MCFGPIO_PODR_G (MCF_IPSBAR + 0x00100006) | |
| 111 | #define MCFGPIO_PODR_H (MCF_IPSBAR + 0x00100007) | |
| 112 | #define MCFGPIO_PODR_J (MCF_IPSBAR + 0x00100008) | |
| 113 | #define MCFGPIO_PODR_DD (MCF_IPSBAR + 0x00100009) | |
| 114 | #define MCFGPIO_PODR_EH (MCF_IPSBAR + 0x0010000A) | |
| 115 | #define MCFGPIO_PODR_EL (MCF_IPSBAR + 0x0010000B) | |
| 116 | #define MCFGPIO_PODR_AS (MCF_IPSBAR + 0x0010000C) | |
| 117 | #define MCFGPIO_PODR_QS (MCF_IPSBAR + 0x0010000D) | |
| 118 | #define MCFGPIO_PODR_SD (MCF_IPSBAR + 0x0010000E) | |
| 119 | #define MCFGPIO_PODR_TC (MCF_IPSBAR + 0x0010000F) | |
| 120 | #define MCFGPIO_PODR_TD (MCF_IPSBAR + 0x00100010) | |
| 121 | #define MCFGPIO_PODR_UA (MCF_IPSBAR + 0x00100011) | |
| 122 | ||
| 123 | #define MCFGPIO_PDDR_A (MCF_IPSBAR + 0x00100014) | |
| 124 | #define MCFGPIO_PDDR_B (MCF_IPSBAR + 0x00100015) | |
| 125 | #define MCFGPIO_PDDR_C (MCF_IPSBAR + 0x00100016) | |
| 126 | #define MCFGPIO_PDDR_D (MCF_IPSBAR + 0x00100017) | |
| 127 | #define MCFGPIO_PDDR_E (MCF_IPSBAR + 0x00100018) | |
| 128 | #define MCFGPIO_PDDR_F (MCF_IPSBAR + 0x00100019) | |
| 129 | #define MCFGPIO_PDDR_G (MCF_IPSBAR + 0x0010001A) | |
| 130 | #define MCFGPIO_PDDR_H (MCF_IPSBAR + 0x0010001B) | |
| 131 | #define MCFGPIO_PDDR_J (MCF_IPSBAR + 0x0010001C) | |
| 132 | #define MCFGPIO_PDDR_DD (MCF_IPSBAR + 0x0010001D) | |
| 133 | #define MCFGPIO_PDDR_EH (MCF_IPSBAR + 0x0010001E) | |
| 134 | #define MCFGPIO_PDDR_EL (MCF_IPSBAR + 0x0010001F) | |
| 135 | #define MCFGPIO_PDDR_AS (MCF_IPSBAR + 0x00100020) | |
| 136 | #define MCFGPIO_PDDR_QS (MCF_IPSBAR + 0x00100021) | |
| 137 | #define MCFGPIO_PDDR_SD (MCF_IPSBAR + 0x00100022) | |
| 138 | #define MCFGPIO_PDDR_TC (MCF_IPSBAR + 0x00100023) | |
| 139 | #define MCFGPIO_PDDR_TD (MCF_IPSBAR + 0x00100024) | |
| 140 | #define MCFGPIO_PDDR_UA (MCF_IPSBAR + 0x00100025) | |
| 141 | ||
| 142 | #define MCFGPIO_PPDSDR_A (MCF_IPSBAR + 0x00100028) | |
| 143 | #define MCFGPIO_PPDSDR_B (MCF_IPSBAR + 0x00100029) | |
| 144 | #define MCFGPIO_PPDSDR_C (MCF_IPSBAR + 0x0010002A) | |
| 145 | #define MCFGPIO_PPDSDR_D (MCF_IPSBAR + 0x0010002B) | |
| 146 | #define MCFGPIO_PPDSDR_E (MCF_IPSBAR + 0x0010002C) | |
| 147 | #define MCFGPIO_PPDSDR_F (MCF_IPSBAR + 0x0010002D) | |
| 148 | #define MCFGPIO_PPDSDR_G (MCF_IPSBAR + 0x0010002E) | |
| 149 | #define MCFGPIO_PPDSDR_H (MCF_IPSBAR + 0x0010002F) | |
| 150 | #define MCFGPIO_PPDSDR_J (MCF_IPSBAR + 0x00100030) | |
| 151 | #define MCFGPIO_PPDSDR_DD (MCF_IPSBAR + 0x00100031) | |
| 152 | #define MCFGPIO_PPDSDR_EH (MCF_IPSBAR + 0x00100032) | |
| 153 | #define MCFGPIO_PPDSDR_EL (MCF_IPSBAR + 0x00100033) | |
| 154 | #define MCFGPIO_PPDSDR_AS (MCF_IPSBAR + 0x00100034) | |
| 155 | #define MCFGPIO_PPDSDR_QS (MCF_IPSBAR + 0x00100035) | |
| 156 | #define MCFGPIO_PPDSDR_SD (MCF_IPSBAR + 0x00100036) | |
| 157 | #define MCFGPIO_PPDSDR_TC (MCF_IPSBAR + 0x00100037) | |
| 158 | #define MCFGPIO_PPDSDR_TD (MCF_IPSBAR + 0x00100038) | |
| 159 | #define MCFGPIO_PPDSDR_UA (MCF_IPSBAR + 0x00100039) | |
| 160 | ||
| 161 | #define MCFGPIO_PCLRR_A (MCF_IPSBAR + 0x0010003C) | |
| 162 | #define MCFGPIO_PCLRR_B (MCF_IPSBAR + 0x0010003D) | |
| 163 | #define MCFGPIO_PCLRR_C (MCF_IPSBAR + 0x0010003E) | |
| 164 | #define MCFGPIO_PCLRR_D (MCF_IPSBAR + 0x0010003F) | |
| 165 | #define MCFGPIO_PCLRR_E (MCF_IPSBAR + 0x00100040) | |
| 166 | #define MCFGPIO_PCLRR_F (MCF_IPSBAR + 0x00100041) | |
| 167 | #define MCFGPIO_PCLRR_G (MCF_IPSBAR + 0x00100042) | |
| 168 | #define MCFGPIO_PCLRR_H (MCF_IPSBAR + 0x00100043) | |
| 169 | #define MCFGPIO_PCLRR_J (MCF_IPSBAR + 0x00100044) | |
| 170 | #define MCFGPIO_PCLRR_DD (MCF_IPSBAR + 0x00100045) | |
| 171 | #define MCFGPIO_PCLRR_EH (MCF_IPSBAR + 0x00100046) | |
| 172 | #define MCFGPIO_PCLRR_EL (MCF_IPSBAR + 0x00100047) | |
| 173 | #define MCFGPIO_PCLRR_AS (MCF_IPSBAR + 0x00100048) | |
| 174 | #define MCFGPIO_PCLRR_QS (MCF_IPSBAR + 0x00100049) | |
| 175 | #define MCFGPIO_PCLRR_SD (MCF_IPSBAR + 0x0010004A) | |
| 176 | #define MCFGPIO_PCLRR_TC (MCF_IPSBAR + 0x0010004B) | |
| 177 | #define MCFGPIO_PCLRR_TD (MCF_IPSBAR + 0x0010004C) | |
| 178 | #define MCFGPIO_PCLRR_UA (MCF_IPSBAR + 0x0010004D) | |
| 6da6e63c | 179 | |
| 180 | #define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050) | |
| 181 | #define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051) | |
| 182 | #define MCFGPIO_PEPAR (MCF_IPSBAR + 0x00100052) | |
| 183 | #define MCFGPIO_PJPAR (MCF_IPSBAR + 0x00100054) | |
| 184 | #define MCFGPIO_PSDPAR (MCF_IPSBAR + 0x00100055) | |
| 185 | #define MCFGPIO_PASPAR (MCF_IPSBAR + 0x00100056) | |
| 186 | #define MCFGPIO_PEHLPAR (MCF_IPSBAR + 0x00100058) | |
| 187 | #define MCFGPIO_PQSPAR (MCF_IPSBAR + 0x00100059) | |
| 188 | #define MCFGPIO_PTCPAR (MCF_IPSBAR + 0x0010005A) | |
| 189 | #define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B) | |
| 190 | #define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C) | |
| 191 | ||
| f317c71a GU |
192 | /* |
| 193 | * PIT timer base addresses. | |
| 194 | */ | |
| 195 | #define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000) | |
| 196 | #define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000) | |
| 197 | #define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000) | |
| 198 | #define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000) | |
| 199 | ||
| 6da6e63c | 200 | /* |
| 201 | * Edge Port registers | |
| 202 | */ | |
| 203 | #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000) | |
| 204 | #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x00130002) | |
| 205 | #define MCFEPORT_EPIER (MCF_IPSBAR + 0x00130003) | |
| 206 | #define MCFEPORT_EPDR (MCF_IPSBAR + 0x00130004) | |
| 207 | #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x00130005) | |
| 208 | #define MCFEPORT_EPFR (MCF_IPSBAR + 0x00130006) | |
| 209 | ||
| 210 | /* | |
| 211 | * Queued ADC registers | |
| 212 | */ | |
| 213 | #define MCFQADC_PORTQA (MCF_IPSBAR + 0x00190006) | |
| 214 | #define MCFQADC_PORTQB (MCF_IPSBAR + 0x00190007) | |
| 215 | #define MCFQADC_DDRQA (MCF_IPSBAR + 0x00190008) | |
| 216 | #define MCFQADC_DDRQB (MCF_IPSBAR + 0x00190009) | |
| 217 | ||
| 218 | /* | |
| 219 | * General Purpose Timers registers | |
| 220 | */ | |
| 221 | #define MCFGPTA_GPTPORT (MCF_IPSBAR + 0x001A001D) | |
| 222 | #define MCFGPTA_GPTDDR (MCF_IPSBAR + 0x001A001E) | |
| 223 | #define MCFGPTB_GPTPORT (MCF_IPSBAR + 0x001B001D) | |
| 224 | #define MCFGPTB_GPTDDR (MCF_IPSBAR + 0x001B001E) | |
| 225 | /* | |
| 226 | * | |
| 227 | * definitions for generic gpio support | |
| 228 | * | |
| 229 | */ | |
| c222f5f4 GU |
230 | #define MCFGPIO_PODR MCFGPIO_PODR_A /* port output data */ |
| 231 | #define MCFGPIO_PDDR MCFGPIO_PDDR_A /* port data direction */ | |
| 232 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_A/* port pin data */ | |
| 233 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_A/* set output */ | |
| 234 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_A /* clr output */ | |
| 6da6e63c | 235 | |
| 236 | #define MCFGPIO_IRQ_MAX 8 | |
| 237 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE | |
| 238 | #define MCFGPIO_PIN_MAX 180 | |
| 239 | ||
| dd65b1de GU |
240 | /* |
| 241 | * Reset Control Unit (relative to IPSBAR). | |
| 242 | */ | |
| 645e5333 GU |
243 | #define MCF_RCR (MCF_IPSBAR + 0x110000) |
| 244 | #define MCF_RSR (MCF_IPSBAR + 0x110001) | |
| dd65b1de GU |
245 | |
| 246 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ | |
| 247 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ | |
| 7ce4d425 | 248 | |
| 2d24b532 SK |
249 | /* |
| 250 | * I2C module | |
| 251 | */ | |
| 252 | #define MCFI2C_BASE0 (MCF_IPSBAR + 0x300) | |
| 253 | #define MCFI2C_SIZE0 0x40 | |
| 254 | ||
| 8a415c4b | 255 | /****************************************************************************/ |
| 1da177e4 | 256 | #endif /* m528xsim_h */ |