[thirdparty/kernel/linux.git] / arch / m68k / include / asm / m5407sim.h

/* SPDX-License-Identifier: GPL-2.0 */
/****************************************************************************/

/*
 *	m5407sim.h -- ColdFire 5407 System Integration Module support.
 *
 *	(C) Copyright 2000,  Lineo (www.lineo.com)
 *	(C) Copyright 1999,  Moreton Bay Ventures Pty Ltd.
 *
 *      Modified by David W. Miller for the MCF5307 Eval Board.
 */

/****************************************************************************/
#ifndef	m5407sim_h
#define	m5407sim_h
/****************************************************************************/

#define	CPU_NAME		"COLDFIRE(m5407)"
#define	CPU_INSTR_PER_JIFFY	3
#define	MCF_BUSCLK		(MCF_CLK / 2)

#include <asm/m54xxacr.h>

/*
 *	Define the 5407 SIM register set addresses.
 */
#define	MCFSIM_RSR		(MCF_MBAR + 0x00)	/* Reset Status */
#define	MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
#define	MCFSIM_SWIVR		(MCF_MBAR + 0x02)	/* SW Watchdog intr */
#define	MCFSIM_SWSR		(MCF_MBAR + 0x03)	/* SW Watchdog service*/
#define	MCFSIM_PAR		(MCF_MBAR + 0x04)	/* Pin Assignment */
#define	MCFSIM_IRQPAR		(MCF_MBAR + 0x06)	/* Intr Assignment */
#define	MCFSIM_PLLCR		(MCF_MBAR + 0x08)	/* PLL Ctrl */
#define	MCFSIM_MPARK		(MCF_MBAR + 0x0C)	/* BUS Master Ctrl */
#define	MCFSIM_IPR		(MCF_MBAR + 0x40)	/* Interrupt Pending */
#define	MCFSIM_IMR		(MCF_MBAR + 0x44)	/* Interrupt Mask */
#define	MCFSIM_AVR		(MCF_MBAR + 0x4b)	/* Autovector Ctrl */
#define	MCFSIM_ICR0		(MCF_MBAR + 0x4c)	/* Intr Ctrl reg 0 */
#define	MCFSIM_ICR1		(MCF_MBAR + 0x4d)	/* Intr Ctrl reg 1 */
#define	MCFSIM_ICR2		(MCF_MBAR + 0x4e)	/* Intr Ctrl reg 2 */
#define	MCFSIM_ICR3		(MCF_MBAR + 0x4f)	/* Intr Ctrl reg 3 */
#define	MCFSIM_ICR4		(MCF_MBAR + 0x50)	/* Intr Ctrl reg 4 */
#define	MCFSIM_ICR5		(MCF_MBAR + 0x51)	/* Intr Ctrl reg 5 */
#define	MCFSIM_ICR6		(MCF_MBAR + 0x52)	/* Intr Ctrl reg 6 */
#define	MCFSIM_ICR7		(MCF_MBAR + 0x53)	/* Intr Ctrl reg 7 */
#define	MCFSIM_ICR8		(MCF_MBAR + 0x54)	/* Intr Ctrl reg 8 */
#define	MCFSIM_ICR9		(MCF_MBAR + 0x55)	/* Intr Ctrl reg 9 */
#define	MCFSIM_ICR10		(MCF_MBAR + 0x56)	/* Intr Ctrl reg 10 */
#define	MCFSIM_ICR11		(MCF_MBAR + 0x57)	/* Intr Ctrl reg 11 */

#define MCFSIM_CSAR0		(MCF_MBAR + 0x80)	/* CS 0 Address reg */
#define MCFSIM_CSMR0		(MCF_MBAR + 0x84)	/* CS 0 Mask reg */
#define MCFSIM_CSCR0		(MCF_MBAR + 0x8a)	/* CS 0 Control reg */
#define MCFSIM_CSAR1		(MCF_MBAR + 0x8c)	/* CS 1 Address reg */
#define MCFSIM_CSMR1		(MCF_MBAR + 0x90)	/* CS 1 Mask reg */
#define MCFSIM_CSCR1		(MCF_MBAR + 0x96)	/* CS 1 Control reg */

#define MCFSIM_CSAR2		(MCF_MBAR + 0x98)	/* CS 2 Address reg */
#define MCFSIM_CSMR2		(MCF_MBAR + 0x9c)	/* CS 2 Mask reg */
#define MCFSIM_CSCR2		(MCF_MBAR + 0xa2)	/* CS 2 Control reg */
#define MCFSIM_CSAR3		(MCF_MBAR + 0xa4)	/* CS 3 Address reg */
#define MCFSIM_CSMR3		(MCF_MBAR + 0xa8)	/* CS 3 Mask reg */
#define MCFSIM_CSCR3		(MCF_MBAR + 0xae)	/* CS 3 Control reg */
#define MCFSIM_CSAR4		(MCF_MBAR + 0xb0)	/* CS 4 Address reg */
#define MCFSIM_CSMR4		(MCF_MBAR + 0xb4)	/* CS 4 Mask reg */
#define MCFSIM_CSCR4		(MCF_MBAR + 0xba)	/* CS 4 Control reg */
#define MCFSIM_CSAR5		(MCF_MBAR + 0xbc)	/* CS 5 Address reg */
#define MCFSIM_CSMR5		(MCF_MBAR + 0xc0)	/* CS 5 Mask reg */
#define MCFSIM_CSCR5		(MCF_MBAR + 0xc6)	/* CS 5 Control reg */
#define MCFSIM_CSAR6		(MCF_MBAR + 0xc8)	/* CS 6 Address reg */
#define MCFSIM_CSMR6		(MCF_MBAR + 0xcc)	/* CS 6 Mask reg */
#define MCFSIM_CSCR6		(MCF_MBAR + 0xd2)	/* CS 6 Control reg */
#define MCFSIM_CSAR7		(MCF_MBAR + 0xd4)	/* CS 7 Address reg */
#define MCFSIM_CSMR7		(MCF_MBAR + 0xd8)	/* CS 7 Mask reg */
#define MCFSIM_CSCR7		(MCF_MBAR + 0xde)	/* CS 7 Control reg */

#define MCFSIM_DCR		(MCF_MBAR + 0x100)	/* DRAM Control */
#define MCFSIM_DACR0		(MCF_MBAR + 0x108)	/* DRAM 0 Addr/Ctrl */
#define MCFSIM_DMR0		(MCF_MBAR + 0x10c)	/* DRAM 0 Mask */
#define MCFSIM_DACR1		(MCF_MBAR + 0x110)	/* DRAM 1 Addr/Ctrl */
#define MCFSIM_DMR1		(MCF_MBAR + 0x114)	/* DRAM 1 Mask */

/*
 *	Timer module.
 */
#define MCFTIMER_BASE1		(MCF_MBAR + 0x140)	/* Base of TIMER1 */
#define MCFTIMER_BASE2		(MCF_MBAR + 0x180)	/* Base of TIMER2 */

#define MCFUART_BASE0		(MCF_MBAR + 0x1c0)	/* Base address UART0 */
#define MCFUART_BASE1		(MCF_MBAR + 0x200)	/* Base address UART1 */

#define	MCFSIM_PADDR		(MCF_MBAR + 0x244)
#define	MCFSIM_PADAT		(MCF_MBAR + 0x248)

/*
 *	DMA unit base addresses.
 */
#define MCFDMA_BASE0		(MCF_MBAR + 0x300)	/* Base address DMA 0 */
#define MCFDMA_BASE1		(MCF_MBAR + 0x340)	/* Base address DMA 1 */
#define MCFDMA_BASE2		(MCF_MBAR + 0x380)	/* Base address DMA 2 */
#define MCFDMA_BASE3		(MCF_MBAR + 0x3C0)	/* Base address DMA 3 */

/*
 * Generic GPIO support
 */
#define MCFGPIO_PIN_MAX		16
#define MCFGPIO_IRQ_MAX		-1
#define MCFGPIO_IRQ_VECBASE	-1

/*
 *	Some symbol defines for the above...
 */
#define	MCFSIM_SWDICR		MCFSIM_ICR0	/* Watchdog timer ICR */
#define	MCFSIM_TIMER1ICR	MCFSIM_ICR1	/* Timer 1 ICR */
#define	MCFSIM_TIMER2ICR	MCFSIM_ICR2	/* Timer 2 ICR */
#define	MCFSIM_I2CICR		MCFSIM_ICR3	/* I2C ICR */
#define	MCFSIM_UART1ICR		MCFSIM_ICR4	/* UART 1 ICR */
#define	MCFSIM_UART2ICR		MCFSIM_ICR5	/* UART 2 ICR */
#define	MCFSIM_DMA0ICR		MCFSIM_ICR6	/* DMA 0 ICR */
#define	MCFSIM_DMA1ICR		MCFSIM_ICR7	/* DMA 1 ICR */
#define	MCFSIM_DMA2ICR		MCFSIM_ICR8	/* DMA 2 ICR */
#define	MCFSIM_DMA3ICR		MCFSIM_ICR9	/* DMA 3 ICR */

/*
 *	Some symbol defines for the Parallel Port Pin Assignment Register
 */
#define MCFSIM_PAR_DREQ0        0x40            /* Set to select DREQ0 input */
                                                /* Clear to select par I/O */
#define MCFSIM_PAR_DREQ1        0x20            /* Select DREQ1 input */
                                                /* Clear to select par I/O */

/*
 *       Defines for the IRQPAR Register
 */
#define IRQ5_LEVEL4		0x80
#define IRQ3_LEVEL6		0x40
#define IRQ1_LEVEL2		0x20

/*
 *	Define system peripheral IRQ usage.
 */
#define	MCF_IRQ_I2C0		29		/* I2C, Level 5 */
#define	MCF_IRQ_TIMER		30		/* Timer0, Level 6 */
#define	MCF_IRQ_PROFILER	31		/* Timer1, Level 7 */
#define	MCF_IRQ_UART0		73		/* UART0 */
#define	MCF_IRQ_UART1		74		/* UART1 */

/*
 * I2C module
 */
#define	MCFI2C_BASE0		(MCF_MBAR + 0x280)
#define	MCFI2C_SIZE0		0x40

/****************************************************************************/
#endif	/* m5407sim_h */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1da177e4 LT	2	/****************************************************************************/
	3
	4	/*
	5	* m5407sim.h -- ColdFire 5407 System Integration Module support.
	6	*
	7	* (C) Copyright 2000, Lineo (www.lineo.com)
	8	* (C) Copyright 1999, Moreton Bay Ventures Pty Ltd.
	9	*
	10	* Modified by David W. Miller for the MCF5307 Eval Board.
	11	*/
	12
	13	/****************************************************************************/
	14	#ifndef m5407sim_h
	15	#define m5407sim_h
	16	/****************************************************************************/
	17
733f31b7 GU	18	#define CPU_NAME "COLDFIRE(m5407)"
733f31b7 GU	19	#define CPU_INSTR_PER_JIFFY 3
ce3de78a	20	#define MCF_BUSCLK (MCF_CLK / 2)
7fc82b65	21
3d461401 GU	22	#include <asm/m54xxacr.h>
3d461401 GU	23
1da177e4 LT	24	/*
	25	* Define the 5407 SIM register set addresses.
	26	*/
e1e362dc GU	27	#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
e1e362dc GU	28	#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
660b73e3 GU	29	#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
660b73e3 GU	30	#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
a45f56b2	31	#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
35142b91 GU	32	#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
	33	#define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */
	34	#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
6a3a786d GU	35	#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
	36	#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
	37	#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
c986a3d5 GU	38	#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
	39	#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
	40	#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
	41	#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
	42	#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
	43	#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
	44	#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
	45	#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
	46	#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
	47	#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
	48	#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
	49	#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
1da177e4	50
1419ea3b GU	51	#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
	52	#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
	53	#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
	54	#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
	55	#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
	56	#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
1da177e4	57
1419ea3b GU	58	#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
	59	#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
	60	#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
	61	#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
	62	#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
	63	#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
	64	#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
	65	#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
	66	#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
	67	#define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
	68	#define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
	69	#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
	70	#define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
	71	#define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
	72	#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
	73	#define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
	74	#define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
	75	#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
1da177e4	76
6a92e198 GU	77	#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
	78	#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
	79	#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
	80	#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
	81	#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
1da177e4	82
58f0ac98 GU	83	/*
	84	* Timer module.
	85	*/
	86	#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
	87	#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
	88
69d23b61 GU	89	#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
69d23b61 GU	90	#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
57015421	91
dca7cf33	92	#define MCFSIM_PADDR (MCF_MBAR + 0x244)
dca7cf33	93	#define MCFSIM_PADAT (MCF_MBAR + 0x248)
1da177e4	94
babc08b7 GU	95	/*
	96	* DMA unit base addresses.
	97	*/
	98	#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
	99	#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
	100	#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
	101	#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
	102
dca7cf33	103	/*
	104	* Generic GPIO support
	105	*/
a2551728 GU	106	#define MCFGPIO_PIN_MAX 16
	107	#define MCFGPIO_IRQ_MAX -1
	108	#define MCFGPIO_IRQ_VECBASE -1
1da177e4 LT	109
	110	/*
	111	* Some symbol defines for the above...
	112	*/
	113	#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
	114	#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
	115	#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
2d24b532	116	#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
1da177e4 LT	117	#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
	118	#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
	119	#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
	120	#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
	121	#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
	122	#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
	123
1da177e4 LT	124	/*
	125	* Some symbol defines for the Parallel Port Pin Assignment Register
	126	*/
	127	#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */
	128	/* Clear to select par I/O */
	129	#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */
	130	/* Clear to select par I/O */
	131
	132	/*
	133	* Defines for the IRQPAR Register
	134	*/
a2551728 GU	135	#define IRQ5_LEVEL4 0x80
	136	#define IRQ3_LEVEL6 0x40
	137	#define IRQ1_LEVEL2 0x20
1da177e4	138
04b75b10 GU	139	/*
	140	* Define system peripheral IRQ usage.
	141	*/
2d24b532	142	#define MCF_IRQ_I2C0 29 /* I2C, Level 5 */
04b75b10 GU	143	#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
04b75b10 GU	144	#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
69d23b61 GU	145	#define MCF_IRQ_UART0 73 /* UART0 */
69d23b61 GU	146	#define MCF_IRQ_UART1 74 /* UART1 */
1da177e4	147
2d24b532 SK	148	/*
	149	* I2C module
	150	*/
	151	#define MCFI2C_BASE0 (MCF_MBAR + 0x280)
	152	#define MCFI2C_SIZE0 0x40
	153
1da177e4 LT	154	/****************************************************************************/
1da177e4 LT	155	#endif /* m5407sim_h */