[thirdparty/u-boot.git] / arch / microblaze / cpu / start.S

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2007 Michal Simek
 * (C) Copyright 2004 Atmark Techno, Inc.
 *
 * Michal  SIMEK <monstr@monstr.eu>
 * Yasushi SHOJI <yashi@atmark-techno.com>
 */

#include <asm-offsets.h>
#include <config.h>

#define SYM_ADDR(reg, reg_add, symbol)	\
	mfs	r20, rpc; \
	addik	r20, r20, _GLOBAL_OFFSET_TABLE_ + 8; \
	lwi	reg, r20, symbol@GOT; \
	addk	reg, reg reg_add;

	.text
	.global _start
_start:
	mts	rmsr, r0	/* disable cache */
	mfs	r20, rpc
	addi	r20, r20, -4

	mts	rslr, r0
	mts	rshr, r20

#if defined(CONFIG_SPL_BUILD)
	addi	r1, r0, CONFIG_SPL_STACK
#else
	add	r1, r0, r20
	bri	1f

	/* Force alignment for easier ASM code below */
#define ALIGNMENT_ADDR	0x20
	.align	4
uboot_dyn_start:
	.word	__rel_dyn_start

uboot_dyn_end:
	.word	__rel_dyn_end

uboot_sym_start:
	.word	__dyn_sym_start
1:

	addi	r5, r20, 0
	add	r6, r0, r0

	lwi	r7, r20, ALIGNMENT_ADDR
	addi	r7, r7, -CONFIG_TEXT_BASE
	add	r7, r7, r5
	lwi	r8, r20, ALIGNMENT_ADDR + 0x4
	addi	r8, r8, -CONFIG_TEXT_BASE
	add	r8, r8, r5
	lwi	r9, r20, ALIGNMENT_ADDR + 0x8
	addi	r9, r9, -CONFIG_TEXT_BASE
	add	r9, r9, r5
	addi	r10, r0, CONFIG_TEXT_BASE

	brlid	r15, mb_fix_rela
	nop
#endif

	addi	r1, r1, -4	/* Decrement SP to top of memory */

	/* Call board_init_f_alloc_reserve with the current stack pointer as
	 * parameter. */
	add	r5, r0, r1
	brlid	r15, board_init_f_alloc_reserve
	nop

	/* board_init_f_alloc_reserve returns a pointer to the allocated area
	 * in r3. Set the new stack pointer below this area. */
	add	r1, r0, r3
	mts	rshr, r1
	addi	r1, r1, -4

	/* Call board_init_f_init_reserve with the address returned by
	 * board_init_f_alloc_reserve as parameter. */
	add	r5, r0, r3
	brlid	r15, board_init_f_init_reserve
	nop

#if !defined(CONFIG_SPL_BUILD)
	/* Setup vectors with pre-relocation symbols */
	or	r5, r0, r0
	brlid	r15, __setup_exceptions
	nop
#endif

	/*
	 * Initialize global data cpuinfo with default values (cache
	 * size, cache line size, etc).
	 */
	brlid	r15, microblaze_early_cpuinfo_init
	nop

	/* Flush cache before enable cache */
	brlid	r15, flush_cache_all
	nop

	/* enable instruction and data cache */
	mfs	r12, rmsr
	ori	r12, r12, 0x1a0
	mts	rmsr, r12

clear_bss:
	/* clear BSS segments */
	SYM_ADDR(r5, r0, __bss_start)
	SYM_ADDR(r4, r0, __bss_end)
	cmp	r6, r5, r4
	beqi	r6, 3f
2:
	swi     r0, r5, 0 /* write zero to loc */
	addi    r5, r5, 4 /* increment to next loc */
	cmp     r6, r5, r4 /* check if we have reach the end */
	bnei    r6, 2b
3:	/* jumping to board_init */
#ifdef CONFIG_DEBUG_UART
	brlid	r15, debug_uart_init
	nop
#endif
#ifndef CONFIG_SPL_BUILD
	or	r5, r0, r0	/* flags - empty */
	bri	board_init_f
#else
	bri	board_init_r
#endif
1:	bri	1b

#ifndef CONFIG_SPL_BUILD
	.text
	.ent	__setup_exceptions
	.align	2
/*
 * Set up reset, interrupt, user exception and hardware exception vectors.
 *
 * Parameters:
 * r5 - relocation offset (zero when setting up vectors before
 *      relocation, and gd->reloc_off when setting up vectors after
 *      relocation)
 *    - the relocation offset is added to the _exception_handler,
 *      _interrupt_handler and _hw_exception_handler symbols to reflect the
 *      post-relocation memory addresses
 *
 * Reserve registers:
 * r10: Stores little/big endian offset for vectors
 * r2: Stores imm opcode
 * r3: Stores brai opcode
 * r4: Stores the vector base address
 */
__setup_exceptions:
	addik	r1, r1, -32
	swi	r2, r1, 4
	swi	r3, r1, 8
	swi	r4, r1, 12
	swi	r6, r1, 16
	swi	r7, r1, 20
	swi	r8, r1, 24
	swi	r10, r1, 28

	/* Find-out if u-boot is running on BIG/LITTLE endian platform
	 * There are some steps which is necessary to keep in mind:
	 * 1. Setup offset value to r6
	 * 2. Store word offset value to address 0x0
	 * 3. Load just byte from address 0x0
	 * 4a) LITTLE endian - r10 contains 0x2 because it is the smallest
	 *     value that's why is on address 0x0
	 * 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
	 */
	addik	r6, r0, 0x2 /* BIG/LITTLE endian offset */
	sw	r6, r1, r0
	lbu	r10, r1, r0

	/* add opcode instruction for 32bit jump - 2 instruction imm & brai */
	addi	r2, r0, 0xb0000000	/* hex b000 opcode imm */
	addi	r3, r0, 0xb8080000	/* hew b808 opcode brai */

	/* Store the vector base address in r4 */
	addi	r4, r0, CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR

	/* reset address */
	swi	r2, r4, 0x0	/* reset address - imm opcode */
	swi	r3, r4, 0x4	/* reset address - brai opcode */

	SYM_ADDR(r6, r0, _start)
	/* Intentionally keep reset vector back to origin u-boot location */
	sw	r6, r1, r0
	lhu	r7, r1, r10
	rsubi	r8, r10, 0x2
	sh	r7, r4, r8
	rsubi	r8, r10, 0x6
	sh	r6, r4, r8

#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
	/* user_vector_exception */
	swi	r2, r4, 0x8	/* user vector exception - imm opcode */
	swi	r3, r4, 0xC	/* user vector exception - brai opcode */

	SYM_ADDR(r6, r5, _exception_handler)
	sw	r6, r1, r0
	/*
	 * BIG ENDIAN memory map for user exception
	 * 0x8: 0xB000XXXX
	 * 0xC: 0xB808XXXX
	 *
	 * then it is necessary to count address for storing the most significant
	 * 16bits from _exception_handler address and copy it to
	 * 0xa address. Big endian use offset in r10=0 that's why is it just
	 * 0xa address. The same is done for the least significant 16 bits
	 * for 0xe address.
	 *
	 * LITTLE ENDIAN memory map for user exception
	 * 0x8: 0xXXXX00B0
	 * 0xC: 0xXXXX08B8
	 *
	 * Offset is for little endian setup to 0x2. rsubi instruction decrease
	 * address value to ensure that points to proper place which is
	 * 0x8 for the most significant 16 bits and
	 * 0xC for the least significant 16 bits
	 */
	lhu	r7, r1, r10
	rsubi	r8, r10, 0xa
	sh	r7, r4, r8
	rsubi	r8, r10, 0xe
	sh	r6, r4, r8
#endif

	/* interrupt_handler */
	swi	r2, r4, 0x10	/* interrupt - imm opcode */
	swi	r3, r4, 0x14	/* interrupt - brai opcode */

	SYM_ADDR(r6, r5, _interrupt_handler)
	sw	r6, r1, r0
	lhu	r7, r1, r10
	rsubi	r8, r10, 0x12
	sh	r7, r4, r8
	rsubi	r8, r10, 0x16
	sh	r6, r4, r8

	/* hardware exception */
	swi	r2, r4, 0x20	/* hardware exception - imm opcode */
	swi	r3, r4, 0x24	/* hardware exception - brai opcode */

	SYM_ADDR(r6, r5, _hw_exception_handler)
	sw	r6, r1, r0
	lhu	r7, r1, r10
	rsubi	r8, r10, 0x22
	sh	r7, r4, r8
	rsubi	r8, r10, 0x26
	sh	r6, r4, r8

	lwi	r10, r1, 28
	lwi	r8, r1, 24
	lwi	r7, r1, 20
	lwi	r6, r1, 16
	lwi	r4, r1, 12
	lwi	r3, r1, 8
	lwi	r2, r1, 4
	addik	r1, r1, 32

	rtsd	r15, 8
	or	r0, r0, r0
	.end	__setup_exceptions

/*
 * Relocate u-boot
 */
	.text
	.global	relocate_code
	.ent	relocate_code
	.align	2
relocate_code:
	/*
	 * r5 - start_addr_sp
	 * r6 - new_gd
	 * r7 - reloc_addr
	 */
	addi	r1, r5, 0 /* Start to use new SP */
	mts	rshr, r1
	addi	r31, r6, 0 /* Start to use new GD */

	/* Relocate text and data - r12 temp value */
	SYM_ADDR(r21, r0, _start)
	SYM_ADDR(r22, r0, _end) /* Include BSS too */
	addi	r22, r22, -4

	rsub	r6, r21, r22
	or	r5, r0, r0
1:	lw	r12, r21, r5 /* Load u-boot data */
	sw	r12, r7, r5 /* Write zero to loc */
	cmp	r12, r5, r6 /* Check if we have reach the end */
	bneid	r12, 1b
	addi	r5, r5, 4 /* Increment to next loc - relocate code */

	/* R23 points to the base address. */
	rsub	r23, r21, r7 /* keep - this is already here gd->reloc_off */

	/* Setup vectors with post-relocation symbols */
	add	r5, r0, r23 /* load gd->reloc_off to r5 */
	brlid	r15, __setup_exceptions
	nop

	/* reloc_offset is current location */
	SYM_ADDR(r10, r0, _start)

	/* r5 new address where I should copy code */
	add	r5, r0, r7 /* Move reloc addr to r5 */

	/* Verbose message */
	addi	r6, r0, 0

	SYM_ADDR(r7, r0, __rel_dyn_start)
	rsub	r7, r10, r7
	add	r7, r7, r5
	SYM_ADDR(r8, r0, __rel_dyn_end)
	rsub	r8, r10, r8
	add	r8, r8, r5
	SYM_ADDR(r9, r0, __dyn_sym_start)
	rsub	r9, r10, r9
	add	r9, r9, r5
	brlid	r15, mb_fix_rela
	nop
	/* end of code which does relocation */

	/* Flush caches to ensure consistency */
	brlid	r15, flush_cache_all
	nop

2:	addi	r5, r31, 0 /* gd is initialized in board_r.c */
	SYM_ADDR(r6, r0, _start)
	SYM_ADDR(r12, r23, board_init_r)
	bra	r12 /* Jump to relocated code */

	.end	relocate_code
#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
507bbe3e	2	/*
cfc67116	3	* (C) Copyright 2007 Michal Simek
507bbe3e WD	4	* (C) Copyright 2004 Atmark Techno, Inc.
507bbe3e WD	5	*
cfc67116	6	* Michal SIMEK <monstr@monstr.eu>
507bbe3e	7	* Yasushi SHOJI <yashi@atmark-techno.com>
507bbe3e WD	8	*/
507bbe3e WD	9
25ddd1fb	10	#include <asm-offsets.h>
507bbe3e WD	11	#include <config.h>
507bbe3e WD	12
d58c0074 MS	13	#define SYM_ADDR(reg, reg_add, symbol) \
	14	mfs r20, rpc; \
	15	addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8; \
	16	lwi reg, r20, symbol@GOT; \
	17	addk reg, reg reg_add;
07c052be	18
507bbe3e WD	19	.text
	20	.global _start
	21	_start:
cfc67116	22	mts rmsr, r0 /* disable cache */
b6fe10af MS	23	mfs r20, rpc
b6fe10af MS	24	addi r20, r20, -4
9d242745	25
16a18471	26	mts rslr, r0
b6fe10af	27	mts rshr, r20
f5d8b1a1	28
9d242745	29	#if defined(CONFIG_SPL_BUILD)
f113d7d3	30	addi r1, r0, CONFIG_SPL_STACK
9d242745	31	#else
b6fe10af	32	add r1, r0, r20
d58c0074 MS	33	bri 1f
	34
	35	/* Force alignment for easier ASM code below */
	36	#define ALIGNMENT_ADDR 0x20
	37	.align 4
	38	uboot_dyn_start:
	39	.word __rel_dyn_start
	40
	41	uboot_dyn_end:
	42	.word __rel_dyn_end
	43
	44	uboot_sym_start:
	45	.word __dyn_sym_start
	46	1:
	47
	48	addi r5, r20, 0
	49	add r6, r0, r0
	50
	51	lwi r7, r20, ALIGNMENT_ADDR
98463903	52	addi r7, r7, -CONFIG_TEXT_BASE
d58c0074 MS	53	add r7, r7, r5
d58c0074 MS	54	lwi r8, r20, ALIGNMENT_ADDR + 0x4
98463903	55	addi r8, r8, -CONFIG_TEXT_BASE
d58c0074 MS	56	add r8, r8, r5
d58c0074 MS	57	lwi r9, r20, ALIGNMENT_ADDR + 0x8
98463903	58	addi r9, r9, -CONFIG_TEXT_BASE
d58c0074	59	add r9, r9, r5
98463903	60	addi r10, r0, CONFIG_TEXT_BASE
d58c0074 MS	61
	62	brlid r15, mb_fix_rela
	63	nop
405e651d	64	#endif
f5d8b1a1	65
17980495	66	addi r1, r1, -4 /* Decrement SP to top of memory */
b98cba09	67
f5d8b1a1 OP	68	/* Call board_init_f_alloc_reserve with the current stack pointer as
	69	* parameter. */
	70	add r5, r0, r1
7cf236cf	71	brlid r15, board_init_f_alloc_reserve
f5d8b1a1 OP	72	nop
	73
	74	/* board_init_f_alloc_reserve returns a pointer to the allocated area
	75	* in r3. Set the new stack pointer below this area. */
	76	add r1, r0, r3
	77	mts rshr, r1
	78	addi r1, r1, -4
	79
	80	/* Call board_init_f_init_reserve with the address returned by
	81	* board_init_f_alloc_reserve as parameter. */
	82	add r5, r0, r3
7cf236cf	83	brlid r15, board_init_f_init_reserve
f5d8b1a1 OP	84	nop
	85
	86	#if !defined(CONFIG_SPL_BUILD)
627085ea OP	87	/* Setup vectors with pre-relocation symbols */
627085ea OP	88	or r5, r0, r0
7cf236cf	89	brlid r15, __setup_exceptions
627085ea	90	nop
f5d8b1a1	91	#endif
627085ea	92
95b7a8fd OP	93	/*
	94	* Initialize global data cpuinfo with default values (cache
	95	* size, cache line size, etc).
	96	*/
	97	brlid r15, microblaze_early_cpuinfo_init
	98	nop
	99
627085ea	100	/* Flush cache before enable cache */
b1951349	101	brlid r15, flush_cache_all
627085ea OP	102	nop
	103
	104	/* enable instruction and data cache */
	105	mfs r12, rmsr
	106	ori r12, r12, 0x1a0
	107	mts rmsr, r12
	108
627085ea OP	109	clear_bss:
627085ea OP	110	/* clear BSS segments */
07c052be MS	111	SYM_ADDR(r5, r0, __bss_start)
07c052be MS	112	SYM_ADDR(r4, r0, __bss_end)
627085ea OP	113	cmp r6, r5, r4
	114	beqi r6, 3f
	115	2:
	116	swi r0, r5, 0 /* write zero to loc */
	117	addi r5, r5, 4 /* increment to next loc */
	118	cmp r6, r5, r4 /* check if we have reach the end */
	119	bnei r6, 2b
	120	3: /* jumping to board_init */
	121	#ifdef CONFIG_DEBUG_UART
7cf236cf	122	brlid r15, debug_uart_init
627085ea OP	123	nop
	124	#endif
	125	#ifndef CONFIG_SPL_BUILD
	126	or r5, r0, r0 /* flags - empty */
7cf236cf	127	bri board_init_f
627085ea	128	#else
7cf236cf	129	bri board_init_r
627085ea OP	130	#endif
	131	1: bri 1b
	132
627085ea OP	133	#ifndef CONFIG_SPL_BUILD
	134	.text
	135	.ent __setup_exceptions
	136	.align 2
	137	/*
	138	* Set up reset, interrupt, user exception and hardware exception vectors.
	139	*
	140	* Parameters:
	141	* r5 - relocation offset (zero when setting up vectors before
	142	* relocation, and gd->reloc_off when setting up vectors after
	143	* relocation)
	144	* - the relocation offset is added to the _exception_handler,
	145	* _interrupt_handler and _hw_exception_handler symbols to reflect the
	146	* post-relocation memory addresses
	147	*
	148	* Reserve registers:
	149	* r10: Stores little/big endian offset for vectors
	150	* r2: Stores imm opcode
	151	* r3: Stores brai opcode
f149ee4c	152	* r4: Stores the vector base address
627085ea OP	153	*/
627085ea OP	154	__setup_exceptions:
f149ee4c	155	addik r1, r1, -32
627085ea OP	156	swi r2, r1, 4
627085ea OP	157	swi r3, r1, 8
f149ee4c OP	158	swi r4, r1, 12
	159	swi r6, r1, 16
	160	swi r7, r1, 20
	161	swi r8, r1, 24
	162	swi r10, r1, 28
627085ea	163
b98cba09 MS	164	/* Find-out if u-boot is running on BIG/LITTLE endian platform
	165	* There are some steps which is necessary to keep in mind:
	166	* 1. Setup offset value to r6
	167	* 2. Store word offset value to address 0x0
	168	* 3. Load just byte from address 0x0
	169	* 4a) LITTLE endian - r10 contains 0x2 because it is the smallest
	170	* value that's why is on address 0x0
	171	* 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
	172	*/
	173	addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
48039c33 OP	174	sw r6, r1, r0
48039c33 OP	175	lbu r10, r1, r0
b98cba09	176
86c1b2a8 MS	177	/* add opcode instruction for 32bit jump - 2 instruction imm & brai */
	178	addi r2, r0, 0xb0000000 /* hex b000 opcode imm */
	179	addi r3, r0, 0xb8080000 /* hew b808 opcode brai */
507bbe3e	180
f149ee4c OP	181	/* Store the vector base address in r4 */
	182	addi r4, r0, CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
	183
cfc67116	184	/* reset address */
f149ee4c OP	185	swi r2, r4, 0x0 /* reset address - imm opcode */
f149ee4c OP	186	swi r3, r4, 0x4 /* reset address - brai opcode */
86c1b2a8	187
07c052be	188	SYM_ADDR(r6, r0, _start)
81169ae6	189	/* Intentionally keep reset vector back to origin u-boot location */
cfc67116	190	sw r6, r1, r0
5562bcc2 MS	191	lhu r7, r1, r10
5562bcc2 MS	192	rsubi r8, r10, 0x2
f149ee4c	193	sh r7, r4, r8
5562bcc2	194	rsubi r8, r10, 0x6
f149ee4c	195	sh r6, r4, r8
cfc67116	196
83b175be	197	#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
cfc67116	198	/* user_vector_exception */
f149ee4c OP	199	swi r2, r4, 0x8 /* user vector exception - imm opcode */
f149ee4c OP	200	swi r3, r4, 0xC /* user vector exception - brai opcode */
86c1b2a8	201
07c052be	202	SYM_ADDR(r6, r5, _exception_handler)
cfc67116	203	sw r6, r1, r0
b98cba09 MS	204	/*
	205	* BIG ENDIAN memory map for user exception
	206	* 0x8: 0xB000XXXX
	207	* 0xC: 0xB808XXXX
	208	*
	209	* then it is necessary to count address for storing the most significant
071bc923	210	* 16bits from _exception_handler address and copy it to
b98cba09 MS	211	* 0xa address. Big endian use offset in r10=0 that's why is it just
	212	* 0xa address. The same is done for the least significant 16 bits
	213	* for 0xe address.
	214	*
	215	* LITTLE ENDIAN memory map for user exception
	216	* 0x8: 0xXXXX00B0
	217	* 0xC: 0xXXXX08B8
	218	*
	219	* Offset is for little endian setup to 0x2. rsubi instruction decrease
	220	* address value to ensure that points to proper place which is
	221	* 0x8 for the most significant 16 bits and
	222	* 0xC for the least significant 16 bits
	223	*/
	224	lhu r7, r1, r10
	225	rsubi r8, r10, 0xa
f149ee4c	226	sh r7, r4, r8
b98cba09	227	rsubi r8, r10, 0xe
f149ee4c	228	sh r6, r4, r8
cfc67116 MS	229	#endif
cfc67116 MS	230
cfc67116	231	/* interrupt_handler */
f149ee4c OP	232	swi r2, r4, 0x10 /* interrupt - imm opcode */
f149ee4c OP	233	swi r3, r4, 0x14 /* interrupt - brai opcode */
86c1b2a8	234
07c052be	235	SYM_ADDR(r6, r5, _interrupt_handler)
cfc67116	236	sw r6, r1, r0
b98cba09 MS	237	lhu r7, r1, r10
b98cba09 MS	238	rsubi r8, r10, 0x12
f149ee4c	239	sh r7, r4, r8
b98cba09	240	rsubi r8, r10, 0x16
f149ee4c	241	sh r6, r4, r8
507bbe3e	242
cfc67116	243	/* hardware exception */
f149ee4c OP	244	swi r2, r4, 0x20 /* hardware exception - imm opcode */
f149ee4c OP	245	swi r3, r4, 0x24 /* hardware exception - brai opcode */
86c1b2a8	246
07c052be	247	SYM_ADDR(r6, r5, _hw_exception_handler)
cfc67116	248	sw r6, r1, r0
b98cba09 MS	249	lhu r7, r1, r10
b98cba09 MS	250	rsubi r8, r10, 0x22
f149ee4c	251	sh r7, r4, r8
b98cba09	252	rsubi r8, r10, 0x26
f149ee4c	253	sh r6, r4, r8
cfc67116	254
f149ee4c OP	255	lwi r10, r1, 28
	256	lwi r8, r1, 24
	257	lwi r7, r1, 20
	258	lwi r6, r1, 16
	259	lwi r4, r1, 12
627085ea OP	260	lwi r3, r1, 8
627085ea OP	261	lwi r2, r1, 4
f149ee4c	262	addik r1, r1, 32
0643631a	263
627085ea OP	264	rtsd r15, 8
	265	or r0, r0, r0
	266	.end __setup_exceptions
0510b14b	267
e945f6dc MS	268	/*
	269	* Relocate u-boot
	270	*/
	271	.text
	272	.global relocate_code
	273	.ent relocate_code
	274	.align 2
	275	relocate_code:
	276	/*
	277	* r5 - start_addr_sp
	278	* r6 - new_gd
	279	* r7 - reloc_addr
	280	*/
	281	addi r1, r5, 0 /* Start to use new SP */
532ad5f8	282	mts rshr, r1
e945f6dc MS	283	addi r31, r6, 0 /* Start to use new GD */
e945f6dc MS	284
e945f6dc	285	/* Relocate text and data - r12 temp value */
07c052be MS	286	SYM_ADDR(r21, r0, _start)
07c052be MS	287	SYM_ADDR(r22, r0, _end) /* Include BSS too */
1918c416	288	addi r22, r22, -4
7c4dd542 MS	289
	290	rsub r6, r21, r22
	291	or r5, r0, r0
	292	1: lw r12, r21, r5 /* Load u-boot data */
3041b512	293	sw r12, r7, r5 /* Write zero to loc */
7c4dd542	294	cmp r12, r5, r6 /* Check if we have reach the end */
e945f6dc	295	bneid r12, 1b
7c4dd542	296	addi r5, r5, 4 /* Increment to next loc - relocate code */
e945f6dc	297
3ad95ed6	298	/* R23 points to the base address. */
3041b512	299	rsub r23, r21, r7 /* keep - this is already here gd->reloc_off */
e945f6dc	300
627085ea OP	301	/* Setup vectors with post-relocation symbols */
627085ea OP	302	add r5, r0, r23 /* load gd->reloc_off to r5 */
7cf236cf	303	brlid r15, __setup_exceptions
627085ea	304	nop
e945f6dc	305
d58c0074 MS	306	/* reloc_offset is current location */
	307	SYM_ADDR(r10, r0, _start)
	308
	309	/* r5 new address where I should copy code */
	310	add r5, r0, r7 /* Move reloc addr to r5 */
	311
	312	/* Verbose message */
	313	addi r6, r0, 0
	314
	315	SYM_ADDR(r7, r0, __rel_dyn_start)
	316	rsub r7, r10, r7
	317	add r7, r7, r5
	318	SYM_ADDR(r8, r0, __rel_dyn_end)
	319	rsub r8, r10, r8
	320	add r8, r8, r5
	321	SYM_ADDR(r9, r0, __dyn_sym_start)
	322	rsub r9, r10, r9
	323	add r9, r9, r5
	324	brlid r15, mb_fix_rela
627085ea	325	nop
d58c0074	326	/* end of code which does relocation */
e945f6dc MS	327
e945f6dc MS	328	/* Flush caches to ensure consistency */
b1951349	329	brlid r15, flush_cache_all
e945f6dc MS	330	nop
	331
	332	2: addi r5, r31, 0 /* gd is initialized in board_r.c */
07c052be MS	333	SYM_ADDR(r6, r0, _start)
07c052be MS	334	SYM_ADDR(r12, r23, board_init_r)
e945f6dc MS	335	bra r12 /* Jump to relocated code */
	336
	337	.end relocate_code
9d242745	338	#endif