[people/ms/u-boot.git] / arch / mips / Kconfig

menu "MIPS architecture"
	depends on MIPS

config SYS_ARCH
	default "mips"

config SYS_CPU
	default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2
	default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2

choice
	prompt "Target select"
	optional

config TARGET_QEMU_MIPS
	bool "Support qemu-mips"
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_LITTLE_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SUPPORTS_CPU_MIPS64_R1
	select SUPPORTS_CPU_MIPS64_R2

config TARGET_MALTA
	bool "Support malta"
	select DYNAMIC_IO_PORT_BASE
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_LITTLE_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SWAP_IO_SPACE
	select MIPS_L1_CACHE_SHIFT_6

config TARGET_VCT
	bool "Support vct"
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SYS_MIPS_CACHE_INIT_RAM_LOAD

config TARGET_DBAU1X00
	bool "Support dbau1x00"
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_LITTLE_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SYS_MIPS_CACHE_INIT_RAM_LOAD
	select MIPS_TUNE_4KC

config TARGET_PB1X00
	bool "Support pb1x00"
	select SUPPORTS_LITTLE_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SYS_MIPS_CACHE_INIT_RAM_LOAD
	select MIPS_TUNE_4KC

config ARCH_ATH79
	bool "Support QCA/Atheros ath79"
	select OF_CONTROL
	select DM

config MACH_PIC32
	bool "Support Microchip PIC32"
	select OF_CONTROL
	select DM

endchoice

source "board/dbau1x00/Kconfig"
source "board/imgtec/malta/Kconfig"
source "board/micronas/vct/Kconfig"
source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
source "arch/mips/mach-ath79/Kconfig"
source "arch/mips/mach-pic32/Kconfig"

if MIPS

choice
	prompt "Endianness selection"
	help
	  Some MIPS boards can be configured for either little or big endian
	  byte order. These modes require different U-Boot images. In general there
	  is one preferred byteorder for a particular system but some systems are
	  just as commonly used in the one or the other endianness.

config SYS_BIG_ENDIAN
	bool "Big endian"
	depends on SUPPORTS_BIG_ENDIAN

config SYS_LITTLE_ENDIAN
	bool "Little endian"
	depends on SUPPORTS_LITTLE_ENDIAN

endchoice

choice
	prompt "CPU selection"
	default CPU_MIPS32_R2

config CPU_MIPS32_R1
	bool "MIPS32 Release 1"
	depends on SUPPORTS_CPU_MIPS32_R1
	select 32BIT
	help
	  Choose this option to build an U-Boot for release 1 or later of the
	  MIPS32 architecture.

config CPU_MIPS32_R2
	bool "MIPS32 Release 2"
	depends on SUPPORTS_CPU_MIPS32_R2
	select 32BIT
	help
	  Choose this option to build an U-Boot for release 2 or later of the
	  MIPS32 architecture.

config CPU_MIPS64_R1
	bool "MIPS64 Release 1"
	depends on SUPPORTS_CPU_MIPS64_R1
	select 64BIT
	help
	  Choose this option to build a kernel for release 1 or later of the
	  MIPS64 architecture.

config CPU_MIPS64_R2
	bool "MIPS64 Release 2"
	depends on SUPPORTS_CPU_MIPS64_R2
	select 64BIT
	help
	  Choose this option to build a kernel for release 2 or later of the
	  MIPS64 architecture.

endchoice

menu "OS boot interface"

config MIPS_BOOT_CMDLINE_LEGACY
	bool "Hand over legacy command line to Linux kernel"
	default y
	help
	  Enable this option if you want U-Boot to hand over the Yamon-style
	  command line to the kernel. All bootargs will be prepared as argc/argv
	  compatible list. The argument count (argc) is stored in register $a0.
	  The address of the argument list (argv) is stored in register $a1.

config MIPS_BOOT_ENV_LEGACY
	bool "Hand over legacy environment to Linux kernel"
	default y
	help
	  Enable this option if you want U-Boot to hand over the Yamon-style
	  environment to the kernel. Information like memory size, initrd
	  address and size will be prepared as zero-terminated key/value list.
	  The address of the environment is stored in register $a2.

config MIPS_BOOT_FDT
	bool "Hand over a flattened device tree to Linux kernel"
	default n
	help
	  Enable this option if you want U-Boot to hand over a flattened
	  device tree to the kernel. According to UHI register $a0 will be set
	  to -2 and the FDT address is stored in $a1.

endmenu

config SUPPORTS_BIG_ENDIAN
	bool

config SUPPORTS_LITTLE_ENDIAN
	bool

config SUPPORTS_CPU_MIPS32_R1
	bool

config SUPPORTS_CPU_MIPS32_R2
	bool

config SUPPORTS_CPU_MIPS64_R1
	bool

config SUPPORTS_CPU_MIPS64_R2
	bool

config CPU_MIPS32
	bool
	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2

config CPU_MIPS64
	bool
	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2

config MIPS_TUNE_4KC
	bool

config MIPS_TUNE_14KC
	bool

config MIPS_TUNE_24KC
	bool

config 32BIT
	bool

config 64BIT
	bool

config SWAP_IO_SPACE
	bool

config SYS_MIPS_CACHE_INIT_RAM_LOAD
	bool

config MIPS_L1_CACHE_SHIFT_4
	bool

config MIPS_L1_CACHE_SHIFT_5
	bool

config MIPS_L1_CACHE_SHIFT_6
	bool

config MIPS_L1_CACHE_SHIFT_7
	bool

config MIPS_L1_CACHE_SHIFT
	int
	default "7" if MIPS_L1_CACHE_SHIFT_7
	default "6" if MIPS_L1_CACHE_SHIFT_6
	default "5" if MIPS_L1_CACHE_SHIFT_5
	default "4" if MIPS_L1_CACHE_SHIFT_4
	default "5"

config DYNAMIC_IO_PORT_BASE
	bool

endif

endmenu
Commit	Line	Data
dd84058d MY	1	menu "MIPS architecture"
	2	depends on MIPS
	3
	4	config SYS_ARCH
dd84058d MY	5	default "mips"
dd84058d MY	6
b9863b6d DS	7	config SYS_CPU
	8	default "mips32" if CPU_MIPS32_R1 \|\| CPU_MIPS32_R2
	9	default "mips64" if CPU_MIPS64_R1 \|\| CPU_MIPS64_R2
	10
dd84058d MY	11	choice
dd84058d MY	12	prompt "Target select"
a26cd049	13	optional
dd84058d MY	14
	15	config TARGET_QEMU_MIPS
	16	bool "Support qemu-mips"
0e1dc345 DS	17	select SUPPORTS_BIG_ENDIAN
0e1dc345 DS	18	select SUPPORTS_LITTLE_ENDIAN
02611cbb DS	19	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	20	select SUPPORTS_CPU_MIPS32_R2
aa45f75e DS	21	select SUPPORTS_CPU_MIPS64_R1
aa45f75e DS	22	select SUPPORTS_CPU_MIPS64_R2
dd84058d MY	23
	24	config TARGET_MALTA
	25	bool "Support malta"
05e34255	26	select DYNAMIC_IO_PORT_BASE
0e1dc345 DS	27	select SUPPORTS_BIG_ENDIAN
0e1dc345 DS	28	select SUPPORTS_LITTLE_ENDIAN
02611cbb DS	29	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	30	select SUPPORTS_CPU_MIPS32_R2
9d638eea	31	select SWAP_IO_SPACE
f53830e7	32	select MIPS_L1_CACHE_SHIFT_6
dd84058d MY	33
	34	config TARGET_VCT
	35	bool "Support vct"
0e1dc345	36	select SUPPORTS_BIG_ENDIAN
02611cbb DS	37	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	38	select SUPPORTS_CPU_MIPS32_R2
dd7c7200	39	select SYS_MIPS_CACHE_INIT_RAM_LOAD
dd84058d MY	40
	41	config TARGET_DBAU1X00
	42	bool "Support dbau1x00"
0e1dc345 DS	43	select SUPPORTS_BIG_ENDIAN
0e1dc345 DS	44	select SUPPORTS_LITTLE_ENDIAN
02611cbb DS	45	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	46	select SUPPORTS_CPU_MIPS32_R2
dd7c7200	47	select SYS_MIPS_CACHE_INIT_RAM_LOAD
0315a289	48	select MIPS_TUNE_4KC
dd84058d MY	49
	50	config TARGET_PB1X00
	51	bool "Support pb1x00"
0e1dc345	52	select SUPPORTS_LITTLE_ENDIAN
02611cbb DS	53	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	54	select SUPPORTS_CPU_MIPS32_R2
dd7c7200	55	select SYS_MIPS_CACHE_INIT_RAM_LOAD
0315a289	56	select MIPS_TUNE_4KC
dd84058d	57
1d3d0f1f WW	58	config ARCH_ATH79
	59	bool "Support QCA/Atheros ath79"
	60	select OF_CONTROL
	61	select DM
	62
32c1a6ee PCM	63	config MACH_PIC32
	64	bool "Support Microchip PIC32"
	65	select OF_CONTROL
	66	select DM
	67
dd84058d MY	68	endchoice
	69
	70	source "board/dbau1x00/Kconfig"
	71	source "board/imgtec/malta/Kconfig"
	72	source "board/micronas/vct/Kconfig"
	73	source "board/pb1x00/Kconfig"
	74	source "board/qemu-mips/Kconfig"
1d3d0f1f	75	source "arch/mips/mach-ath79/Kconfig"
32c1a6ee	76	source "arch/mips/mach-pic32/Kconfig"
dd84058d	77
0e1dc345 DS	78	if MIPS
	79
	80	choice
	81	prompt "Endianness selection"
	82	help
	83	Some MIPS boards can be configured for either little or big endian
	84	byte order. These modes require different U-Boot images. In general there
	85	is one preferred byteorder for a particular system but some systems are
	86	just as commonly used in the one or the other endianness.
	87
	88	config SYS_BIG_ENDIAN
	89	bool "Big endian"
	90	depends on SUPPORTS_BIG_ENDIAN
	91
	92	config SYS_LITTLE_ENDIAN
	93	bool "Little endian"
	94	depends on SUPPORTS_LITTLE_ENDIAN
	95
	96	endchoice
	97
02611cbb DS	98	choice
	99	prompt "CPU selection"
	100	default CPU_MIPS32_R2
	101
	102	config CPU_MIPS32_R1
	103	bool "MIPS32 Release 1"
	104	depends on SUPPORTS_CPU_MIPS32_R1
	105	select 32BIT
	106	help
	107	Choose this option to build an U-Boot for release 1 or later of the
	108	MIPS32 architecture.
	109
	110	config CPU_MIPS32_R2
	111	bool "MIPS32 Release 2"
	112	depends on SUPPORTS_CPU_MIPS32_R2
	113	select 32BIT
	114	help
	115	Choose this option to build an U-Boot for release 2 or later of the
	116	MIPS32 architecture.
	117
	118	config CPU_MIPS64_R1
	119	bool "MIPS64 Release 1"
	120	depends on SUPPORTS_CPU_MIPS64_R1
	121	select 64BIT
	122	help
	123	Choose this option to build a kernel for release 1 or later of the
	124	MIPS64 architecture.
	125
	126	config CPU_MIPS64_R2
	127	bool "MIPS64 Release 2"
	128	depends on SUPPORTS_CPU_MIPS64_R2
	129	select 64BIT
	130	help
	131	Choose this option to build a kernel for release 2 or later of the
	132	MIPS64 architecture.
	133
	134	endchoice
	135
25fc664f DS	136	menu "OS boot interface"
	137
	138	config MIPS_BOOT_CMDLINE_LEGACY
	139	bool "Hand over legacy command line to Linux kernel"
	140	default y
	141	help
	142	Enable this option if you want U-Boot to hand over the Yamon-style
	143	command line to the kernel. All bootargs will be prepared as argc/argv
	144	compatible list. The argument count (argc) is stored in register $a0.
	145	The address of the argument list (argv) is stored in register $a1.
	146
ca65e585 DS	147	config MIPS_BOOT_ENV_LEGACY
	148	bool "Hand over legacy environment to Linux kernel"
	149	default y
	150	help
	151	Enable this option if you want U-Boot to hand over the Yamon-style
	152	environment to the kernel. Information like memory size, initrd
	153	address and size will be prepared as zero-terminated key/value list.
1cc0a9f4	154	The address of the environment is stored in register $a2.
ca65e585	155
5002d8cc	156	config MIPS_BOOT_FDT
90b1c9fa	157	bool "Hand over a flattened device tree to Linux kernel"
5002d8cc DS	158	default n
	159	help
	160	Enable this option if you want U-Boot to hand over a flattened
90b1c9fa DS	161	device tree to the kernel. According to UHI register $a0 will be set
90b1c9fa DS	162	to -2 and the FDT address is stored in $a1.
5002d8cc	163
25fc664f DS	164	endmenu
25fc664f DS	165
0e1dc345 DS	166	config SUPPORTS_BIG_ENDIAN
	167	bool
	168
	169	config SUPPORTS_LITTLE_ENDIAN
	170	bool
	171
02611cbb DS	172	config SUPPORTS_CPU_MIPS32_R1
	173	bool
	174
	175	config SUPPORTS_CPU_MIPS32_R2
	176	bool
	177
	178	config SUPPORTS_CPU_MIPS64_R1
	179	bool
	180
	181	config SUPPORTS_CPU_MIPS64_R2
	182	bool
	183
c57dafb5 DS	184	config CPU_MIPS32
	185	bool
	186	default y if CPU_MIPS32_R1 \|\| CPU_MIPS32_R2
	187
	188	config CPU_MIPS64
	189	bool
	190	default y if CPU_MIPS64_R1 \|\| CPU_MIPS64_R2
	191
0315a289 DS	192	config MIPS_TUNE_4KC
	193	bool
	194
	195	config MIPS_TUNE_14KC
	196	bool
	197
	198	config MIPS_TUNE_24KC
	199	bool
	200
02611cbb DS	201	config 32BIT
	202	bool
	203
	204	config 64BIT
	205	bool
	206
9d638eea DS	207	config SWAP_IO_SPACE
	208	bool
	209
dd7c7200 PB	210	config SYS_MIPS_CACHE_INIT_RAM_LOAD
	211	bool
	212
f53830e7 DS	213	config MIPS_L1_CACHE_SHIFT_4
	214	bool
	215
	216	config MIPS_L1_CACHE_SHIFT_5
	217	bool
	218
	219	config MIPS_L1_CACHE_SHIFT_6
	220	bool
	221
	222	config MIPS_L1_CACHE_SHIFT_7
	223	bool
	224
	225	config MIPS_L1_CACHE_SHIFT
	226	int
	227	default "7" if MIPS_L1_CACHE_SHIFT_7
	228	default "6" if MIPS_L1_CACHE_SHIFT_6
	229	default "5" if MIPS_L1_CACHE_SHIFT_5
	230	default "4" if MIPS_L1_CACHE_SHIFT_4
	231	default "5"
	232
05e34255 PB	233	config DYNAMIC_IO_PORT_BASE
	234	bool
	235
0e1dc345 DS	236	endif
0e1dc345 DS	237
dd84058d	238	endmenu