[people/ms/u-boot.git] / arch / mips / Kconfig

menu "MIPS architecture"
	depends on MIPS

config SYS_ARCH
	default "mips"

config SYS_CPU
	default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2
	default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2

choice
	prompt "Target select"
	optional

config TARGET_QEMU_MIPS
	bool "Support qemu-mips"
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_LITTLE_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SUPPORTS_CPU_MIPS64_R1
	select SUPPORTS_CPU_MIPS64_R2

config TARGET_MALTA
	bool "Support malta"
	select DYNAMIC_IO_PORT_BASE
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_LITTLE_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SWAP_IO_SPACE
	select MIPS_L1_CACHE_SHIFT_6

config TARGET_VCT
	bool "Support vct"
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SYS_MIPS_CACHE_INIT_RAM_LOAD

config TARGET_DBAU1X00
	bool "Support dbau1x00"
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_LITTLE_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SYS_MIPS_CACHE_INIT_RAM_LOAD
	select MIPS_TUNE_4KC

config TARGET_PB1X00
	bool "Support pb1x00"
	select SUPPORTS_LITTLE_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SYS_MIPS_CACHE_INIT_RAM_LOAD
	select MIPS_TUNE_4KC

config MACH_PIC32
	bool "Support Microchip PIC32"
	select OF_CONTROL
	select DM

endchoice

source "board/dbau1x00/Kconfig"
source "board/imgtec/malta/Kconfig"
source "board/micronas/vct/Kconfig"
source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
source "arch/mips/mach-pic32/Kconfig"

if MIPS

choice
	prompt "Endianness selection"
	help
	  Some MIPS boards can be configured for either little or big endian
	  byte order. These modes require different U-Boot images. In general there
	  is one preferred byteorder for a particular system but some systems are
	  just as commonly used in the one or the other endianness.

config SYS_BIG_ENDIAN
	bool "Big endian"
	depends on SUPPORTS_BIG_ENDIAN

config SYS_LITTLE_ENDIAN
	bool "Little endian"
	depends on SUPPORTS_LITTLE_ENDIAN

endchoice

choice
	prompt "CPU selection"
	default CPU_MIPS32_R2

config CPU_MIPS32_R1
	bool "MIPS32 Release 1"
	depends on SUPPORTS_CPU_MIPS32_R1
	select 32BIT
	help
	  Choose this option to build an U-Boot for release 1 or later of the
	  MIPS32 architecture.

config CPU_MIPS32_R2
	bool "MIPS32 Release 2"
	depends on SUPPORTS_CPU_MIPS32_R2
	select 32BIT
	help
	  Choose this option to build an U-Boot for release 2 or later of the
	  MIPS32 architecture.

config CPU_MIPS64_R1
	bool "MIPS64 Release 1"
	depends on SUPPORTS_CPU_MIPS64_R1
	select 64BIT
	help
	  Choose this option to build a kernel for release 1 or later of the
	  MIPS64 architecture.

config CPU_MIPS64_R2
	bool "MIPS64 Release 2"
	depends on SUPPORTS_CPU_MIPS64_R2
	select 64BIT
	help
	  Choose this option to build a kernel for release 2 or later of the
	  MIPS64 architecture.

endchoice

menu "OS boot interface"

config MIPS_BOOT_CMDLINE_LEGACY
	bool "Hand over legacy command line to Linux kernel"
	default y
	help
	  Enable this option if you want U-Boot to hand over the Yamon-style
	  command line to the kernel. All bootargs will be prepared as argc/argv
	  compatible list. The argument count (argc) is stored in register $a0.
	  The address of the argument list (argv) is stored in register $a1.

config MIPS_BOOT_ENV_LEGACY
	bool "Hand over legacy environment to Linux kernel"
	default y
	help
	  Enable this option if you want U-Boot to hand over the Yamon-style
	  environment to the kernel. Information like memory size, initrd
	  address and size will be prepared as zero-terminated key/value list.
	  The address of the enviroment is stored in register $a2.

config MIPS_BOOT_FDT
	bool "Hand over a flattened device tree to Linux kernel"
	default n
	help
	  Enable this option if you want U-Boot to hand over a flattened
	  device tree to the kernel. According to UHI register $a0 will be set
	  to -2 and the FDT address is stored in $a1.

endmenu

config SUPPORTS_BIG_ENDIAN
	bool

config SUPPORTS_LITTLE_ENDIAN
	bool

config SUPPORTS_CPU_MIPS32_R1
	bool

config SUPPORTS_CPU_MIPS32_R2
	bool

config SUPPORTS_CPU_MIPS64_R1
	bool

config SUPPORTS_CPU_MIPS64_R2
	bool

config CPU_MIPS32
	bool
	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2

config CPU_MIPS64
	bool
	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2

config MIPS_TUNE_4KC
	bool

config MIPS_TUNE_14KC
	bool

config MIPS_TUNE_24KC
	bool

config 32BIT
	bool

config 64BIT
	bool

config SWAP_IO_SPACE
	bool

config SYS_MIPS_CACHE_INIT_RAM_LOAD
	bool

config MIPS_L1_CACHE_SHIFT_4
	bool

config MIPS_L1_CACHE_SHIFT_5
	bool

config MIPS_L1_CACHE_SHIFT_6
	bool

config MIPS_L1_CACHE_SHIFT_7
	bool

config MIPS_L1_CACHE_SHIFT
	int
	default "7" if MIPS_L1_CACHE_SHIFT_7
	default "6" if MIPS_L1_CACHE_SHIFT_6
	default "5" if MIPS_L1_CACHE_SHIFT_5
	default "4" if MIPS_L1_CACHE_SHIFT_4
	default "5"

config DYNAMIC_IO_PORT_BASE
	bool

endif

endmenu
Commit	Line	Data
dd84058d MY	1	menu "MIPS architecture"
	2	depends on MIPS
	3
	4	config SYS_ARCH
dd84058d MY	5	default "mips"
dd84058d MY	6
b9863b6d DS	7	config SYS_CPU
	8	default "mips32" if CPU_MIPS32_R1 \|\| CPU_MIPS32_R2
	9	default "mips64" if CPU_MIPS64_R1 \|\| CPU_MIPS64_R2
	10
dd84058d MY	11	choice
dd84058d MY	12	prompt "Target select"
a26cd049	13	optional
dd84058d MY	14
	15	config TARGET_QEMU_MIPS
	16	bool "Support qemu-mips"
0e1dc345 DS	17	select SUPPORTS_BIG_ENDIAN
0e1dc345 DS	18	select SUPPORTS_LITTLE_ENDIAN
02611cbb DS	19	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	20	select SUPPORTS_CPU_MIPS32_R2
aa45f75e DS	21	select SUPPORTS_CPU_MIPS64_R1
aa45f75e DS	22	select SUPPORTS_CPU_MIPS64_R2
dd84058d MY	23
	24	config TARGET_MALTA
	25	bool "Support malta"
05e34255	26	select DYNAMIC_IO_PORT_BASE
0e1dc345 DS	27	select SUPPORTS_BIG_ENDIAN
0e1dc345 DS	28	select SUPPORTS_LITTLE_ENDIAN
02611cbb DS	29	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	30	select SUPPORTS_CPU_MIPS32_R2
9d638eea	31	select SWAP_IO_SPACE
f53830e7	32	select MIPS_L1_CACHE_SHIFT_6
dd84058d MY	33
	34	config TARGET_VCT
	35	bool "Support vct"
0e1dc345	36	select SUPPORTS_BIG_ENDIAN
02611cbb DS	37	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	38	select SUPPORTS_CPU_MIPS32_R2
dd7c7200	39	select SYS_MIPS_CACHE_INIT_RAM_LOAD
dd84058d MY	40
	41	config TARGET_DBAU1X00
	42	bool "Support dbau1x00"
0e1dc345 DS	43	select SUPPORTS_BIG_ENDIAN
0e1dc345 DS	44	select SUPPORTS_LITTLE_ENDIAN
02611cbb DS	45	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	46	select SUPPORTS_CPU_MIPS32_R2
dd7c7200	47	select SYS_MIPS_CACHE_INIT_RAM_LOAD
0315a289	48	select MIPS_TUNE_4KC
dd84058d MY	49
	50	config TARGET_PB1X00
	51	bool "Support pb1x00"
0e1dc345	52	select SUPPORTS_LITTLE_ENDIAN
02611cbb DS	53	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	54	select SUPPORTS_CPU_MIPS32_R2
dd7c7200	55	select SYS_MIPS_CACHE_INIT_RAM_LOAD
0315a289	56	select MIPS_TUNE_4KC
dd84058d	57
32c1a6ee PCM	58	config MACH_PIC32
	59	bool "Support Microchip PIC32"
	60	select OF_CONTROL
	61	select DM
	62
dd84058d MY	63	endchoice
	64
	65	source "board/dbau1x00/Kconfig"
	66	source "board/imgtec/malta/Kconfig"
	67	source "board/micronas/vct/Kconfig"
	68	source "board/pb1x00/Kconfig"
	69	source "board/qemu-mips/Kconfig"
32c1a6ee	70	source "arch/mips/mach-pic32/Kconfig"
dd84058d	71
0e1dc345 DS	72	if MIPS
	73
	74	choice
	75	prompt "Endianness selection"
	76	help
	77	Some MIPS boards can be configured for either little or big endian
	78	byte order. These modes require different U-Boot images. In general there
	79	is one preferred byteorder for a particular system but some systems are
	80	just as commonly used in the one or the other endianness.
	81
	82	config SYS_BIG_ENDIAN
	83	bool "Big endian"
	84	depends on SUPPORTS_BIG_ENDIAN
	85
	86	config SYS_LITTLE_ENDIAN
	87	bool "Little endian"
	88	depends on SUPPORTS_LITTLE_ENDIAN
	89
	90	endchoice
	91
02611cbb DS	92	choice
	93	prompt "CPU selection"
	94	default CPU_MIPS32_R2
	95
	96	config CPU_MIPS32_R1
	97	bool "MIPS32 Release 1"
	98	depends on SUPPORTS_CPU_MIPS32_R1
	99	select 32BIT
	100	help
	101	Choose this option to build an U-Boot for release 1 or later of the
	102	MIPS32 architecture.
	103
	104	config CPU_MIPS32_R2
	105	bool "MIPS32 Release 2"
	106	depends on SUPPORTS_CPU_MIPS32_R2
	107	select 32BIT
	108	help
	109	Choose this option to build an U-Boot for release 2 or later of the
	110	MIPS32 architecture.
	111
	112	config CPU_MIPS64_R1
	113	bool "MIPS64 Release 1"
	114	depends on SUPPORTS_CPU_MIPS64_R1
	115	select 64BIT
	116	help
	117	Choose this option to build a kernel for release 1 or later of the
	118	MIPS64 architecture.
	119
	120	config CPU_MIPS64_R2
	121	bool "MIPS64 Release 2"
	122	depends on SUPPORTS_CPU_MIPS64_R2
	123	select 64BIT
	124	help
	125	Choose this option to build a kernel for release 2 or later of the
	126	MIPS64 architecture.
	127
	128	endchoice
	129
25fc664f DS	130	menu "OS boot interface"
	131
	132	config MIPS_BOOT_CMDLINE_LEGACY
	133	bool "Hand over legacy command line to Linux kernel"
	134	default y
	135	help
	136	Enable this option if you want U-Boot to hand over the Yamon-style
	137	command line to the kernel. All bootargs will be prepared as argc/argv
	138	compatible list. The argument count (argc) is stored in register $a0.
	139	The address of the argument list (argv) is stored in register $a1.
	140
ca65e585 DS	141	config MIPS_BOOT_ENV_LEGACY
	142	bool "Hand over legacy environment to Linux kernel"
	143	default y
	144	help
	145	Enable this option if you want U-Boot to hand over the Yamon-style
	146	environment to the kernel. Information like memory size, initrd
	147	address and size will be prepared as zero-terminated key/value list.
	148	The address of the enviroment is stored in register $a2.
	149
5002d8cc	150	config MIPS_BOOT_FDT
90b1c9fa	151	bool "Hand over a flattened device tree to Linux kernel"
5002d8cc DS	152	default n
	153	help
	154	Enable this option if you want U-Boot to hand over a flattened
90b1c9fa DS	155	device tree to the kernel. According to UHI register $a0 will be set
90b1c9fa DS	156	to -2 and the FDT address is stored in $a1.
5002d8cc	157
25fc664f DS	158	endmenu
25fc664f DS	159
0e1dc345 DS	160	config SUPPORTS_BIG_ENDIAN
	161	bool
	162
	163	config SUPPORTS_LITTLE_ENDIAN
	164	bool
	165
02611cbb DS	166	config SUPPORTS_CPU_MIPS32_R1
	167	bool
	168
	169	config SUPPORTS_CPU_MIPS32_R2
	170	bool
	171
	172	config SUPPORTS_CPU_MIPS64_R1
	173	bool
	174
	175	config SUPPORTS_CPU_MIPS64_R2
	176	bool
	177
c57dafb5 DS	178	config CPU_MIPS32
	179	bool
	180	default y if CPU_MIPS32_R1 \|\| CPU_MIPS32_R2
	181
	182	config CPU_MIPS64
	183	bool
	184	default y if CPU_MIPS64_R1 \|\| CPU_MIPS64_R2
	185
0315a289 DS	186	config MIPS_TUNE_4KC
	187	bool
	188
	189	config MIPS_TUNE_14KC
	190	bool
	191
	192	config MIPS_TUNE_24KC
	193	bool
	194
02611cbb DS	195	config 32BIT
	196	bool
	197
	198	config 64BIT
	199	bool
	200
9d638eea DS	201	config SWAP_IO_SPACE
	202	bool
	203
dd7c7200 PB	204	config SYS_MIPS_CACHE_INIT_RAM_LOAD
	205	bool
	206
f53830e7 DS	207	config MIPS_L1_CACHE_SHIFT_4
	208	bool
	209
	210	config MIPS_L1_CACHE_SHIFT_5
	211	bool
	212
	213	config MIPS_L1_CACHE_SHIFT_6
	214	bool
	215
	216	config MIPS_L1_CACHE_SHIFT_7
	217	bool
	218
	219	config MIPS_L1_CACHE_SHIFT
	220	int
	221	default "7" if MIPS_L1_CACHE_SHIFT_7
	222	default "6" if MIPS_L1_CACHE_SHIFT_6
	223	default "5" if MIPS_L1_CACHE_SHIFT_5
	224	default "4" if MIPS_L1_CACHE_SHIFT_4
	225	default "5"
	226
05e34255 PB	227	config DYNAMIC_IO_PORT_BASE
	228	bool
	229
0e1dc345 DS	230	endif
0e1dc345 DS	231
dd84058d	232	endmenu