[thirdparty/kernel/linux.git] / arch / mips / boot / dts / brcm / bcm7125.dtsi

// SPDX-License-Identifier: GPL-2.0
/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "brcm,bcm7125";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		mips-hpt-frequency = <202500000>;

		cpu@0 {
			compatible = "brcm,bmips4380";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "brcm,bmips4380";
			device_type = "cpu";
			reg = <1>;
		};
	};

	aliases {
		uart0 = &uart0;
	};

	cpu_intc: interrupt-controller {
		#address-cells = <0>;
		compatible = "mti,cpu-interrupt-controller";

		interrupt-controller;
		#interrupt-cells = <1>;
	};

	clocks {
		uart_clk: uart_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <81000000>;
		};

		upg_clk: upg_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <27000000>;
		};
	};

	rdb {
		#address-cells = <1>;
		#size-cells = <1>;

		compatible = "simple-bus";
		ranges = <0 0x10000000 0x01000000>;

		periph_intc: interrupt-controller@441400 {
			compatible = "brcm,bcm7038-l1-intc";
			reg = <0x441400 0x30>, <0x441600 0x30>;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-parent = <&cpu_intc>;
			interrupts = <2>, <3>;
		};

		sun_l2_intc: interrupt-controller@401800 {
			compatible = "brcm,l2-intc";
			reg = <0x401800 0x30>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&periph_intc>;
			interrupts = <23>;
		};

		gisb-arb@400000 {
			compatible = "brcm,bcm7400-gisb-arb";
			reg = <0x400000 0xdc>;
			native-endian;
			interrupt-parent = <&sun_l2_intc>;
			interrupts = <0>, <2>;
			brcm,gisb-arb-master-mask = <0x2f7>;
			brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
						     "bsp_0", "rdc_0", "rptd_0",
						     "avd_0", "jtag_0";
		};

		upg_irq0_intc: interrupt-controller@406780 {
			compatible = "brcm,bcm7120-l2-intc";
			reg = <0x406780 0x8>;

			brcm,int-map-mask = <0x44>, <0xf000000>, <0x100000>;
			brcm,int-fwd-mask = <0x70000>;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-parent = <&periph_intc>;
			interrupts = <18>, <19>, <20>;
			interrupt-names = "upg_main", "upg_bsc", "upg_spi";
		};

		sun_top_ctrl: syscon@404000 {
			compatible = "brcm,bcm7125-sun-top-ctrl", "syscon";
			reg = <0x404000 0x60c>;
			native-endian;
		};

		reboot {
			compatible = "brcm,bcm7038-reboot";
			syscon = <&sun_top_ctrl 0x8 0x14>;
		};

		uart0: serial@406b00 {
			compatible = "ns16550a";
			reg = <0x406b00 0x20>;
			reg-io-width = <0x4>;
			reg-shift = <0x2>;
			native-endian;
			interrupt-parent = <&periph_intc>;
			interrupts = <21>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart1: serial@406b40 {
			compatible = "ns16550a";
			reg = <0x406b40 0x20>;
			reg-io-width = <0x4>;
			reg-shift = <0x2>;
			native-endian;
			interrupt-parent = <&periph_intc>;
			interrupts = <64>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart2: serial@406b80 {
			compatible = "ns16550a";
			reg = <0x406b80 0x20>;
			reg-io-width = <0x4>;
			reg-shift = <0x2>;
			native-endian;
			interrupt-parent = <&periph_intc>;
			interrupts = <65>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		bsca: i2c@406200 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_irq0_intc>;
		      reg = <0x406200 0x58>;
		      interrupts = <24>;
		      interrupt-names = "upg_bsca";
		      status = "disabled";
		};

		bscb: i2c@406280 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_irq0_intc>;
		      reg = <0x406280 0x58>;
		      interrupts = <25>;
		      interrupt-names = "upg_bscb";
		      status = "disabled";
		};

		bscc: i2c@406300 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_irq0_intc>;
		      reg = <0x406300 0x58>;
		      interrupts = <26>;
		      interrupt-names = "upg_bscc";
		      status = "disabled";
		};

		bscd: i2c@406380 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_irq0_intc>;
		      reg = <0x406380 0x58>;
		      interrupts = <27>;
		      interrupt-names = "upg_bscd";
		      status = "disabled";
		};

		pwma: pwm@406580 {
			compatible = "brcm,bcm7038-pwm";
			reg = <0x406580 0x28>;
			#pwm-cells = <2>;
			clocks = <&upg_clk>;
			status = "disabled";
		};

		upg_gio: gpio@406700 {
			compatible = "brcm,brcmstb-gpio";
			reg = <0x406700 0x80>;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			gpio-controller;
			interrupt-controller;
			interrupt-parent = <&upg_irq0_intc>;
			interrupts = <6>;
			brcm,gpio-bank-widths = <32 32 32 18>;
		};

		ehci0: usb@488300 {
			compatible = "brcm,bcm7125-ehci", "generic-ehci";
			reg = <0x488300 0x100>;
			native-endian;
			interrupt-parent = <&periph_intc>;
			interrupts = <60>;
			status = "disabled";
		};

		ohci0: usb@488400 {
			compatible = "brcm,bcm7125-ohci", "generic-ohci";
			reg = <0x488400 0x100>;
			native-endian;
			interrupt-parent = <&periph_intc>;
			interrupts = <61>;
			status = "disabled";
		};

		spi_l2_intc: interrupt-controller@411d00 {
			compatible = "brcm,l2-intc";
			reg = <0x411d00 0x30>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&periph_intc>;
			interrupts = <79>;
		};

		qspi: spi@443000 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "brcm,spi-bcm-qspi",
				     "brcm,spi-brcmstb-qspi";
			clocks = <&upg_clk>;
			reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
			reg-names = "cs_reg", "hif_mspi", "bspi";
			interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
			interrupt-parent = <&spi_l2_intc>;
			interrupt-names = "spi_lr_fullness_reached",
					  "spi_lr_session_aborted",
					  "spi_lr_impatient",
					  "spi_lr_session_done",
					  "spi_lr_overread",
					  "mspi_done",
					  "mspi_halted";
			status = "disabled";
		};

		mspi: spi@406400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,spi-bcm-qspi",
				     "brcm,spi-brcmstb-mspi";
			clocks = <&upg_clk>;
			reg = <0x406400 0x180>;
			reg-names = "mspi";
			interrupts = <0x14>;
			interrupt-parent = <&upg_irq0_intc>;
			interrupt-names = "mspi_done";
			status = "disabled";
		};
	};
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
8945e37e KC	2	/ {
	3	#address-cells = <1>;
	4	#size-cells = <1>;
	5	compatible = "brcm,bcm7125";
	6
	7	cpus {
	8	#address-cells = <1>;
	9	#size-cells = <0>;
	10
	11	mips-hpt-frequency = <202500000>;
	12
	13	cpu@0 {
	14	compatible = "brcm,bmips4380";
	15	device_type = "cpu";
	16	reg = <0>;
	17	};
	18
	19	cpu@1 {
	20	compatible = "brcm,bmips4380";
	21	device_type = "cpu";
	22	reg = <1>;
	23	};
	24	};
	25
	26	aliases {
	27	uart0 = &uart0;
	28	};
	29
a2c510a2	30	cpu_intc: interrupt-controller {
8945e37e KC	31	#address-cells = <0>;
	32	compatible = "mti,cpu-interrupt-controller";
	33
	34	interrupt-controller;
	35	#interrupt-cells = <1>;
	36	};
	37
	38	clocks {
	39	uart_clk: uart_clk {
	40	compatible = "fixed-clock";
	41	#clock-cells = <0>;
	42	clock-frequency = <81000000>;
	43	};
7bbe59dd JS	44
	45	upg_clk: upg_clk {
	46	compatible = "fixed-clock";
	47	#clock-cells = <0>;
	48	clock-frequency = <27000000>;
	49	};
8945e37e KC	50	};
	51
	52	rdb {
	53	#address-cells = <1>;
	54	#size-cells = <1>;
	55
	56	compatible = "simple-bus";
	57	ranges = <0 0x10000000 0x01000000>;
	58
a2c510a2	59	periph_intc: interrupt-controller@441400 {
8945e37e KC	60	compatible = "brcm,bcm7038-l1-intc";
	61	reg = <0x441400 0x30>, <0x441600 0x30>;
	62
	63	interrupt-controller;
	64	#interrupt-cells = <1>;
	65
	66	interrupt-parent = <&cpu_intc>;
	67	interrupts = <2>, <3>;
	68	};
	69
a2c510a2	70	sun_l2_intc: interrupt-controller@401800 {
8945e37e KC	71	compatible = "brcm,l2-intc";
	72	reg = <0x401800 0x30>;
	73	interrupt-controller;
	74	#interrupt-cells = <1>;
	75	interrupt-parent = <&periph_intc>;
	76	interrupts = <23>;
	77	};
	78
	79	gisb-arb@400000 {
	80	compatible = "brcm,bcm7400-gisb-arb";
	81	reg = <0x400000 0xdc>;
	82	native-endian;
	83	interrupt-parent = <&sun_l2_intc>;
	84	interrupts = <0>, <2>;
	85	brcm,gisb-arb-master-mask = <0x2f7>;
	86	brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
	87	"bsp_0", "rdc_0", "rptd_0",
	88	"avd_0", "jtag_0";
	89	};
	90
a2c510a2	91	upg_irq0_intc: interrupt-controller@406780 {
8945e37e KC	92	compatible = "brcm,bcm7120-l2-intc";
	93	reg = <0x406780 0x8>;
	94
d783738c	95	brcm,int-map-mask = <0x44>, <0xf000000>, <0x100000>;
8945e37e KC	96	brcm,int-fwd-mask = <0x70000>;
	97
	98	interrupt-controller;
	99	#interrupt-cells = <1>;
	100
	101	interrupt-parent = <&periph_intc>;
d783738c JS	102	interrupts = <18>, <19>, <20>;
d783738c JS	103	interrupt-names = "upg_main", "upg_bsc", "upg_spi";
8945e37e KC	104	};
	105
	106	sun_top_ctrl: syscon@404000 {
	107	compatible = "brcm,bcm7125-sun-top-ctrl", "syscon";
	108	reg = <0x404000 0x60c>;
25d6463e	109	native-endian;
8945e37e KC	110	};
	111
	112	reboot {
	113	compatible = "brcm,bcm7038-reboot";
	114	syscon = <&sun_top_ctrl 0x8 0x14>;
	115	};
	116
	117	uart0: serial@406b00 {
	118	compatible = "ns16550a";
	119	reg = <0x406b00 0x20>;
	120	reg-io-width = <0x4>;
	121	reg-shift = <0x2>;
	122	native-endian;
	123	interrupt-parent = <&periph_intc>;
	124	interrupts = <21>;
	125	clocks = <&uart_clk>;
	126	status = "disabled";
	127	};
	128
5c40d493 JS	129	uart1: serial@406b40 {
	130	compatible = "ns16550a";
	131	reg = <0x406b40 0x20>;
	132	reg-io-width = <0x4>;
	133	reg-shift = <0x2>;
	134	native-endian;
	135	interrupt-parent = <&periph_intc>;
	136	interrupts = <64>;
	137	clocks = <&uart_clk>;
	138	status = "disabled";
	139	};
	140
	141	uart2: serial@406b80 {
	142	compatible = "ns16550a";
	143	reg = <0x406b80 0x20>;
	144	reg-io-width = <0x4>;
	145	reg-shift = <0x2>;
	146	native-endian;
	147	interrupt-parent = <&periph_intc>;
	148	interrupts = <65>;
	149	clocks = <&uart_clk>;
	150	status = "disabled";
	151	};
	152
	153	bsca: i2c@406200 {
	154	clock-frequency = <390000>;
	155	compatible = "brcm,brcmstb-i2c";
	156	interrupt-parent = <&upg_irq0_intc>;
	157	reg = <0x406200 0x58>;
	158	interrupts = <24>;
	159	interrupt-names = "upg_bsca";
	160	status = "disabled";
	161	};
	162
	163	bscb: i2c@406280 {
	164	clock-frequency = <390000>;
	165	compatible = "brcm,brcmstb-i2c";
	166	interrupt-parent = <&upg_irq0_intc>;
	167	reg = <0x406280 0x58>;
	168	interrupts = <25>;
	169	interrupt-names = "upg_bscb";
	170	status = "disabled";
	171	};
	172
	173	bscc: i2c@406300 {
	174	clock-frequency = <390000>;
	175	compatible = "brcm,brcmstb-i2c";
	176	interrupt-parent = <&upg_irq0_intc>;
	177	reg = <0x406300 0x58>;
	178	interrupts = <26>;
	179	interrupt-names = "upg_bscc";
	180	status = "disabled";
	181	};
	182
	183	bscd: i2c@406380 {
	184	clock-frequency = <390000>;
	185	compatible = "brcm,brcmstb-i2c";
	186	interrupt-parent = <&upg_irq0_intc>;
	187	reg = <0x406380 0x58>;
	188	interrupts = <27>;
	189	interrupt-names = "upg_bscd";
	190	status = "disabled";
	191	};
	192
7bbe59dd JS	193	pwma: pwm@406580 {
	194	compatible = "brcm,bcm7038-pwm";
	195	reg = <0x406580 0x28>;
	196	#pwm-cells = <2>;
	197	clocks = <&upg_clk>;
	198	status = "disabled";
	199	};
	200
c707844d JS	201	upg_gio: gpio@406700 {
	202	compatible = "brcm,brcmstb-gpio";
	203	reg = <0x406700 0x80>;
	204	#gpio-cells = <2>;
	205	#interrupt-cells = <2>;
	206	gpio-controller;
	207	interrupt-controller;
	208	interrupt-parent = <&upg_irq0_intc>;
	209	interrupts = <6>;
	210	brcm,gpio-bank-widths = <32 32 32 18>;
	211	};
	212
8945e37e KC	213	ehci0: usb@488300 {
	214	compatible = "brcm,bcm7125-ehci", "generic-ehci";
	215	reg = <0x488300 0x100>;
	216	native-endian;
	217	interrupt-parent = <&periph_intc>;
	218	interrupts = <60>;
	219	status = "disabled";
	220	};
	221
	222	ohci0: usb@488400 {
	223	compatible = "brcm,bcm7125-ohci", "generic-ohci";
	224	reg = <0x488400 0x100>;
	225	native-endian;
	226	interrupt-parent = <&periph_intc>;
	227	interrupts = <61>;
	228	status = "disabled";
	229	};
d783738c JS	230
	231	spi_l2_intc: interrupt-controller@411d00 {
	232	compatible = "brcm,l2-intc";
	233	reg = <0x411d00 0x30>;
	234	interrupt-controller;
	235	#interrupt-cells = <1>;
	236	interrupt-parent = <&periph_intc>;
	237	interrupts = <79>;
	238	};
	239
	240	qspi: spi@443000 {
	241	#address-cells = <0x1>;
	242	#size-cells = <0x0>;
	243	compatible = "brcm,spi-bcm-qspi",
	244	"brcm,spi-brcmstb-qspi";
	245	clocks = <&upg_clk>;
	246	reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
	247	reg-names = "cs_reg", "hif_mspi", "bspi";
	248	interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
	249	interrupt-parent = <&spi_l2_intc>;
	250	interrupt-names = "spi_lr_fullness_reached",
	251	"spi_lr_session_aborted",
	252	"spi_lr_impatient",
	253	"spi_lr_session_done",
	254	"spi_lr_overread",
	255	"mspi_done",
	256	"mspi_halted";
	257	status = "disabled";
	258	};
	259
	260	mspi: spi@406400 {
	261	#address-cells = <1>;
	262	#size-cells = <0>;
	263	compatible = "brcm,spi-bcm-qspi",
	264	"brcm,spi-brcmstb-mspi";
	265	clocks = <&upg_clk>;
	266	reg = <0x406400 0x180>;
	267	reg-names = "mspi";
	268	interrupts = <0x14>;
	269	interrupt-parent = <&upg_irq0_intc>;
	270	interrupt-names = "mspi_done";
	271	status = "disabled";
	272	};
8945e37e KC	273	};
8945e37e KC	274	};