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c021880a | 1 | /* |
373b16fc | 2 | * Cache-handling routined for MIPS CPUs |
c021880a WD |
3 | * |
4 | * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
c021880a | 25 | #include <config.h> |
2f5d414c | 26 | #include <asm/asm.h> |
c021880a WD |
27 | #include <asm/regdef.h> |
28 | #include <asm/mipsregs.h> | |
29 | #include <asm/addrspace.h> | |
30 | #include <asm/cacheops.h> | |
31 | ||
2e0e5271 SK |
32 | #define RA t8 |
33 | ||
373b16fc SK |
34 | /* |
35 | * 16kB is the maximum size of instruction and data caches on MIPS 4K, | |
36 | * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. | |
37 | * | |
38 | * Note that the above size is the maximum size of primary cache. U-Boot | |
39 | * doesn't have L2 cache support for now. | |
40 | */ | |
41 | #define MIPS_MAX_CACHE_SIZE 0x10000 | |
c021880a | 42 | |
7daf2ebe | 43 | #define INDEX_BASE CKSEG0 |
2e0e5271 SK |
44 | |
45 | .macro cache_op op addr | |
46 | .set push | |
47 | .set noreorder | |
48 | .set mips3 | |
49 | cache \op, 0(\addr) | |
50 | .set pop | |
51 | .endm | |
52 | ||
c021880a WD |
53 | /* |
54 | * cacheop macro to automate cache operations | |
55 | * first some helpers... | |
56 | */ | |
57 | #define _mincache(size, maxsize) \ | |
58 | bltu size,maxsize,9f ; \ | |
59 | move size,maxsize ; \ | |
60 | 9: | |
61 | ||
62 | #define _align(minaddr, maxaddr, linesize) \ | |
63 | .set noat ; \ | |
64 | subu AT,linesize,1 ; \ | |
65 | not AT ; \ | |
66 | and minaddr,AT ; \ | |
67 | addu maxaddr,-1 ; \ | |
68 | and maxaddr,AT ; \ | |
69 | .set at | |
70 | ||
71 | /* general operations */ | |
72 | #define doop1(op1) \ | |
73 | cache op1,0(a0) | |
74 | #define doop2(op1, op2) \ | |
75 | cache op1,0(a0) ; \ | |
76 | nop ; \ | |
77 | cache op2,0(a0) | |
78 | ||
79 | /* specials for cache initialisation */ | |
80 | #define doop1lw(op1) \ | |
81 | lw zero,0(a0) | |
82 | #define doop1lw1(op1) \ | |
83 | cache op1,0(a0) ; \ | |
84 | lw zero,0(a0) ; \ | |
85 | cache op1,0(a0) | |
86 | #define doop121(op1,op2) \ | |
87 | cache op1,0(a0) ; \ | |
88 | nop; \ | |
89 | cache op2,0(a0) ; \ | |
90 | nop; \ | |
91 | cache op1,0(a0) | |
92 | ||
93 | #define _oploopn(minaddr, maxaddr, linesize, tag, ops) \ | |
94 | .set noreorder ; \ | |
95 | 10: doop##tag##ops ; \ | |
96 | bne minaddr,maxaddr,10b ; \ | |
97 | add minaddr,linesize ; \ | |
98 | .set reorder | |
99 | ||
100 | /* finally the cache operation macros */ | |
101 | #define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ | |
102 | blez n,11f ; \ | |
103 | addu n,kva ; \ | |
104 | _align(kva, n, cacheLineSize) ; \ | |
105 | _oploopn(kva, n, cacheLineSize, tag, ops) ; \ | |
106 | 11: | |
107 | ||
108 | #define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ | |
109 | _mincache(n, cacheSize); \ | |
110 | blez n,11f ; \ | |
111 | addu n,kva ; \ | |
112 | _align(kva, n, cacheLineSize) ; \ | |
113 | _oploopn(kva, n, cacheLineSize, tag, ops) ; \ | |
114 | 11: | |
115 | ||
116 | #define vcacheop(kva, n, cacheSize, cacheLineSize, op) \ | |
117 | vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) | |
118 | ||
119 | #define icacheop(kva, n, cacheSize, cacheLineSize, op) \ | |
120 | icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) | |
121 | ||
18988407 SK |
122 | .macro f_fill64 dst, offset, val |
123 | LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) | |
124 | LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) | |
125 | LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) | |
126 | LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) | |
127 | LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) | |
128 | LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) | |
129 | LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) | |
130 | LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) | |
131 | #if LONGSIZE == 4 | |
132 | LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) | |
133 | LONG_S \val, (\offset + 9 * LONGSIZE)(\dst) | |
134 | LONG_S \val, (\offset + 10 * LONGSIZE)(\dst) | |
135 | LONG_S \val, (\offset + 11 * LONGSIZE)(\dst) | |
136 | LONG_S \val, (\offset + 12 * LONGSIZE)(\dst) | |
137 | LONG_S \val, (\offset + 13 * LONGSIZE)(\dst) | |
138 | LONG_S \val, (\offset + 14 * LONGSIZE)(\dst) | |
139 | LONG_S \val, (\offset + 15 * LONGSIZE)(\dst) | |
140 | #endif | |
141 | .endm | |
142 | ||
2e0e5271 SK |
143 | /* |
144 | * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) | |
145 | */ | |
146 | LEAF(mips_init_icache) | |
147 | blez a1, 9f | |
148 | mtc0 zero, CP0_TAGLO | |
149 | /* clear tag to invalidate */ | |
150 | PTR_LI t0, INDEX_BASE | |
151 | PTR_ADDU t1, t0, a1 | |
152 | 1: cache_op Index_Store_Tag_I t0 | |
153 | PTR_ADDU t0, a2 | |
154 | bne t0, t1, 1b | |
155 | /* fill once, so data field parity is correct */ | |
156 | PTR_LI t0, INDEX_BASE | |
157 | 2: cache_op Fill t0 | |
158 | PTR_ADDU t0, a2 | |
159 | bne t0, t1, 2b | |
160 | /* invalidate again - prudent but not strictly neccessary */ | |
161 | PTR_LI t0, INDEX_BASE | |
162 | 1: cache_op Index_Store_Tag_I t0 | |
163 | PTR_ADDU t0, a2 | |
164 | bne t0, t1, 1b | |
165 | 9: jr ra | |
166 | END(mips_init_icache) | |
167 | ||
168 | /* | |
169 | * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz) | |
170 | */ | |
171 | LEAF(mips_init_dcache) | |
172 | blez a1, 9f | |
173 | mtc0 zero, CP0_TAGLO | |
174 | /* clear all tags */ | |
175 | PTR_LI t0, INDEX_BASE | |
176 | PTR_ADDU t1, t0, a1 | |
177 | 1: cache_op Index_Store_Tag_D t0 | |
178 | PTR_ADDU t0, a2 | |
179 | bne t0, t1, 1b | |
180 | /* load from each line (in cached space) */ | |
181 | PTR_LI t0, INDEX_BASE | |
182 | 2: LONG_L zero, 0(t0) | |
183 | PTR_ADDU t0, a2 | |
184 | bne t0, t1, 2b | |
185 | /* clear all tags */ | |
186 | PTR_LI t0, INDEX_BASE | |
187 | 1: cache_op Index_Store_Tag_D t0 | |
188 | PTR_ADDU t0, a2 | |
189 | bne t0, t1, 1b | |
190 | 9: jr ra | |
191 | END(mips_init_dcache) | |
192 | ||
c021880a WD |
193 | /******************************************************************************* |
194 | * | |
195 | * mips_cache_reset - low level initialisation of the primary caches | |
196 | * | |
197 | * This routine initialises the primary caches to ensure that they | |
198 | * have good parity. It must be called by the ROM before any cached locations | |
199 | * are used to prevent the possibility of data with bad parity being written to | |
200 | * memory. | |
201 | * To initialise the instruction cache it is essential that a source of data | |
202 | * with good parity is available. This routine | |
203 | * will initialise an area of memory starting at location zero to be used as | |
204 | * a source of parity. | |
205 | * | |
206 | * RETURNS: N/A | |
207 | * | |
208 | */ | |
2f5d414c | 209 | NESTED(mips_cache_reset, 0, ra) |
2e0e5271 | 210 | move RA, ra |
6d0f6bcf JCPV |
211 | li t2, CONFIG_SYS_ICACHE_SIZE |
212 | li t3, CONFIG_SYS_DCACHE_SIZE | |
213 | li t4, CONFIG_SYS_CACHELINE_SIZE | |
c021880a WD |
214 | move t5, t4 |
215 | ||
c021880a WD |
216 | li v0, MIPS_MAX_CACHE_SIZE |
217 | ||
18988407 SK |
218 | /* |
219 | * Now clear that much memory starting from zero. | |
c021880a | 220 | */ |
7daf2ebe | 221 | PTR_LI a0, CKSEG1 |
18988407 SK |
222 | PTR_ADDU a1, a0, v0 |
223 | 2: PTR_ADDIU a0, 64 | |
224 | f_fill64 a0, -64, zero | |
225 | bne a0, a1, 2b | |
8bde7f77 | 226 | |
03c031d5 SK |
227 | /* |
228 | * The caches are probably in an indeterminate state, | |
229 | * so we force good parity into them by doing an | |
230 | * invalidate, load/fill, invalidate for each line. | |
231 | */ | |
c021880a | 232 | |
2e0e5271 SK |
233 | /* |
234 | * Assume bottom of RAM will generate good parity for the cache. | |
c021880a WD |
235 | */ |
236 | ||
2e0e5271 SK |
237 | /* |
238 | * Initialize the I-cache first, | |
c021880a | 239 | */ |
2e0e5271 SK |
240 | move a1, t2 |
241 | move a2, t4 | |
49387dba SK |
242 | PTR_LA t7, mips_init_icache |
243 | jalr t7 | |
c021880a | 244 | |
2e0e5271 SK |
245 | /* |
246 | * then initialize D-cache. | |
c021880a | 247 | */ |
2e0e5271 SK |
248 | move a1, t3 |
249 | move a2, t5 | |
49387dba SK |
250 | PTR_LA t7, mips_init_dcache |
251 | jalr t7 | |
c021880a | 252 | |
2e0e5271 | 253 | jr RA |
2f5d414c | 254 | END(mips_cache_reset) |
c021880a WD |
255 | |
256 | /******************************************************************************* | |
257 | * | |
258 | * dcache_status - get cache status | |
259 | * | |
260 | * RETURNS: 0 - cache disabled; 1 - cache enabled | |
261 | * | |
262 | */ | |
2f5d414c | 263 | LEAF(dcache_status) |
d98e348e SK |
264 | mfc0 t0, CP0_CONFIG |
265 | li t1, CONF_CM_UNCACHED | |
266 | andi t0, t0, CONF_CM_CMASK | |
267 | move v0, zero | |
268 | beq t0, t1, 2f | |
269 | li v0, 1 | |
270 | 2: jr ra | |
2f5d414c | 271 | END(dcache_status) |
c021880a WD |
272 | |
273 | /******************************************************************************* | |
274 | * | |
275 | * dcache_disable - disable cache | |
276 | * | |
277 | * RETURNS: N/A | |
278 | * | |
279 | */ | |
2f5d414c | 280 | LEAF(dcache_disable) |
c021880a WD |
281 | mfc0 t0, CP0_CONFIG |
282 | li t1, -8 | |
283 | and t0, t0, t1 | |
284 | ori t0, t0, CONF_CM_UNCACHED | |
03c031d5 | 285 | mtc0 t0, CP0_CONFIG |
43c50925 | 286 | jr ra |
2f5d414c | 287 | END(dcache_disable) |
c021880a | 288 | |
ea638951 SK |
289 | /******************************************************************************* |
290 | * | |
291 | * dcache_enable - enable cache | |
292 | * | |
293 | * RETURNS: N/A | |
294 | * | |
295 | */ | |
296 | LEAF(dcache_enable) | |
297 | mfc0 t0, CP0_CONFIG | |
298 | ori t0, CONF_CM_CMASK | |
299 | xori t0, CONF_CM_CMASK | |
300 | ori t0, CONF_CM_CACHABLE_NONCOHERENT | |
301 | mtc0 t0, CP0_CONFIG | |
302 | jr ra | |
303 | END(dcache_enable) | |
304 | ||
6d0f6bcf | 305 | #ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS |
c021880a WD |
306 | /******************************************************************************* |
307 | * | |
308 | * mips_cache_lock - lock RAM area pointed to by a0 in cache. | |
309 | * | |
310 | * RETURNS: N/A | |
311 | * | |
312 | */ | |
5da627a4 | 313 | #if defined(CONFIG_PURPLE) |
6d0f6bcf | 314 | # define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2) |
5da627a4 | 315 | #else |
6d0f6bcf | 316 | # define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE) |
60fbe254 | 317 | #endif |
c021880a WD |
318 | .globl mips_cache_lock |
319 | .ent mips_cache_lock | |
320 | mips_cache_lock: | |
7daf2ebe | 321 | li a1, CKSEG0 - CACHE_LOCK_SIZE |
c021880a | 322 | addu a0, a1 |
60fbe254 | 323 | li a2, CACHE_LOCK_SIZE |
6d0f6bcf | 324 | li a3, CONFIG_SYS_CACHELINE_SIZE |
c021880a WD |
325 | move a1, a2 |
326 | icacheop(a0,a1,a2,a3,0x1d) | |
327 | ||
43c50925 | 328 | jr ra |
03c031d5 | 329 | |
c021880a | 330 | .end mips_cache_lock |
6d0f6bcf | 331 | #endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */ |