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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
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2/*
3 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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4 */
5
70789bd2 6#include <dt-bindings/clock/bcm6358-clock.h>
487250e6 7#include <dt-bindings/dma/bcm6358-dma.h>
e30d2bd4 8#include <dt-bindings/gpio/gpio.h>
efe8b9d0 9#include <dt-bindings/reset/bcm6358-reset.h>
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10#include "skeleton.dtsi"
11
12/ {
13 compatible = "brcm,bcm6358";
14
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15 aliases {
16 spi0 = &spi;
17 };
18
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19 cpus {
20 reg = <0xfffe0000 0x4>;
21 #address-cells = <1>;
22 #size-cells = <0>;
8c103c33 23 bootph-all;
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24
25 cpu@0 {
26 compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
27 device_type = "cpu";
28 reg = <0>;
8c103c33 29 bootph-all;
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30 };
31
32 cpu@1 {
33 compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
34 device_type = "cpu";
35 reg = <1>;
8c103c33 36 bootph-all;
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37 };
38 };
39
40 clocks {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
8c103c33 44 bootph-all;
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45
46 periph_osc: periph-osc {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <50000000>;
8c103c33 50 bootph-all;
e30d2bd4 51 };
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52
53 periph_clk: periph-clk {
54 compatible = "brcm,bcm6345-clk";
55 reg = <0xfffe0004 0x4>;
56 #clock-cells = <1>;
57 };
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58 };
59
60 pflash: nor@1e000000 {
61 compatible = "cfi-flash";
62 reg = <0x1e000000 0x2000000>;
63 bank-width = <2>;
64 #address-cells = <1>;
65 #size-cells = <1>;
66
67 status = "disabled";
68 };
69
70 ubus {
71 compatible = "simple-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
8c103c33 74 bootph-all;
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75
76 pll_cntl: syscon@fffe0008 {
77 compatible = "syscon";
78 reg = <0xfffe0008 0x4>;
79 };
80
81 syscon-reboot {
82 compatible = "syscon-reboot";
83 regmap = <&pll_cntl>;
84 offset = <0x0>;
85 mask = <0x1>;
86 };
87
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88 periph_rst: reset-controller@fffe0034 {
89 compatible = "brcm,bcm6345-reset";
90 reg = <0xfffe0034 0x4>;
91 #reset-cells = <1>;
92 };
93
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94 wdt: watchdog@fffe005c {
95 compatible = "brcm,bcm6345-wdt";
96 reg = <0xfffe005c 0xc>;
97 clocks = <&periph_osc>;
98 };
99
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100 wdt-reboot {
101 compatible = "wdt-reboot";
102 wdt = <&wdt>;
103 };
104
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105 gpio1: gpio-controller@fffe0080 {
106 compatible = "brcm,bcm6345-gpio";
107 reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>;
108 gpio-controller;
109 #gpio-cells = <2>;
110 ngpios = <8>;
111
112 status = "disabled";
113 };
114
115 gpio0: gpio-controller@fffe0084 {
116 compatible = "brcm,bcm6345-gpio";
117 reg = <0xfffe0084 0x4>, <0xfffe008c 0x4>;
118 gpio-controller;
119 #gpio-cells = <2>;
120
121 status = "disabled";
122 };
123
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124 leds: led-controller@fffe00d0 {
125 compatible = "brcm,bcm6358-leds";
126 reg = <0xfffe00d0 0x8>;
127 #address-cells = <1>;
128 #size-cells = <0>;
129
130 status = "disabled";
131 };
132
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133 uart0: serial@fffe0100 {
134 compatible = "brcm,bcm6345-uart";
135 reg = <0xfffe0100 0x18>;
136 clocks = <&periph_osc>;
137
138 status = "disabled";
139 };
140
141 uart1: serial@fffe0120 {
142 compatible = "brcm,bcm6345-uart";
143 reg = <0xfffe0120 0x18>;
144 clocks = <&periph_osc>;
145
146 status = "disabled";
147 };
148
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149 spi: spi@fffe0800 {
150 compatible = "brcm,bcm6358-spi";
151 reg = <0xfffe0800 0x70c>;
152 #address-cells = <1>;
153 #size-cells = <0>;
154 clocks = <&periph_clk BCM6358_CLK_SPI>;
155 resets = <&periph_rst BCM6358_RST_SPI>;
156 spi-max-frequency = <20000000>;
157 num-cs = <4>;
158
159 status = "disabled";
160 };
161
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162 memory-controller@fffe1200 {
163 compatible = "brcm,bcm6358-mc";
4153e477 164 reg = <0xfffe1200 0x4c>;
8c103c33 165 bootph-all;
e30d2bd4 166 };
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167
168 ehci: usb-controller@fffe1300 {
169 compatible = "brcm,bcm6358-ehci", "generic-ehci";
170 reg = <0xfffe1300 0x100>;
171 phys = <&usbh>;
172 big-endian;
173
174 status = "disabled";
175 };
176
177 ohci: usb-controller@fffe1400 {
178 compatible = "brcm,bcm6358-ohci", "generic-ohci";
179 reg = <0xfffe1400 0x100>;
180 phys = <&usbh>;
181 big-endian;
182
183 status = "disabled";
184 };
185
186 usbh: usb-phy@fffe1500 {
187 compatible = "brcm,bcm6358-usbh";
188 reg = <0xfffe1500 0x28>;
189 #phy-cells = <0>;
190 resets = <&periph_rst BCM6358_RST_USBH>;
191
192 status = "disabled";
193 };
487250e6 194
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195 enet0: ethernet@fffe4000 {
196 compatible = "brcm,bcm6348-enet";
197 #address-cells = <1>;
198 #size-cells = <0>;
199 reg = <0xfffe4000 0x2dc>;
200 clocks = <&periph_clk BCM6358_CLK_ENET0>;
201 dmas = <&iudma BCM6358_DMA_ENET0_RX>,
202 <&iudma BCM6358_DMA_ENET0_TX>;
203 dma-names = "rx",
204 "tx";
205
206 status = "disabled";
207 };
208
209 enet1: ethernet@fffe4800 {
210 compatible = "brcm,bcm6348-enet";
211 #address-cells = <1>;
212 #size-cells = <0>;
213 reg = <0xfffe4800 0x2dc>;
214 clocks = <&periph_clk BCM6358_CLK_ENET1>;
215 dmas = <&iudma BCM6358_DMA_ENET1_RX>,
216 <&iudma BCM6358_DMA_ENET1_TX>;
217 dma-names = "rx",
218 "tx";
219
220 status = "disabled";
221 };
222
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223 iudma: dma-controller@fffe5000 {
224 compatible = "brcm,bcm6348-iudma";
225 reg = <0xfffe5000 0x24>,
226 <0xfffe5100 0x80>,
227 <0xfffe5200 0x80>;
228 reg-names = "dma",
229 "dma-channels",
230 "dma-sram";
231 #dma-cells = <1>;
232 dma-channels = <8>;
233 clocks = <&periph_clk BCM6358_CLK_EMUSB>,
234 <&periph_clk BCM6358_CLK_USBSU>,
235 <&periph_clk BCM6358_CLK_EPHY>;
236 resets = <&periph_rst BCM6358_RST_ENET>,
237 <&periph_rst BCM6358_RST_EPHY>;
238 };
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239 };
240};