[people/ms/u-boot.git] / arch / mips / include / asm / io.h

/*
 * Copyright (C) 1994, 1995 Waldorf GmbH
 * Copyright (C) 1994 - 2000, 06 Ralf Baechle
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
 *	Author: Maciej W. Rozycki <macro@mips.com>
 *
 * SPDX-License-Identifier:	GPL-2.0
 */
#ifndef _ASM_IO_H
#define _ASM_IO_H

#include <linux/bug.h>
#include <linux/compiler.h>
#include <linux/types.h>

#include <asm/addrspace.h>
#include <asm/byteorder.h>
#include <asm/cpu-features.h>
#include <asm/pgtable-bits.h>
#include <asm/processor.h>
#include <asm/string.h>

#include <ioremap.h>
#include <mangle-port.h>
#include <spaces.h>

/*
 * Slowdown I/O port space accesses for antique hardware.
 */
#undef CONF_SLOWDOWN_IO

/*
 * Raw operations are never swapped in software.  OTOH values that raw
 * operations are working on may or may not have been swapped by the bus
 * hardware.  An example use would be for flash memory that's used for
 * execute in place.
 */
# define __raw_ioswabb(a, x)	(x)
# define __raw_ioswabw(a, x)	(x)
# define __raw_ioswabl(a, x)	(x)
# define __raw_ioswabq(a, x)	(x)
# define ____raw_ioswabq(a, x)	(x)

/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */

#define IO_SPACE_LIMIT 0xffff

/*
 * On MIPS I/O ports are memory mapped, so we access them using normal
 * load/store instructions. mips_io_port_base is the virtual address to
 * which all ports are being mapped.  For sake of efficiency some code
 * assumes that this is an address that can be loaded with a single lui
 * instruction, so the lower 16 bits must be zero.  Should be true on
 * on any sane architecture; generic code does not use this assumption.
 */
extern const unsigned long mips_io_port_base;

/*
 * Gcc will generate code to load the value of mips_io_port_base after each
 * function call which may be fairly wasteful in some cases.  So we don't
 * play quite by the book.  We tell gcc mips_io_port_base is a long variable
 * which solves the code generation issue.  Now we need to violate the
 * aliasing rules a little to make initialization possible and finally we
 * will need the barrier() to fight side effects of the aliasing chat.
 * This trickery will eventually collapse under gcc's optimizer.  Oh well.
 */
static inline void set_io_port_base(unsigned long base)
{
	* (unsigned long *) &mips_io_port_base = base;
	barrier();
}

/*
 * Thanks to James van Artsdalen for a better timing-fix than
 * the two short jumps: using outb's to a nonexistent port seems
 * to guarantee better timings even on fast machines.
 *
 * On the other hand, I'd like to be sure of a non-existent port:
 * I feel a bit unsafe about using 0x80 (should be safe, though)
 *
 *		Linus
 *
 */

#define __SLOW_DOWN_IO \
	__asm__ __volatile__( \
		"sb\t$0,0x80(%0)" \
		: : "r" (mips_io_port_base));

#ifdef CONF_SLOWDOWN_IO
#ifdef REALLY_SLOW_IO
#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
#else
#define SLOW_DOWN_IO __SLOW_DOWN_IO
#endif
#else
#define SLOW_DOWN_IO
#endif

/*
 *     virt_to_phys    -       map virtual addresses to physical
 *     @address: address to remap
 *
 *     The returned physical address is the physical (CPU) mapping for
 *     the memory address given. It is only valid to use this function on
 *     addresses directly mapped or allocated via kmalloc.
 *
 *     This function does not give bus mappings for DMA transfers. In
 *     almost all conceivable cases a device driver should not be using
 *     this function
 */
static inline unsigned long virt_to_phys(volatile const void *address)
{
	unsigned long addr = (unsigned long)address;

	/* this corresponds to kernel implementation of __pa() */
#ifdef CONFIG_64BIT
	if (addr < CKSEG0)
		return XPHYSADDR(addr);

	return CPHYSADDR(addr);
#else
	return addr - PAGE_OFFSET + PHYS_OFFSET;
#endif
}

/*
 *     phys_to_virt    -       map physical address to virtual
 *     @address: address to remap
 *
 *     The returned virtual address is a current CPU mapping for
 *     the memory address given. It is only valid to use this function on
 *     addresses that have a kernel mapping
 *
 *     This function does not handle bus mappings for DMA transfers. In
 *     almost all conceivable cases a device driver should not be using
 *     this function
 */
static inline void *phys_to_virt(unsigned long address)
{
	return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
}

/*
 * ISA I/O bus memory addresses are 1:1 with the physical address.
 */
static inline unsigned long isa_virt_to_bus(volatile void *address)
{
	return (unsigned long)address - PAGE_OFFSET;
}

static inline void *isa_bus_to_virt(unsigned long address)
{
	return (void *)(address + PAGE_OFFSET);
}

#define isa_page_to_bus page_to_phys

/*
 * However PCI ones are not necessarily 1:1 and therefore these interfaces
 * are forbidden in portable PCI drivers.
 *
 * Allow them for x86 for legacy drivers, though.
 */
#define virt_to_bus virt_to_phys
#define bus_to_virt phys_to_virt

static inline void __iomem *__ioremap_mode(phys_addr_t offset, unsigned long size,
	unsigned long flags)
{
	void __iomem *addr;
	phys_addr_t phys_addr;

	addr = plat_ioremap(offset, size, flags);
	if (addr)
		return addr;

	phys_addr = fixup_bigphys_addr(offset, size);
	return (void __iomem *)(unsigned long)CKSEG1ADDR(phys_addr);
}

/*
 * ioremap     -   map bus memory into CPU space
 * @offset:    bus address of the memory
 * @size:      size of the resource to map
 *
 * ioremap performs a platform specific sequence of operations to
 * make bus memory CPU accessible via the readb/readw/readl/writeb/
 * writew/writel functions and the other mmio helpers. The returned
 * address is not guaranteed to be usable directly as a virtual
 * address.
 */
#define ioremap(offset, size)						\
	__ioremap_mode((offset), (size), _CACHE_UNCACHED)

/*
 * ioremap_nocache     -   map bus memory into CPU space
 * @offset:    bus address of the memory
 * @size:      size of the resource to map
 *
 * ioremap_nocache performs a platform specific sequence of operations to
 * make bus memory CPU accessible via the readb/readw/readl/writeb/
 * writew/writel functions and the other mmio helpers. The returned
 * address is not guaranteed to be usable directly as a virtual
 * address.
 *
 * This version of ioremap ensures that the memory is marked uncachable
 * on the CPU as well as honouring existing caching rules from things like
 * the PCI bus. Note that there are other caches and buffers on many
 * busses. In particular driver authors should read up on PCI writes
 *
 * It's useful if some control registers are in such an area and
 * write combining or read caching is not desirable:
 */
#define ioremap_nocache(offset, size)					\
	__ioremap_mode((offset), (size), _CACHE_UNCACHED)
#define ioremap_uc ioremap_nocache

/*
 * ioremap_cachable -	map bus memory into CPU space
 * @offset:	    bus address of the memory
 * @size:	    size of the resource to map
 *
 * ioremap_nocache performs a platform specific sequence of operations to
 * make bus memory CPU accessible via the readb/readw/readl/writeb/
 * writew/writel functions and the other mmio helpers. The returned
 * address is not guaranteed to be usable directly as a virtual
 * address.
 *
 * This version of ioremap ensures that the memory is marked cachable by
 * the CPU.  Also enables full write-combining.	 Useful for some
 * memory-like regions on I/O busses.
 */
#define ioremap_cachable(offset, size)					\
	__ioremap_mode((offset), (size), _page_cachable_default)

/*
 * These two are MIPS specific ioremap variant.	 ioremap_cacheable_cow
 * requests a cachable mapping, ioremap_uncached_accelerated requests a
 * mapping using the uncached accelerated mode which isn't supported on
 * all processors.
 */
#define ioremap_cacheable_cow(offset, size)				\
	__ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
#define ioremap_uncached_accelerated(offset, size)			\
	__ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)

static inline void iounmap(const volatile void __iomem *addr)
{
	plat_iounmap(addr);
}

#ifdef CONFIG_CPU_CAVIUM_OCTEON
#define war_octeon_io_reorder_wmb()		wmb()
#else
#define war_octeon_io_reorder_wmb()		do { } while (0)
#endif

#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)			\
									\
static inline void pfx##write##bwlq(type val,				\
				    volatile void __iomem *mem)		\
{									\
	volatile type *__mem;						\
	type __val;							\
									\
	war_octeon_io_reorder_wmb();					\
									\
	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));	\
									\
	__val = pfx##ioswab##bwlq(__mem, val);				\
									\
	if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
		*__mem = __val;						\
	else if (cpu_has_64bits) {					\
		type __tmp;						\
									\
		__asm__ __volatile__(					\
			".set	arch=r4000"	"\t\t# __writeq""\n\t"	\
			"dsll32 %L0, %L0, 0"			"\n\t"	\
			"dsrl32 %L0, %L0, 0"			"\n\t"	\
			"dsll32 %M0, %M0, 0"			"\n\t"	\
			"or	%L0, %L0, %M0"			"\n\t"	\
			"sd	%L0, %2"			"\n\t"	\
			".set	mips0"				"\n"	\
			: "=r" (__tmp)					\
			: "0" (__val), "m" (*__mem));			\
	} else								\
		BUG();							\
}									\
									\
static inline type pfx##read##bwlq(const volatile void __iomem *mem)	\
{									\
	volatile type *__mem;						\
	type __val;							\
									\
	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));	\
									\
	if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
		__val = *__mem;						\
	else if (cpu_has_64bits) {					\
		__asm__ __volatile__(					\
			".set	arch=r4000"	"\t\t# __readq" "\n\t"	\
			"ld	%L0, %1"			"\n\t"	\
			"dsra32 %M0, %L0, 0"			"\n\t"	\
			"sll	%L0, %L0, 0"			"\n\t"	\
			".set	mips0"				"\n"	\
			: "=r" (__val)					\
			: "m" (*__mem));				\
	} else {							\
		__val = 0;						\
		BUG();							\
	}								\
									\
	return pfx##ioswab##bwlq(__mem, __val);				\
}

#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)			\
									\
static inline void pfx##out##bwlq##p(type val, unsigned long port)	\
{									\
	volatile type *__addr;						\
	type __val;							\
									\
	war_octeon_io_reorder_wmb();					\
									\
	__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
									\
	__val = pfx##ioswab##bwlq(__addr, val);				\
									\
	/* Really, we want this to be atomic */				\
	BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));		\
									\
	*__addr = __val;						\
	slow;								\
}									\
									\
static inline type pfx##in##bwlq##p(unsigned long port)			\
{									\
	volatile type *__addr;						\
	type __val;							\
									\
	__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
									\
	BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));		\
									\
	__val = *__addr;						\
	slow;								\
									\
	return pfx##ioswab##bwlq(__addr, __val);			\
}

#define __BUILD_MEMORY_PFX(bus, bwlq, type)				\
									\
__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)

#define BUILDIO_MEM(bwlq, type)						\
									\
__BUILD_MEMORY_PFX(__raw_, bwlq, type)					\
__BUILD_MEMORY_PFX(, bwlq, type)					\
__BUILD_MEMORY_PFX(__mem_, bwlq, type)					\

BUILDIO_MEM(b, u8)
BUILDIO_MEM(w, u16)
BUILDIO_MEM(l, u32)
BUILDIO_MEM(q, u64)

#define __BUILD_IOPORT_PFX(bus, bwlq, type)				\
	__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)			\
	__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)

#define BUILDIO_IOPORT(bwlq, type)					\
	__BUILD_IOPORT_PFX(, bwlq, type)				\
	__BUILD_IOPORT_PFX(__mem_, bwlq, type)

BUILDIO_IOPORT(b, u8)
BUILDIO_IOPORT(w, u16)
BUILDIO_IOPORT(l, u32)
#ifdef CONFIG_64BIT
BUILDIO_IOPORT(q, u64)
#endif

#define __BUILDIO(bwlq, type)						\
									\
__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)

__BUILDIO(q, u64)

#define readb_relaxed			readb
#define readw_relaxed			readw
#define readl_relaxed			readl
#define readq_relaxed			readq

#define writeb_relaxed			writeb
#define writew_relaxed			writew
#define writel_relaxed			writel
#define writeq_relaxed			writeq

#define readb_be(addr)							\
	__raw_readb((__force unsigned *)(addr))
#define readw_be(addr)							\
	be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
#define readl_be(addr)							\
	be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
#define readq_be(addr)							\
	be64_to_cpu(__raw_readq((__force unsigned *)(addr)))

#define writeb_be(val, addr)						\
	__raw_writeb((val), (__force unsigned *)(addr))
#define writew_be(val, addr)						\
	__raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
#define writel_be(val, addr)						\
	__raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
#define writeq_be(val, addr)						\
	__raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))

/*
 * Some code tests for these symbols
 */
#define readq				readq
#define writeq				writeq

#define __BUILD_MEMORY_STRING(bwlq, type)				\
									\
static inline void writes##bwlq(volatile void __iomem *mem,		\
				const void *addr, unsigned int count)	\
{									\
	const volatile type *__addr = addr;				\
									\
	while (count--) {						\
		__mem_write##bwlq(*__addr, mem);			\
		__addr++;						\
	}								\
}									\
									\
static inline void reads##bwlq(volatile void __iomem *mem, void *addr,	\
			       unsigned int count)			\
{									\
	volatile type *__addr = addr;					\
									\
	while (count--) {						\
		*__addr = __mem_read##bwlq(mem);			\
		__addr++;						\
	}								\
}

#define __BUILD_IOPORT_STRING(bwlq, type)				\
									\
static inline void outs##bwlq(unsigned long port, const void *addr,	\
			      unsigned int count)			\
{									\
	const volatile type *__addr = addr;				\
									\
	while (count--) {						\
		__mem_out##bwlq(*__addr, port);				\
		__addr++;						\
	}								\
}									\
									\
static inline void ins##bwlq(unsigned long port, void *addr,		\
			     unsigned int count)			\
{									\
	volatile type *__addr = addr;					\
									\
	while (count--) {						\
		*__addr = __mem_in##bwlq(port);				\
		__addr++;						\
	}								\
}

#define BUILDSTRING(bwlq, type)						\
									\
__BUILD_MEMORY_STRING(bwlq, type)					\
__BUILD_IOPORT_STRING(bwlq, type)

BUILDSTRING(b, u8)
BUILDSTRING(w, u16)
BUILDSTRING(l, u32)
#ifdef CONFIG_64BIT
BUILDSTRING(q, u64)
#endif


#ifdef CONFIG_CPU_CAVIUM_OCTEON
#define mmiowb() wmb()
#else
/* Depends on MIPS II instruction set */
#define mmiowb() asm volatile ("sync" ::: "memory")
#endif

static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
{
	memset((void __force *)addr, val, count);
}
static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
{
	memcpy(dst, (void __force *)src, count);
}
static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
{
	memcpy((void __force *)dst, src, count);
}

/*
 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
 * Avoid interrupt mucking, just adjust the address for 4-byte access.
 * Assume the addresses are 8-byte aligned.
 */
#ifdef __MIPSEB__
#define __CSR_32_ADJUST 4
#else
#define __CSR_32_ADJUST 0
#endif

#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
#define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))

/*
 * U-Boot specific
 */
#define sync()		mmiowb()

#define MAP_NOCACHE	(1)
#define MAP_WRCOMBINE	(0)
#define MAP_WRBACK	(0)
#define MAP_WRTHROUGH	(0)

static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
	if (flags == MAP_NOCACHE)
		return ioremap(paddr, len);

	return (void *)paddr;
}

/*
 * Take down a mapping set up by map_physmem().
 */
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}

#define __BUILD_CLRBITS(bwlq, sfx, end, type)				\
									\
static inline void clrbits_##sfx(volatile void __iomem *mem, type clr)	\
{									\
	type __val = __raw_read##bwlq(mem);				\
	__val = end##_to_cpu(__val);					\
	__val &= ~clr;							\
	__val = cpu_to_##end(__val);					\
	__raw_write##bwlq(__val, mem);					\
}

#define __BUILD_SETBITS(bwlq, sfx, end, type)				\
									\
static inline void setbits_##sfx(volatile void __iomem *mem, type set)	\
{									\
	type __val = __raw_read##bwlq(mem);				\
	__val = end##_to_cpu(__val);					\
	__val |= set;							\
	__val = cpu_to_##end(__val);					\
	__raw_write##bwlq(__val, mem);					\
}

#define __BUILD_CLRSETBITS(bwlq, sfx, end, type)			\
									\
static inline void clrsetbits_##sfx(volatile void __iomem *mem,		\
					type clr, type set)		\
{									\
	type __val = __raw_read##bwlq(mem);				\
	__val = end##_to_cpu(__val);					\
	__val &= ~clr;							\
	__val |= set;							\
	__val = cpu_to_##end(__val);					\
	__raw_write##bwlq(__val, mem);					\
}

#define BUILD_CLRSETBITS(bwlq, sfx, end, type)				\
									\
__BUILD_CLRBITS(bwlq, sfx, end, type)					\
__BUILD_SETBITS(bwlq, sfx, end, type)					\
__BUILD_CLRSETBITS(bwlq, sfx, end, type)

#define __to_cpu(v)		(v)
#define cpu_to__(v)		(v)

BUILD_CLRSETBITS(b, 8, _, u8)
BUILD_CLRSETBITS(w, le16, le16, u16)
BUILD_CLRSETBITS(w, be16, be16, u16)
BUILD_CLRSETBITS(w, 16, _, u16)
BUILD_CLRSETBITS(l, le32, le32, u32)
BUILD_CLRSETBITS(l, be32, be32, u32)
BUILD_CLRSETBITS(l, 32, _, u32)
BUILD_CLRSETBITS(q, le64, le64, u64)
BUILD_CLRSETBITS(q, be64, be64, u64)
BUILD_CLRSETBITS(q, 64, _, u64)

#endif /* _ASM_IO_H */
Commit	Line	Data
6069ff26	1	/*
6069ff26	2	* Copyright (C) 1994, 1995 Waldorf GmbH
23ff8633	3	* Copyright (C) 1994 - 2000, 06 Ralf Baechle
6069ff26	4	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
23ff8633 DS	5	* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
	6	* Author: Maciej W. Rozycki <macro@mips.com>
	7	*
	8	* SPDX-License-Identifier: GPL-2.0
6069ff26 WD	9	*/
	10	#ifndef _ASM_IO_H
	11	#define _ASM_IO_H
	12
d6ea6d88	13	#include <linux/bug.h>
23ff8633 DS	14	#include <linux/compiler.h>
	15	#include <linux/types.h>
	16
6069ff26 WD	17	#include <asm/addrspace.h>
6069ff26 WD	18	#include <asm/byteorder.h>
23ff8633 DS	19	#include <asm/cpu-features.h>
	20	#include <asm/pgtable-bits.h>
	21	#include <asm/processor.h>
	22	#include <asm/string.h>
	23
	24	#include <ioremap.h>
	25	#include <mangle-port.h>
	26	#include <spaces.h>
6069ff26 WD	27
	28	/*
	29	* Slowdown I/O port space accesses for antique hardware.
	30	*/
	31	#undef CONF_SLOWDOWN_IO
	32
	33	/*
23ff8633 DS	34	* Raw operations are never swapped in software. OTOH values that raw
	35	* operations are working on may or may not have been swapped by the bus
	36	* hardware. An example use would be for flash memory that's used for
	37	* execute in place.
6069ff26	38	*/
23ff8633 DS	39	# define __raw_ioswabb(a, x) (x)
	40	# define __raw_ioswabw(a, x) (x)
	41	# define __raw_ioswabl(a, x) (x)
	42	# define __raw_ioswabq(a, x) (x)
	43	# define ____raw_ioswabq(a, x) (x)
6069ff26	44
23ff8633	45	/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
6069ff26	46
23ff8633	47	#define IO_SPACE_LIMIT 0xffff
6069ff26 WD	48
	49	/*
	50	* On MIPS I/O ports are memory mapped, so we access them using normal
	51	* load/store instructions. mips_io_port_base is the virtual address to
	52	* which all ports are being mapped. For sake of efficiency some code
	53	* assumes that this is an address that can be loaded with a single lui
	54	* instruction, so the lower 16 bits must be zero. Should be true on
	55	* on any sane architecture; generic code does not use this assumption.
	56	*/
5c15010e JCPV	57	extern const unsigned long mips_io_port_base;
	58
	59	/*
	60	* Gcc will generate code to load the value of mips_io_port_base after each
	61	* function call which may be fairly wasteful in some cases. So we don't
	62	* play quite by the book. We tell gcc mips_io_port_base is a long variable
	63	* which solves the code generation issue. Now we need to violate the
	64	* aliasing rules a little to make initialization possible and finally we
	65	* will need the barrier() to fight side effects of the aliasing chat.
	66	* This trickery will eventually collapse under gcc's optimizer. Oh well.
	67	*/
	68	static inline void set_io_port_base(unsigned long base)
	69	{
	70	* (unsigned long *) &mips_io_port_base = base;
23ff8633	71	barrier();
5c15010e	72	}
6069ff26 WD	73
	74	/*
	75	* Thanks to James van Artsdalen for a better timing-fix than
	76	* the two short jumps: using outb's to a nonexistent port seems
	77	* to guarantee better timings even on fast machines.
	78	*
	79	* On the other hand, I'd like to be sure of a non-existent port:
	80	* I feel a bit unsafe about using 0x80 (should be safe, though)
	81	*
	82	* Linus
	83	*
	84	*/
	85
	86	#define __SLOW_DOWN_IO \
	87	__asm__ __volatile__( \
	88	"sb\t$0,0x80(%0)" \
	89	: : "r" (mips_io_port_base));
	90
	91	#ifdef CONF_SLOWDOWN_IO
	92	#ifdef REALLY_SLOW_IO
	93	#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
	94	#else
	95	#define SLOW_DOWN_IO __SLOW_DOWN_IO
	96	#endif
	97	#else
	98	#define SLOW_DOWN_IO
	99	#endif
	100
	101	/*
23ff8633 DS	102	* virt_to_phys - map virtual addresses to physical
	103	* @address: address to remap
	104	*
	105	* The returned physical address is the physical (CPU) mapping for
	106	* the memory address given. It is only valid to use this function on
	107	* addresses directly mapped or allocated via kmalloc.
	108	*
	109	* This function does not give bus mappings for DMA transfers. In
	110	* almost all conceivable cases a device driver should not be using
	111	* this function
6069ff26	112	*/
23ff8633	113	static inline unsigned long virt_to_phys(volatile const void *address)
6069ff26	114	{
23ff8633 DS	115	unsigned long addr = (unsigned long)address;
	116
	117	/* this corresponds to kernel implementation of __pa() */
	118	#ifdef CONFIG_64BIT
	119	if (addr < CKSEG0)
	120	return XPHYSADDR(addr);
	121
	122	return CPHYSADDR(addr);
090854c8	123	#else
23ff8633	124	return addr - PAGE_OFFSET + PHYS_OFFSET;
090854c8	125	#endif
6069ff26 WD	126	}
6069ff26 WD	127
23ff8633 DS	128	/*
	129	* phys_to_virt - map physical address to virtual
	130	* @address: address to remap
	131	*
	132	* The returned virtual address is a current CPU mapping for
	133	* the memory address given. It is only valid to use this function on
	134	* addresses that have a kernel mapping
	135	*
	136	* This function does not handle bus mappings for DMA transfers. In
	137	* almost all conceivable cases a device driver should not be using
	138	* this function
	139	*/
	140	static inline void *phys_to_virt(unsigned long address)
6069ff26	141	{
23ff8633	142	return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
6069ff26 WD	143	}
	144
	145	/*
23ff8633	146	* ISA I/O bus memory addresses are 1:1 with the physical address.
6069ff26	147	*/
23ff8633	148	static inline unsigned long isa_virt_to_bus(volatile void *address)
6069ff26	149	{
23ff8633	150	return (unsigned long)address - PAGE_OFFSET;
6069ff26 WD	151	}
6069ff26 WD	152
23ff8633	153	static inline void *isa_bus_to_virt(unsigned long address)
6069ff26	154	{
23ff8633	155	return (void *)(address + PAGE_OFFSET);
6069ff26 WD	156	}
6069ff26 WD	157
23ff8633 DS	158	#define isa_page_to_bus page_to_phys
23ff8633 DS	159
6069ff26	160	/*
23ff8633 DS	161	* However PCI ones are not necessarily 1:1 and therefore these interfaces
	162	* are forbidden in portable PCI drivers.
	163	*
	164	* Allow them for x86 for legacy drivers, though.
6069ff26	165	*/
23ff8633 DS	166	#define virt_to_bus virt_to_phys
23ff8633 DS	167	#define bus_to_virt phys_to_virt
6069ff26	168
23ff8633 DS	169	static inline void __iomem *__ioremap_mode(phys_addr_t offset, unsigned long size,
23ff8633 DS	170	unsigned long flags)
6069ff26	171	{
23ff8633 DS	172	void __iomem *addr;
23ff8633 DS	173	phys_addr_t phys_addr;
6069ff26	174
23ff8633 DS	175	addr = plat_ioremap(offset, size, flags);
	176	if (addr)
	177	return addr;
6069ff26	178
23ff8633 DS	179	phys_addr = fixup_bigphys_addr(offset, size);
	180	return (void __iomem *)(unsigned long)CKSEG1ADDR(phys_addr);
	181	}
6069ff26 WD	182
6069ff26 WD	183	/*
23ff8633 DS	184	* ioremap - map bus memory into CPU space
	185	* @offset: bus address of the memory
	186	* @size: size of the resource to map
	187	*
	188	* ioremap performs a platform specific sequence of operations to
	189	* make bus memory CPU accessible via the readb/readw/readl/writeb/
	190	* writew/writel functions and the other mmio helpers. The returned
	191	* address is not guaranteed to be usable directly as a virtual
	192	* address.
6069ff26	193	*/
23ff8633 DS	194	#define ioremap(offset, size) \
23ff8633 DS	195	__ioremap_mode((offset), (size), _CACHE_UNCACHED)
6069ff26 WD	196
6069ff26 WD	197	/*
23ff8633 DS	198	* ioremap_nocache - map bus memory into CPU space
	199	* @offset: bus address of the memory
	200	* @size: size of the resource to map
	201	*
	202	* ioremap_nocache performs a platform specific sequence of operations to
	203	* make bus memory CPU accessible via the readb/readw/readl/writeb/
	204	* writew/writel functions and the other mmio helpers. The returned
	205	* address is not guaranteed to be usable directly as a virtual
	206	* address.
	207	*
	208	* This version of ioremap ensures that the memory is marked uncachable
	209	* on the CPU as well as honouring existing caching rules from things like
	210	* the PCI bus. Note that there are other caches and buffers on many
	211	* busses. In particular driver authors should read up on PCI writes
	212	*
	213	* It's useful if some control registers are in such an area and
	214	* write combining or read caching is not desirable:
6069ff26	215	*/
23ff8633 DS	216	#define ioremap_nocache(offset, size) \
	217	__ioremap_mode((offset), (size), _CACHE_UNCACHED)
	218	#define ioremap_uc ioremap_nocache
6069ff26	219
23ff8633 DS	220	/*
	221	* ioremap_cachable - map bus memory into CPU space
	222	* @offset: bus address of the memory
	223	* @size: size of the resource to map
	224	*
	225	* ioremap_nocache performs a platform specific sequence of operations to
	226	* make bus memory CPU accessible via the readb/readw/readl/writeb/
	227	* writew/writel functions and the other mmio helpers. The returned
	228	* address is not guaranteed to be usable directly as a virtual
	229	* address.
	230	*
	231	* This version of ioremap ensures that the memory is marked cachable by
	232	* the CPU. Also enables full write-combining. Useful for some
	233	* memory-like regions on I/O busses.
	234	*/
	235	#define ioremap_cachable(offset, size) \
	236	__ioremap_mode((offset), (size), _page_cachable_default)
6069ff26 WD	237
6069ff26 WD	238	/*
23ff8633 DS	239	* These two are MIPS specific ioremap variant. ioremap_cacheable_cow
	240	* requests a cachable mapping, ioremap_uncached_accelerated requests a
	241	* mapping using the uncached accelerated mode which isn't supported on
	242	* all processors.
6069ff26	243	*/
23ff8633 DS	244	#define ioremap_cacheable_cow(offset, size) \
	245	__ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
	246	#define ioremap_uncached_accelerated(offset, size) \
	247	__ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
6069ff26	248
23ff8633	249	static inline void iounmap(const volatile void __iomem *addr)
6069ff26	250	{
23ff8633	251	plat_iounmap(addr);
6069ff26	252	}
6069ff26	253
23ff8633 DS	254	#ifdef CONFIG_CPU_CAVIUM_OCTEON
	255	#define war_octeon_io_reorder_wmb() wmb()
	256	#else
	257	#define war_octeon_io_reorder_wmb() do { } while (0)
	258	#endif
6069ff26	259
23ff8633 DS	260	#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
	261	\
	262	static inline void pfx##write##bwlq(type val, \
	263	volatile void __iomem *mem) \
	264	{ \
	265	volatile type *__mem; \
	266	type __val; \
	267	\
	268	war_octeon_io_reorder_wmb(); \
	269	\
	270	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
	271	\
	272	__val = pfx##ioswab##bwlq(__mem, val); \
	273	\
	274	if (sizeof(type) != sizeof(u64) \|\| sizeof(u64) == sizeof(long)) \
	275	*__mem = __val; \
	276	else if (cpu_has_64bits) { \
	277	type __tmp; \
	278	\
	279	__asm__ __volatile__( \
	280	".set arch=r4000" "\t\t# __writeq""\n\t" \
	281	"dsll32 %L0, %L0, 0" "\n\t" \
	282	"dsrl32 %L0, %L0, 0" "\n\t" \
	283	"dsll32 %M0, %M0, 0" "\n\t" \
	284	"or %L0, %L0, %M0" "\n\t" \
	285	"sd %L0, %2" "\n\t" \
	286	".set mips0" "\n" \
	287	: "=r" (__tmp) \
	288	: "0" (__val), "m" (*__mem)); \
	289	} else \
	290	BUG(); \
	291	} \
	292	\
	293	static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
	294	{ \
	295	volatile type *__mem; \
	296	type __val; \
	297	\
	298	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
	299	\
	300	if (sizeof(type) != sizeof(u64) \|\| sizeof(u64) == sizeof(long)) \
	301	__val = *__mem; \
	302	else if (cpu_has_64bits) { \
	303	__asm__ __volatile__( \
	304	".set arch=r4000" "\t\t# __readq" "\n\t" \
	305	"ld %L0, %1" "\n\t" \
	306	"dsra32 %M0, %L0, 0" "\n\t" \
	307	"sll %L0, %L0, 0" "\n\t" \
	308	".set mips0" "\n" \
	309	: "=r" (__val) \
	310	: "m" (*__mem)); \
	311	} else { \
	312	__val = 0; \
	313	BUG(); \
	314	} \
	315	\
	316	return pfx##ioswab##bwlq(__mem, __val); \
	317	}
6069ff26	318
23ff8633 DS	319	#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
	320	\
	321	static inline void pfx##out##bwlq##p(type val, unsigned long port) \
	322	{ \
	323	volatile type *__addr; \
	324	type __val; \
	325	\
	326	war_octeon_io_reorder_wmb(); \
	327	\
	328	__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
	329	\
	330	__val = pfx##ioswab##bwlq(__addr, val); \
	331	\
	332	/* Really, we want this to be atomic */ \
	333	BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
	334	\
	335	*__addr = __val; \
	336	slow; \
	337	} \
	338	\
	339	static inline type pfx##in##bwlq##p(unsigned long port) \
	340	{ \
	341	volatile type *__addr; \
	342	type __val; \
	343	\
	344	__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
	345	\
	346	BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
	347	\
	348	__val = *__addr; \
	349	slow; \
	350	\
	351	return pfx##ioswab##bwlq(__addr, __val); \
	352	}
6069ff26	353
23ff8633 DS	354	#define __BUILD_MEMORY_PFX(bus, bwlq, type) \
	355	\
	356	__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
	357
	358	#define BUILDIO_MEM(bwlq, type) \
	359	\
	360	__BUILD_MEMORY_PFX(__raw_, bwlq, type) \
	361	__BUILD_MEMORY_PFX(, bwlq, type) \
	362	__BUILD_MEMORY_PFX(__mem_, bwlq, type) \
	363
	364	BUILDIO_MEM(b, u8)
	365	BUILDIO_MEM(w, u16)
	366	BUILDIO_MEM(l, u32)
	367	BUILDIO_MEM(q, u64)
	368
	369	#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
	370	__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
	371	__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
	372
	373	#define BUILDIO_IOPORT(bwlq, type) \
	374	__BUILD_IOPORT_PFX(, bwlq, type) \
	375	__BUILD_IOPORT_PFX(__mem_, bwlq, type)
	376
	377	BUILDIO_IOPORT(b, u8)
	378	BUILDIO_IOPORT(w, u16)
	379	BUILDIO_IOPORT(l, u32)
	380	#ifdef CONFIG_64BIT
	381	BUILDIO_IOPORT(q, u64)
	382	#endif
6069ff26	383
23ff8633 DS	384	#define __BUILDIO(bwlq, type) \
	385	\
	386	__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
	387
	388	__BUILDIO(q, u64)
	389
	390	#define readb_relaxed readb
	391	#define readw_relaxed readw
	392	#define readl_relaxed readl
	393	#define readq_relaxed readq
	394
	395	#define writeb_relaxed writeb
	396	#define writew_relaxed writew
	397	#define writel_relaxed writel
	398	#define writeq_relaxed writeq
	399
	400	#define readb_be(addr) \
	401	__raw_readb((__force unsigned *)(addr))
	402	#define readw_be(addr) \
	403	be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
	404	#define readl_be(addr) \
	405	be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
	406	#define readq_be(addr) \
	407	be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
	408
	409	#define writeb_be(val, addr) \
	410	__raw_writeb((val), (__force unsigned *)(addr))
	411	#define writew_be(val, addr) \
	412	__raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
	413	#define writel_be(val, addr) \
	414	__raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
	415	#define writeq_be(val, addr) \
	416	__raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
6069ff26 WD	417
6069ff26 WD	418	/*
23ff8633	419	* Some code tests for these symbols
6069ff26	420	*/
23ff8633 DS	421	#define readq readq
	422	#define writeq writeq
	423
	424	#define __BUILD_MEMORY_STRING(bwlq, type) \
	425	\
	426	static inline void writes##bwlq(volatile void __iomem *mem, \
	427	const void *addr, unsigned int count) \
	428	{ \
	429	const volatile type *__addr = addr; \
	430	\
	431	while (count--) { \
	432	__mem_write##bwlq(*__addr, mem); \
	433	__addr++; \
	434	} \
	435	} \
	436	\
	437	static inline void reads##bwlq(volatile void __iomem mem, void addr, \
	438	unsigned int count) \
	439	{ \
	440	volatile type *__addr = addr; \
	441	\
	442	while (count--) { \
	443	*__addr = __mem_read##bwlq(mem); \
	444	__addr++; \
	445	} \
	446	}
6069ff26	447
23ff8633 DS	448	#define __BUILD_IOPORT_STRING(bwlq, type) \
	449	\
	450	static inline void outs##bwlq(unsigned long port, const void *addr, \
	451	unsigned int count) \
	452	{ \
	453	const volatile type *__addr = addr; \
	454	\
	455	while (count--) { \
	456	__mem_out##bwlq(*__addr, port); \
	457	__addr++; \
	458	} \
	459	} \
	460	\
	461	static inline void ins##bwlq(unsigned long port, void *addr, \
	462	unsigned int count) \
	463	{ \
	464	volatile type *__addr = addr; \
	465	\
	466	while (count--) { \
	467	*__addr = __mem_in##bwlq(port); \
	468	__addr++; \
	469	} \
	470	}
6069ff26	471
23ff8633 DS	472	#define BUILDSTRING(bwlq, type) \
	473	\
	474	__BUILD_MEMORY_STRING(bwlq, type) \
	475	__BUILD_IOPORT_STRING(bwlq, type)
6069ff26	476
23ff8633 DS	477	BUILDSTRING(b, u8)
	478	BUILDSTRING(w, u16)
	479	BUILDSTRING(l, u32)
	480	#ifdef CONFIG_64BIT
	481	BUILDSTRING(q, u64)
	482	#endif
6069ff26	483
6069ff26	484
23ff8633 DS	485	#ifdef CONFIG_CPU_CAVIUM_OCTEON
	486	#define mmiowb() wmb()
	487	#else
	488	/* Depends on MIPS II instruction set */
	489	#define mmiowb() asm volatile ("sync" ::: "memory")
	490	#endif
6069ff26	491
23ff8633 DS	492	static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
	493	{
	494	memset((void __force *)addr, val, count);
	495	}
	496	static inline void memcpy_fromio(void dst, const volatile void __iomem src, int count)
	497	{
	498	memcpy(dst, (void __force *)src, count);
	499	}
	500	static inline void memcpy_toio(volatile void __iomem dst, const void src, int count)
3a197b2f	501	{
23ff8633	502	memcpy((void __force *)dst, src, count);
3a197b2f HW	503	}
3a197b2f HW	504
4d7d6936	505	/*
23ff8633 DS	506	* Read a 32-bit register that requires a 64-bit read cycle on the bus.
	507	* Avoid interrupt mucking, just adjust the address for 4-byte access.
	508	* Assume the addresses are 8-byte aligned.
4d7d6936	509	*/
23ff8633 DS	510	#ifdef __MIPSEB__
	511	#define __CSR_32_ADJUST 4
	512	#else
	513	#define __CSR_32_ADJUST 0
	514	#endif
	515
	516	#define csr_out32(v, a) ((volatile u32 )((unsigned long)(a) + __CSR_32_ADJUST) = (v))
	517	#define csr_in32(a) ((volatile u32 )((unsigned long)(a) + __CSR_32_ADJUST))
	518
	519	/*
	520	* U-Boot specific
	521	*/
	522	#define sync() mmiowb()
	523
	524	#define MAP_NOCACHE (1)
4d7d6936 HS	525	#define MAP_WRCOMBINE (0)
	526	#define MAP_WRBACK (0)
	527	#define MAP_WRTHROUGH (0)
	528
	529	static inline void *
	530	map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
	531	{
23ff8633 DS	532	if (flags == MAP_NOCACHE)
	533	return ioremap(paddr, len);
	534
4d7d6936 HS	535	return (void *)paddr;
	536	}
	537
	538	/*
	539	* Take down a mapping set up by map_physmem().
	540	*/
	541	static inline void unmap_physmem(void *vaddr, unsigned long flags)
	542	{
4d7d6936 HS	543	}
4d7d6936 HS	544
0e0efb40 DS	545	#define __BUILD_CLRBITS(bwlq, sfx, end, type) \
	546	\
	547	static inline void clrbits_##sfx(volatile void __iomem *mem, type clr) \
	548	{ \
	549	type __val = __raw_read##bwlq(mem); \
	550	__val = end##_to_cpu(__val); \
	551	__val &= ~clr; \
	552	__val = cpu_to_##end(__val); \
	553	__raw_write##bwlq(__val, mem); \
	554	}
	555
	556	#define __BUILD_SETBITS(bwlq, sfx, end, type) \
	557	\
	558	static inline void setbits_##sfx(volatile void __iomem *mem, type set) \
	559	{ \
	560	type __val = __raw_read##bwlq(mem); \
	561	__val = end##_to_cpu(__val); \
	562	__val \|= set; \
	563	__val = cpu_to_##end(__val); \
	564	__raw_write##bwlq(__val, mem); \
	565	}
	566
	567	#define __BUILD_CLRSETBITS(bwlq, sfx, end, type) \
	568	\
	569	static inline void clrsetbits_##sfx(volatile void __iomem *mem, \
	570	type clr, type set) \
	571	{ \
	572	type __val = __raw_read##bwlq(mem); \
	573	__val = end##_to_cpu(__val); \
	574	__val &= ~clr; \
	575	__val \|= set; \
	576	__val = cpu_to_##end(__val); \
	577	__raw_write##bwlq(__val, mem); \
	578	}
	579
	580	#define BUILD_CLRSETBITS(bwlq, sfx, end, type) \
	581	\
	582	__BUILD_CLRBITS(bwlq, sfx, end, type) \
	583	__BUILD_SETBITS(bwlq, sfx, end, type) \
	584	__BUILD_CLRSETBITS(bwlq, sfx, end, type)
	585
	586	#define __to_cpu(v) (v)
	587	#define cpu_to__(v) (v)
	588
	589	BUILD_CLRSETBITS(b, 8, _, u8)
	590	BUILD_CLRSETBITS(w, le16, le16, u16)
	591	BUILD_CLRSETBITS(w, be16, be16, u16)
	592	BUILD_CLRSETBITS(w, 16, _, u16)
	593	BUILD_CLRSETBITS(l, le32, le32, u32)
	594	BUILD_CLRSETBITS(l, be32, be32, u32)
	595	BUILD_CLRSETBITS(l, 32, _, u32)
	596	BUILD_CLRSETBITS(q, le64, le64, u64)
	597	BUILD_CLRSETBITS(q, be64, be64, u64)
	598	BUILD_CLRSETBITS(q, 64, _, u64)
	599
6069ff26	600	#endif /* _ASM_IO_H */