projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5a4dcfac GJ |
1 | /* |
| 2 | * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> | |
| a3e80904 | 3 | * Copyright (C) 2013 Imagination Technologies |
| 5a4dcfac | 4 | * |
| a3e80904 | 5 | * SPDX-License-Identifier: GPL-2.0 |
| 5a4dcfac GJ |
6 | */ |
| 7 | ||
| 8 | #ifndef _MIPS_ASM_MALTA_H | |
| 9 | #define _MIPS_ASM_MALTA_H | |
| 10 | ||
| baf37f06 PB |
11 | #define MALTA_GT_BASE 0x1be00000 |
| 12 | #define MALTA_GT_PCIIO_BASE 0x18000000 | |
| 13 | #define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8) | |
| 5a4dcfac | 14 | |
| baf37f06 PB |
15 | #define MALTA_MSC01_BIU_BASE 0x1bc80000 |
| 16 | #define MALTA_MSC01_PCI_BASE 0x1bd00000 | |
| 17 | #define MALTA_MSC01_PBC_BASE 0x1bd40000 | |
| 18 | #define MALTA_MSC01_IP1_BASE 0x1bc00000 | |
| 19 | #define MALTA_MSC01_IP1_SIZE 0x00400000 | |
| 20 | #define MALTA_MSC01_IP2_BASE1 0x10000000 | |
| 21 | #define MALTA_MSC01_IP2_SIZE1 0x08000000 | |
| 22 | #define MALTA_MSC01_IP2_BASE2 0x18000000 | |
| 23 | #define MALTA_MSC01_IP2_SIZE2 0x04000000 | |
| 24 | #define MALTA_MSC01_IP3_BASE 0x1c000000 | |
| 25 | #define MALTA_MSC01_IP3_SIZE 0x04000000 | |
| 26 | #define MALTA_MSC01_PCIMEM_BASE 0x10000000 | |
| 27 | #define MALTA_MSC01_PCIMEM_SIZE 0x10000000 | |
| 28 | #define MALTA_MSC01_PCIMEM_MAP 0x10000000 | |
| 29 | #define MALTA_MSC01_PCIIO_BASE 0x1b000000 | |
| 30 | #define MALTA_MSC01_PCIIO_SIZE 0x00800000 | |
| 31 | #define MALTA_MSC01_PCIIO_MAP 0x00000000 | |
| 32 | #define MALTA_MSC01_UART0_BASE (MALTA_MSC01_PCIIO_BASE + 0x3f8) | |
| 5a4dcfac | 33 | |
| e0ada631 PB |
34 | #define MALTA_ASCIIWORD 0x1f000410 |
| 35 | #define MALTA_ASCIIPOS0 0x1f000418 | |
| 36 | #define MALTA_ASCIIPOS1 0x1f000420 | |
| 37 | #define MALTA_ASCIIPOS2 0x1f000428 | |
| 38 | #define MALTA_ASCIIPOS3 0x1f000430 | |
| 39 | #define MALTA_ASCIIPOS4 0x1f000438 | |
| 40 | #define MALTA_ASCIIPOS5 0x1f000440 | |
| 41 | #define MALTA_ASCIIPOS6 0x1f000448 | |
| 42 | #define MALTA_ASCIIPOS7 0x1f000450 | |
| 43 | ||
| baf37f06 PB |
44 | #define MALTA_RESET_BASE 0x1f000500 |
| 45 | #define GORESET 0x42 | |
| ac12984d | 46 | |
| 10473d04 | 47 | #define MALTA_FLASH_BASE 0x1e000000 |
| 01564315 | 48 | |
| baf37f06 PB |
49 | #define MALTA_REVISION 0x1fc00010 |
| 50 | #define MALTA_REVISION_CORID_SHF 10 | |
| 51 | #define MALTA_REVISION_CORID_MSK (0x3f << MALTA_REVISION_CORID_SHF) | |
| 52 | #define MALTA_REVISION_CORID_CORE_LV 1 | |
| 53 | #define MALTA_REVISION_CORID_CORE_FPGA6 14 | |
| 52caee0f | 54 | |
| 81f98bbd PB |
55 | #define PCI_CFG_PIIX4_PIRQRCA 0x60 |
| 56 | #define PCI_CFG_PIIX4_PIRQRCB 0x61 | |
| 57 | #define PCI_CFG_PIIX4_PIRQRCC 0x62 | |
| 58 | #define PCI_CFG_PIIX4_PIRQRCD 0x63 | |
| bea12b78 PB |
59 | #define PCI_CFG_PIIX4_SERIRQC 0x64 |
| 60 | #define PCI_CFG_PIIX4_GENCFG 0xb0 | |
| 61 | ||
| 62 | #define PCI_CFG_PIIX4_SERIRQC_EN (1 << 7) | |
| 63 | #define PCI_CFG_PIIX4_SERIRQC_CONT (1 << 6) | |
| 64 | ||
| 65 | #define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16) | |
| 81f98bbd | 66 | |
| 5a4dcfac | 67 | #endif /* _MIPS_ASM_MALTA_H */ |