[people/ms/u-boot.git] / arch / mips / mach-ath79 / reset.c

/*
 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

#include <common.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ath79.h>
#include <mach/ar71xx_regs.h>

void _machine_restart(void)
{
	void __iomem *base;
	u32 reg = 0;

	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
			   MAP_NOCACHE);
	if (soc_is_ar71xx())
		reg = AR71XX_RESET_REG_RESET_MODULE;
	else if (soc_is_ar724x())
		reg = AR724X_RESET_REG_RESET_MODULE;
	else if (soc_is_ar913x())
		reg = AR913X_RESET_REG_RESET_MODULE;
	else if (soc_is_ar933x())
		reg = AR933X_RESET_REG_RESET_MODULE;
	else if (soc_is_ar934x())
		reg = AR934X_RESET_REG_RESET_MODULE;
	else if (soc_is_qca953x())
		reg = QCA953X_RESET_REG_RESET_MODULE;
	else if (soc_is_qca955x())
		reg = QCA955X_RESET_REG_RESET_MODULE;
	else if (soc_is_qca956x())
		reg = QCA956X_RESET_REG_RESET_MODULE;
	else
		puts("Reset register not defined for this SOC\n");

	if (reg)
		setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP);

	while (1)
		/* NOP */;
}

u32 get_bootstrap(void)
{
	void __iomem *base;
	u32 reg = 0;

	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
			   MAP_NOCACHE);
	if (soc_is_ar933x())
		reg = AR933X_RESET_REG_BOOTSTRAP;
	else if (soc_is_ar934x())
		reg = AR934X_RESET_REG_BOOTSTRAP;
	else if (soc_is_qca953x())
		reg = QCA953X_RESET_REG_BOOTSTRAP;
	else if (soc_is_qca955x())
		reg = QCA955X_RESET_REG_BOOTSTRAP;
	else if (soc_is_qca956x())
		reg = QCA956X_RESET_REG_BOOTSTRAP;
	else
		puts("Bootstrap register not defined for this SOC\n");

	if (reg)
		return readl(base + reg);

	return 0;
}

static int eth_init_ar933x(void)
{
	void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
					  MAP_NOCACHE);
	void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
					  MAP_NOCACHE);
	void __iomem *gregs = map_physmem(AR933X_GMAC_BASE, AR933X_GMAC_SIZE,
					  MAP_NOCACHE);
	const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
			 AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
			 AR933X_RESET_ETH_SWITCH;

	/* Clear MDIO slave EN bit. */
	clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
	mdelay(10);

	/* Get Atheros S26 PHY out of reset. */
	clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
			0x1f, 0x10);
	mdelay(10);

	setbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
	mdelay(10);
	clrbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
	mdelay(10);

	/* Configure AR93xx GMAC register. */
	clrsetbits_be32(gregs + AR933X_GMAC_REG_ETH_CFG,
			AR933X_ETH_CFG_MII_GE0_MASTER |
			AR933X_ETH_CFG_MII_GE0_SLAVE,
			AR933X_ETH_CFG_MII_GE0_SLAVE);
	return 0;
}

static int eth_init_ar934x(void)
{
	void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
					  MAP_NOCACHE);
	void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
					  MAP_NOCACHE);
	void __iomem *gregs = map_physmem(AR934X_GMAC_BASE, AR934X_GMAC_SIZE,
					  MAP_NOCACHE);
	const u32 mask = AR934X_RESET_GE0_MAC | AR934X_RESET_GE0_MDIO |
			 AR934X_RESET_GE1_MAC | AR934X_RESET_GE1_MDIO |
			 AR934X_RESET_ETH_SWITCH_ANALOG;
	u32 reg;

	reg = readl(rregs + AR934X_RESET_REG_BOOTSTRAP);
	if (reg & AR934X_BOOTSTRAP_REF_CLK_40)
		writel(0x570, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
	else
		writel(0x271, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
	writel(BIT(26) | BIT(25), pregs + AR934X_PLL_ETH_XMII_CONTROL_REG);

	setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
	mdelay(1);
	clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
	mdelay(1);

	/* Configure AR934x GMAC register. */
	writel(AR934X_ETH_CFG_RGMII_GMAC0, gregs + AR934X_GMAC_REG_ETH_CFG);
	return 0;
}

int ath79_eth_reset(void)
{
	/*
	 * Un-reset ethernet. DM still doesn't have any notion of reset
	 * framework, so we do it by hand here.
	 */
	if (soc_is_ar933x())
		return eth_init_ar933x();
	if (soc_is_ar934x())
		return eth_init_ar934x();

	return -EINVAL;
}

static int usb_reset_ar933x(void __iomem *reset_regs)
{
	/* Ungate the USB block */
	setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
		     AR933X_RESET_USBSUS_OVERRIDE);
	mdelay(1);
	clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
		     AR933X_RESET_USB_HOST);
	mdelay(1);
	clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
		     AR933X_RESET_USB_PHY);
	mdelay(1);

	return 0;
}

static int usb_reset_ar934x(void __iomem *reset_regs)
{
	/* Ungate the USB block */
	setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
		     AR934X_RESET_USBSUS_OVERRIDE);
	mdelay(1);
	clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
		     AR934X_RESET_USB_PHY);
	mdelay(1);
	clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
		     AR934X_RESET_USB_PHY_ANALOG);
	mdelay(1);
	clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
		     AR934X_RESET_USB_HOST);
	mdelay(1);

	return 0;
}

int ath79_usb_reset(void)
{
	void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
					      AR71XX_USB_CTRL_SIZE,
					      MAP_NOCACHE);
	void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE,
					       AR71XX_RESET_SIZE,
					       MAP_NOCACHE);
	/*
	 * Turn on the Buff and Desc swap bits.
	 * NOTE: This write into an undocumented register in mandatory to
	 *       get the USB controller operational in BigEndian mode.
	 */
	writel(0xf0000, usbc_regs + AR71XX_USB_CTRL_REG_CONFIG);

	if (soc_is_ar933x())
		return usb_reset_ar933x(reset_regs);
	if (soc_is_ar934x())
		return usb_reset_ar934x(reset_regs);

	return -EINVAL;
}
Commit	Line	Data
1d3d0f1f WW	1	/*
	2	* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
6b699742	8	#include <asm/errno.h>
1d3d0f1f WW	9	#include <asm/io.h>
	10	#include <asm/addrspace.h>
	11	#include <asm/types.h>
	12	#include <mach/ath79.h>
	13	#include <mach/ar71xx_regs.h>
	14
	15	void _machine_restart(void)
	16	{
	17	void __iomem *base;
	18	u32 reg = 0;
	19
	20	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
	21	MAP_NOCACHE);
	22	if (soc_is_ar71xx())
	23	reg = AR71XX_RESET_REG_RESET_MODULE;
	24	else if (soc_is_ar724x())
	25	reg = AR724X_RESET_REG_RESET_MODULE;
	26	else if (soc_is_ar913x())
	27	reg = AR913X_RESET_REG_RESET_MODULE;
	28	else if (soc_is_ar933x())
	29	reg = AR933X_RESET_REG_RESET_MODULE;
	30	else if (soc_is_ar934x())
	31	reg = AR934X_RESET_REG_RESET_MODULE;
	32	else if (soc_is_qca953x())
	33	reg = QCA953X_RESET_REG_RESET_MODULE;
	34	else if (soc_is_qca955x())
	35	reg = QCA955X_RESET_REG_RESET_MODULE;
	36	else if (soc_is_qca956x())
	37	reg = QCA956X_RESET_REG_RESET_MODULE;
	38	else
	39	puts("Reset register not defined for this SOC\n");
	40
	41	if (reg)
	42	setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP);
	43
	44	while (1)
	45	/* NOP */;
	46	}
	47
	48	u32 get_bootstrap(void)
	49	{
43a092ff	50	void __iomem *base;
1d3d0f1f WW	51	u32 reg = 0;
	52
	53	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
	54	MAP_NOCACHE);
	55	if (soc_is_ar933x())
	56	reg = AR933X_RESET_REG_BOOTSTRAP;
	57	else if (soc_is_ar934x())
	58	reg = AR934X_RESET_REG_BOOTSTRAP;
	59	else if (soc_is_qca953x())
	60	reg = QCA953X_RESET_REG_BOOTSTRAP;
	61	else if (soc_is_qca955x())
	62	reg = QCA955X_RESET_REG_BOOTSTRAP;
	63	else if (soc_is_qca956x())
	64	reg = QCA956X_RESET_REG_BOOTSTRAP;
	65	else
	66	puts("Bootstrap register not defined for this SOC\n");
	67
	68	if (reg)
	69	return readl(base + reg);
	70
	71	return 0;
	72	}
6b699742	73
4771bbee MV	74	static int eth_init_ar933x(void)
	75	{
	76	void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
	77	MAP_NOCACHE);
	78	void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
	79	MAP_NOCACHE);
	80	void __iomem *gregs = map_physmem(AR933X_GMAC_BASE, AR933X_GMAC_SIZE,
	81	MAP_NOCACHE);
	82	const u32 mask = AR933X_RESET_GE0_MAC \| AR933X_RESET_GE0_MDIO \|
	83	AR933X_RESET_GE1_MAC \| AR933X_RESET_GE1_MDIO \|
	84	AR933X_RESET_ETH_SWITCH;
	85
	86	/* Clear MDIO slave EN bit. */
	87	clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
	88	mdelay(10);
	89
	90	/* Get Atheros S26 PHY out of reset. */
	91	clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
	92	0x1f, 0x10);
	93	mdelay(10);
	94
	95	setbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
	96	mdelay(10);
	97	clrbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
	98	mdelay(10);
	99
	100	/* Configure AR93xx GMAC register. */
	101	clrsetbits_be32(gregs + AR933X_GMAC_REG_ETH_CFG,
	102	AR933X_ETH_CFG_MII_GE0_MASTER \|
	103	AR933X_ETH_CFG_MII_GE0_SLAVE,
	104	AR933X_ETH_CFG_MII_GE0_SLAVE);
	105	return 0;
	106	}
	107
	108	static int eth_init_ar934x(void)
	109	{
	110	void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
	111	MAP_NOCACHE);
	112	void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
	113	MAP_NOCACHE);
	114	void __iomem *gregs = map_physmem(AR934X_GMAC_BASE, AR934X_GMAC_SIZE,
	115	MAP_NOCACHE);
	116	const u32 mask = AR934X_RESET_GE0_MAC \| AR934X_RESET_GE0_MDIO \|
	117	AR934X_RESET_GE1_MAC \| AR934X_RESET_GE1_MDIO \|
	118	AR934X_RESET_ETH_SWITCH_ANALOG;
	119	u32 reg;
	120
	121	reg = readl(rregs + AR934X_RESET_REG_BOOTSTRAP);
	122	if (reg & AR934X_BOOTSTRAP_REF_CLK_40)
	123	writel(0x570, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
	124	else
	125	writel(0x271, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
	126	writel(BIT(26) \| BIT(25), pregs + AR934X_PLL_ETH_XMII_CONTROL_REG);
	127
	128	setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
	129	mdelay(1);
	130	clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
	131	mdelay(1);
	132
	133	/* Configure AR934x GMAC register. */
	134	writel(AR934X_ETH_CFG_RGMII_GMAC0, gregs + AR934X_GMAC_REG_ETH_CFG);
	135	return 0;
	136	}
	137
138	int ath79_eth_reset(void)
139	{
140	/*
141	* Un-reset ethernet. DM still doesn't have any notion of reset
142	* framework, so we do it by hand here.
143	*/
144	if (soc_is_ar933x())
145	return eth_init_ar933x();
146	if (soc_is_ar934x())
147	return eth_init_ar934x();
148
149	return -EINVAL;
150	}
151
6b699742 MV	152	static int usb_reset_ar933x(void __iomem *reset_regs)
	153	{
	154	/* Ungate the USB block */
	155	setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
	156	AR933X_RESET_USBSUS_OVERRIDE);
	157	mdelay(1);
	158	clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
	159	AR933X_RESET_USB_HOST);
	160	mdelay(1);
	161	clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
	162	AR933X_RESET_USB_PHY);
	163	mdelay(1);
	164
	165	return 0;
	166	}
	167
	168	static int usb_reset_ar934x(void __iomem *reset_regs)
	169	{
	170	/* Ungate the USB block */
	171	setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
	172	AR934X_RESET_USBSUS_OVERRIDE);
	173	mdelay(1);
	174	clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
	175	AR934X_RESET_USB_PHY);
	176	mdelay(1);
	177	clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
	178	AR934X_RESET_USB_PHY_ANALOG);
	179	mdelay(1);
	180	clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
	181	AR934X_RESET_USB_HOST);
	182	mdelay(1);
	183
	184	return 0;
	185	}
	186
	187	int ath79_usb_reset(void)
	188	{
	189	void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
	190	AR71XX_USB_CTRL_SIZE,
	191	MAP_NOCACHE);
	192	void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE,
	193	AR71XX_RESET_SIZE,
	194	MAP_NOCACHE);
	195	/*
	196	* Turn on the Buff and Desc swap bits.
	197	* NOTE: This write into an undocumented register in mandatory to
	198	* get the USB controller operational in BigEndian mode.
	199	*/
	200	writel(0xf0000, usbc_regs + AR71XX_USB_CTRL_REG_CONFIG);
	201
	202	if (soc_is_ar933x())
	203	return usb_reset_ar933x(reset_regs);
	204	if (soc_is_ar934x())
	205	return usb_reset_ar934x(reset_regs);
	206
	207	return -EINVAL;
	208	}