[thirdparty/kernel/stable.git] / arch / mips / ralink / rt288x.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *
 * Parts of this file are based on Ralink's 2.6.21 BSP
 *
 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 * Copyright (C) 2013 John Crispin <john@phrozen.org>
 */

#include <linux/kernel.h>
#include <linux/init.h>

#include <asm/mipsregs.h>
#include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/rt288x.h>
#include <asm/mach-ralink/pinmux.h>

#include "common.h"

static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) };
static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) };

static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
	GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
	GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
	GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
	GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
	GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
	GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
	GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
	{ 0 }
};

void __init ralink_clk_init(void)
{
	unsigned long cpu_rate, wmac_rate = 40000000;
	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
	t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);

	switch (t) {
	case SYSTEM_CONFIG_CPUCLK_250:
		cpu_rate = 250000000;
		break;
	case SYSTEM_CONFIG_CPUCLK_266:
		cpu_rate = 266666667;
		break;
	case SYSTEM_CONFIG_CPUCLK_280:
		cpu_rate = 280000000;
		break;
	case SYSTEM_CONFIG_CPUCLK_300:
		cpu_rate = 300000000;
		break;
	}

	ralink_clk_add("cpu", cpu_rate);
	ralink_clk_add("300100.timer", cpu_rate / 2);
	ralink_clk_add("300120.watchdog", cpu_rate / 2);
	ralink_clk_add("300500.uart", cpu_rate / 2);
	ralink_clk_add("300900.i2c", cpu_rate / 2);
	ralink_clk_add("300c00.uartlite", cpu_rate / 2);
	ralink_clk_add("400000.ethernet", cpu_rate / 2);
	ralink_clk_add("480000.wmac", wmac_rate);
}

void __init ralink_of_remap(void)
{
	rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
	rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");

	if (!rt_sysc_membase || !rt_memc_membase)
		panic("Failed to remap core resources");
}

void prom_soc_init(struct ralink_soc_info *soc_info)
{
	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
	const char *name;
	u32 n0;
	u32 n1;
	u32 id;

	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
	id = __raw_readl(sysc + SYSC_REG_CHIP_ID);

	if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
		soc_info->compatible = "ralink,r2880-soc";
		name = "RT2880";
	} else {
		panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
	}

	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
		"Ralink %s id:%u rev:%u",
		name,
		(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
		(id & CHIP_ID_REV_MASK));

	soc_info->mem_base = RT2880_SDRAM_BASE;
	soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
	soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;

	rt2880_pinmux_data = rt2880_pinmux_data_act;
	ralink_soc = RT2880_SOC;
}
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
80fb55a9	2	/*
80fb55a9 JC	3	*
	4	* Parts of this file are based on Ralink's 2.6.21 BSP
	5	*
	6	* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
	7	* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
97b92108	8	* Copyright (C) 2013 John Crispin <john@phrozen.org>
80fb55a9 JC	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
80fb55a9 JC	13
	14	#include <asm/mipsregs.h>
	15	#include <asm/mach-ralink/ralink_regs.h>
	16	#include <asm/mach-ralink/rt288x.h>
f576fb6a	17	#include <asm/mach-ralink/pinmux.h>
80fb55a9 JC	18
	19	#include "common.h"
	20
f576fb6a JC	21	static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
	22	static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
	23	static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) };
	24	static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
	25	static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
	26	static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
	27	static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) };
	28
	29	static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
	30	GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
	31	GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
	32	GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
	33	GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
	34	GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
	35	GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
	36	GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
	37	{ 0 }
80fb55a9 JC	38	};
80fb55a9 JC	39
80fb55a9 JC	40	void __init ralink_clk_init(void)
80fb55a9 JC	41	{
f2a8bd2e	42	unsigned long cpu_rate, wmac_rate = 40000000;
80fb55a9 JC	43	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
	44	t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
	45
	46	switch (t) {
	47	case SYSTEM_CONFIG_CPUCLK_250:
	48	cpu_rate = 250000000;
	49	break;
	50	case SYSTEM_CONFIG_CPUCLK_266:
	51	cpu_rate = 266666667;
	52	break;
	53	case SYSTEM_CONFIG_CPUCLK_280:
	54	cpu_rate = 280000000;
	55	break;
	56	case SYSTEM_CONFIG_CPUCLK_300:
	57	cpu_rate = 300000000;
	58	break;
	59	}
	60
	61	ralink_clk_add("cpu", cpu_rate);
	62	ralink_clk_add("300100.timer", cpu_rate / 2);
	63	ralink_clk_add("300120.watchdog", cpu_rate / 2);
	64	ralink_clk_add("300500.uart", cpu_rate / 2);
2517caf1	65	ralink_clk_add("300900.i2c", cpu_rate / 2);
80fb55a9 JC	66	ralink_clk_add("300c00.uartlite", cpu_rate / 2);
80fb55a9 JC	67	ralink_clk_add("400000.ethernet", cpu_rate / 2);
f2a8bd2e	68	ralink_clk_add("480000.wmac", wmac_rate);
80fb55a9 JC	69	}
	70
	71	void __init ralink_of_remap(void)
	72	{
	73	rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
	74	rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
	75
	76	if (!rt_sysc_membase \|\| !rt_memc_membase)
	77	panic("Failed to remap core resources");
	78	}
	79
	80	void prom_soc_init(struct ralink_soc_info *soc_info)
	81	{
	82	void __iomem sysc = (void __iomem ) KSEG1ADDR(RT2880_SYSC_BASE);
	83	const char *name;
	84	u32 n0;
	85	u32 n1;
	86	u32 id;
	87
	88	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
	89	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
	90	id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
	91
	92	if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
	93	soc_info->compatible = "ralink,r2880-soc";
	94	name = "RT2880";
	95	} else {
	96	panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
	97	}
	98
	99	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
	100	"Ralink %s id:%u rev:%u",
	101	name,
	102	(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
	103	(id & CHIP_ID_REV_MASK));
38d5b81c JC	104
	105	soc_info->mem_base = RT2880_SDRAM_BASE;
	106	soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
	107	soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
f576fb6a JC	108
f576fb6a JC	109	rt2880_pinmux_data = rt2880_pinmux_data_act;
0af3a40f	110	ralink_soc = RT2880_SOC;
80fb55a9	111	}