[thirdparty/linux.git] / arch / mips / vr41xx / common / pmu.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  pmu.c, Power Management Unit routines for NEC VR4100 series.
 *
 *  Copyright (C) 2003-2007  Yoichi Yuasa <yuasa@linux-mips.org>
 */
#include <linux/cpu.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/pm.h>
#include <linux/sched.h>
#include <linux/types.h>

#include <asm/cacheflush.h>
#include <asm/cpu.h>
#include <asm/idle.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/reboot.h>

#define PMU_TYPE1_BASE	0x0b0000a0UL
#define PMU_TYPE1_SIZE	0x0eUL

#define PMU_TYPE2_BASE	0x0f0000c0UL
#define PMU_TYPE2_SIZE	0x10UL

#define PMUCNT2REG	0x06
 #define SOFTRST	0x0010

static void __iomem *pmu_base;

#define pmu_read(offset)		readw(pmu_base + (offset))
#define pmu_write(offset, value)	writew((value), pmu_base + (offset))

static void __cpuidle vr41xx_cpu_wait(void)
{
	local_irq_disable();
	if (!need_resched())
		/*
		 * "standby" sets IE bit of the CP0_STATUS to 1.
		 */
		__asm__("standby;\n");
	else
		local_irq_enable();
}

static inline void software_reset(void)
{
	uint16_t pmucnt2;

	switch (current_cpu_type()) {
	case CPU_VR4122:
	case CPU_VR4131:
	case CPU_VR4133:
		pmucnt2 = pmu_read(PMUCNT2REG);
		pmucnt2 |= SOFTRST;
		pmu_write(PMUCNT2REG, pmucnt2);
		break;
	default:
		set_c0_status(ST0_BEV | ST0_ERL);
		change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
		__flush_cache_all();
		write_c0_wired(0);
		__asm__("jr	%0"::"r"(0xbfc00000));
		break;
	}
}

static void vr41xx_restart(char *command)
{
	local_irq_disable();
	software_reset();
	while (1) ;
}

static void vr41xx_halt(void)
{
	local_irq_disable();
	printk(KERN_NOTICE "\nYou can turn off the power supply\n");
	__asm__("hibernate;\n");
}

static int __init vr41xx_pmu_init(void)
{
	unsigned long start, size;

	switch (current_cpu_type()) {
	case CPU_VR4111:
	case CPU_VR4121:
		start = PMU_TYPE1_BASE;
		size = PMU_TYPE1_SIZE;
		break;
	case CPU_VR4122:
	case CPU_VR4131:
	case CPU_VR4133:
		start = PMU_TYPE2_BASE;
		size = PMU_TYPE2_SIZE;
		break;
	default:
		printk("Unexpected CPU of NEC VR4100 series\n");
		return -ENODEV;
	}

	if (request_mem_region(start, size, "PMU") == NULL)
		return -EBUSY;

	pmu_base = ioremap(start, size);
	if (pmu_base == NULL) {
		release_mem_region(start, size);
		return -EBUSY;
	}

	cpu_wait = vr41xx_cpu_wait;
	_machine_restart = vr41xx_restart;
	_machine_halt = vr41xx_halt;
	pm_power_off = vr41xx_halt;

	return 0;
}

core_initcall(vr41xx_pmu_init);
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 LT	2	/*
	3	* pmu.c, Power Management Unit routines for NEC VR4100 series.
	4	*
ada8e951	5	* Copyright (C) 2003-2007 Yoichi Yuasa <yuasa@linux-mips.org>
1da177e4	6	*/
97c8580e	7	#include <linux/cpu.h>
3407c0fe	8	#include <linux/errno.h>
1da177e4	9	#include <linux/init.h>
3407c0fe	10	#include <linux/ioport.h>
1da177e4	11	#include <linux/kernel.h>
fcdb27ad	12	#include <linux/pm.h>
61a33168	13	#include <linux/sched.h>
1da177e4 LT	14	#include <linux/types.h>
1da177e4 LT	15
2f2a2d99	16	#include <asm/cacheflush.h>
1da177e4	17	#include <asm/cpu.h>
bdc92d74	18	#include <asm/idle.h>
1da177e4	19	#include <asm/io.h>
61a33168	20	#include <asm/processor.h>
1da177e4	21	#include <asm/reboot.h>
1da177e4	22
3407c0fe YY	23	#define PMU_TYPE1_BASE 0x0b0000a0UL
	24	#define PMU_TYPE1_SIZE 0x0eUL
	25
	26	#define PMU_TYPE2_BASE 0x0f0000c0UL
	27	#define PMU_TYPE2_SIZE 0x10UL
	28
	29	#define PMUCNT2REG 0x06
1da177e4 LT	30	#define SOFTRST 0x0010
1da177e4 LT	31
3407c0fe YY	32	static void __iomem *pmu_base;
	33
	34	#define pmu_read(offset) readw(pmu_base + (offset))
	35	#define pmu_write(offset, value) writew((value), pmu_base + (offset))
	36
97c8580e	37	static void __cpuidle vr41xx_cpu_wait(void)
61a33168 YY	38	{
	39	local_irq_disable();
	40	if (!need_resched())
	41	/*
	42	* "standby" sets IE bit of the CP0_STATUS to 1.
	43	*/
	44	__asm__("standby;\n");
	45	else
	46	local_irq_enable();
	47	}
	48
1da177e4 LT	49	static inline void software_reset(void)
1da177e4 LT	50	{
3407c0fe	51	uint16_t pmucnt2;
1da177e4	52
10cc3529	53	switch (current_cpu_type()) {
1da177e4 LT	54	case CPU_VR4122:
	55	case CPU_VR4131:
	56	case CPU_VR4133:
3407c0fe YY	57	pmucnt2 = pmu_read(PMUCNT2REG);
	58	pmucnt2 \|= SOFTRST;
	59	pmu_write(PMUCNT2REG, pmucnt2);
1da177e4 LT	60	break;
1da177e4 LT	61	default:
2f2a2d99 YY	62	set_c0_status(ST0_BEV \| ST0_ERL);
2f2a2d99 YY	63	change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
a48ac3a1	64	__flush_cache_all();
2f2a2d99	65	write_c0_wired(0);
70342287	66	__asm__("jr %0"::"r"(0xbfc00000));
1da177e4 LT	67	break;
	68	}
	69	}
	70
	71	static void vr41xx_restart(char *command)
	72	{
	73	local_irq_disable();
	74	software_reset();
1da177e4 LT	75	while (1) ;
	76	}
	77
	78	static void vr41xx_halt(void)
	79	{
	80	local_irq_disable();
	81	printk(KERN_NOTICE "\nYou can turn off the power supply\n");
fa417806	82	__asm__("hibernate;\n");
1da177e4 LT	83	}
	84
	85	static int __init vr41xx_pmu_init(void)
	86	{
3407c0fe YY	87	unsigned long start, size;
3407c0fe YY	88
10cc3529	89	switch (current_cpu_type()) {
3407c0fe YY	90	case CPU_VR4111:
	91	case CPU_VR4121:
	92	start = PMU_TYPE1_BASE;
	93	size = PMU_TYPE1_SIZE;
	94	break;
	95	case CPU_VR4122:
	96	case CPU_VR4131:
	97	case CPU_VR4133:
	98	start = PMU_TYPE2_BASE;
	99	size = PMU_TYPE2_SIZE;
	100	break;
	101	default:
	102	printk("Unexpected CPU of NEC VR4100 series\n");
	103	return -ENODEV;
	104	}
	105
	106	if (request_mem_region(start, size, "PMU") == NULL)
	107	return -EBUSY;
	108
	109	pmu_base = ioremap(start, size);
	110	if (pmu_base == NULL) {
	111	release_mem_region(start, size);
	112	return -EBUSY;
	113	}
	114
61a33168	115	cpu_wait = vr41xx_cpu_wait;
1da177e4 LT	116	_machine_restart = vr41xx_restart;
1da177e4 LT	117	_machine_halt = vr41xx_halt;
fa417806	118	pm_power_off = vr41xx_halt;
1da177e4 LT	119
	120	return 0;
	121	}
	122
3407c0fe	123	core_initcall(vr41xx_pmu_init);