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e5d8d54d SW |
1 | /* |
2 | * Old U-boot compatibility for PowerQUICC II | |
3 | * (a.k.a. 82xx with CPM, not the 8240 family of chips) | |
4 | * | |
5 | * Author: Scott Wood <scottwood@freescale.com> | |
6 | * | |
7 | * Copyright (c) 2007 Freescale Semiconductor, Inc. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License version 2 as published | |
11 | * by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include "ops.h" | |
15 | #include "stdio.h" | |
16 | #include "cuboot.h" | |
17 | #include "io.h" | |
18 | ||
19 | #define TARGET_CPM2 | |
20 | #define TARGET_HAS_ETH1 | |
21 | #include "ppcboot.h" | |
22 | ||
23 | static bd_t bd; | |
24 | ||
25 | struct cs_range { | |
26 | u32 csnum; | |
27 | u32 base; /* must be zero */ | |
28 | u32 addr; | |
29 | u32 size; | |
30 | }; | |
31 | ||
32 | struct pci_range { | |
33 | u32 flags; | |
34 | u32 pci_addr[2]; | |
35 | u32 phys_addr; | |
36 | u32 size[2]; | |
37 | }; | |
38 | ||
39 | struct cs_range cs_ranges_buf[MAX_PROP_LEN / sizeof(struct cs_range)]; | |
40 | struct pci_range pci_ranges_buf[MAX_PROP_LEN / sizeof(struct pci_range)]; | |
41 | ||
42 | /* Different versions of u-boot put the BCSR in different places, and | |
43 | * some don't set up the PCI PIC at all, so we assume the device tree is | |
44 | * sane and update the BRx registers appropriately. | |
45 | * | |
46 | * For any node defined as compatible with fsl,pq2-chipselect, | |
47 | * #address/#size must be 2/1 for chipselect bus, 1/1 for parent bus, | |
48 | * and ranges must be for whole chip selects. | |
49 | */ | |
50 | static void update_cs_ranges(void) | |
51 | { | |
52 | u32 ctrl_ph; | |
53 | void *ctrl_node, *bus_node, *parent_node; | |
54 | u32 *ctrl_addr; | |
55 | unsigned long ctrl_size; | |
56 | u32 naddr, nsize; | |
57 | int len; | |
58 | int i; | |
59 | ||
60 | bus_node = finddevice("/chipselect"); | |
61 | if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-chipselect")) | |
62 | return; | |
63 | ||
64 | dt_get_reg_format(bus_node, &naddr, &nsize); | |
65 | if (naddr != 2 || nsize != 1) | |
66 | goto err; | |
67 | ||
68 | parent_node = get_parent(bus_node); | |
69 | if (!parent_node) | |
70 | goto err; | |
71 | ||
72 | dt_get_reg_format(parent_node, &naddr, &nsize); | |
73 | if (naddr != 1 || nsize != 1) | |
74 | goto err; | |
75 | ||
76 | len = getprop(bus_node, "fsl,ctrl", &ctrl_ph, 4); | |
77 | if (len != 4) | |
78 | goto err; | |
79 | ||
80 | ctrl_node = find_node_by_prop_value(NULL, "linux,phandle", | |
81 | (char *)&ctrl_ph, 4); | |
82 | if (!ctrl_node) | |
83 | goto err; | |
84 | ||
85 | if (!dt_is_compatible(ctrl_node, "fsl,pq2-chipselect-ctrl")) | |
86 | goto err; | |
87 | ||
88 | if (!dt_xlate_reg(ctrl_node, 0, (unsigned long *)&ctrl_addr, | |
89 | &ctrl_size)) | |
90 | goto err; | |
91 | ||
92 | len = getprop(bus_node, "ranges", cs_ranges_buf, sizeof(cs_ranges_buf)); | |
93 | ||
94 | for (i = 0; i < len / sizeof(struct cs_range); i++) { | |
95 | u32 base, option; | |
96 | int cs = cs_ranges_buf[i].csnum; | |
97 | if (cs >= ctrl_size / 8) | |
98 | goto err; | |
99 | ||
100 | if (cs_ranges_buf[i].base != 0) | |
101 | goto err; | |
102 | ||
103 | base = in_be32(&ctrl_addr[cs * 2]); | |
104 | ||
105 | /* If CS is already valid, use the existing flags. | |
106 | * Otherwise, guess a sane default. | |
107 | */ | |
108 | if (base & 1) { | |
109 | base &= 0x7fff; | |
110 | option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff; | |
111 | } else { | |
112 | base = 0x1801; | |
113 | option = 0x10; | |
114 | } | |
115 | ||
116 | out_be32(&ctrl_addr[cs * 2], 0); | |
117 | out_be32(&ctrl_addr[cs * 2 + 1], | |
118 | option | ~(cs_ranges_buf[i].size - 1)); | |
119 | out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr); | |
120 | } | |
121 | ||
122 | return; | |
123 | ||
124 | err: | |
125 | printf("Bad /chipselect or fsl,pq2-chipselect-ctrl node\r\n"); | |
126 | } | |
127 | ||
128 | /* Older u-boots don't set PCI up properly. Update the hardware to match | |
129 | * the device tree. The prefetch mem region and non-prefetch mem region | |
130 | * must be contiguous in the host bus. As required by the PCI binding, | |
131 | * PCI #addr/#size must be 3/2. The parent bus must be 1/1. Only | |
132 | * 32-bit PCI is supported. All three region types (prefetchable mem, | |
133 | * non-prefetchable mem, and I/O) must be present. | |
134 | */ | |
135 | static void fixup_pci(void) | |
136 | { | |
137 | struct pci_range *mem = NULL, *mmio = NULL, | |
138 | *io = NULL, *mem_base = NULL; | |
139 | u32 *pci_regs[3]; | |
140 | u8 *soc_regs; | |
141 | int i, len; | |
142 | void *ctrl_node, *bus_node, *parent_node, *soc_node; | |
143 | u32 naddr, nsize, bus_ph, mem_log2; | |
144 | ||
145 | ctrl_node = finddevice("/soc/pci"); | |
146 | if (!ctrl_node || !dt_is_compatible(ctrl_node, "fsl,pq2-pci")) | |
147 | return; | |
148 | ||
149 | soc_node = finddevice("/soc"); | |
150 | if (!soc_node || !dt_is_compatible(soc_node, "fsl,pq2-soc")) | |
151 | goto err; | |
152 | ||
153 | for (i = 0; i < 3; i++) | |
154 | if (!dt_xlate_reg(ctrl_node, i, | |
155 | (unsigned long *)&pci_regs[i], NULL)) | |
156 | goto err; | |
157 | ||
158 | if (!dt_xlate_reg(soc_node, 0, (unsigned long *)&soc_regs, NULL)) | |
159 | goto err; | |
160 | ||
161 | len = getprop(ctrl_node, "fsl,bus", &bus_ph, 4); | |
162 | if (len != 4) | |
163 | goto err; | |
164 | ||
165 | bus_node = find_node_by_prop_value(NULL, "linux,phandle", | |
166 | (char *)&bus_ph, 4); | |
167 | if (!bus_node) | |
168 | goto err; | |
169 | ||
170 | dt_get_reg_format(bus_node, &naddr, &nsize); | |
171 | if (naddr != 3 || nsize != 2) | |
172 | goto err; | |
173 | ||
174 | parent_node = get_parent(bus_node); | |
175 | if (!parent_node) | |
176 | goto err; | |
177 | ||
178 | dt_get_reg_format(parent_node, &naddr, &nsize); | |
179 | if (naddr != 1 || nsize != 1) | |
180 | goto err; | |
181 | ||
182 | len = getprop(bus_node, "ranges", pci_ranges_buf, | |
183 | sizeof(pci_ranges_buf)); | |
184 | ||
185 | for (i = 0; i < len / sizeof(struct pci_range); i++) { | |
186 | u32 flags = pci_ranges_buf[i].flags & 0x43000000; | |
187 | ||
188 | if (flags == 0x42000000) | |
189 | mem = &pci_ranges_buf[i]; | |
190 | else if (flags == 0x02000000) | |
191 | mmio = &pci_ranges_buf[i]; | |
192 | else if (flags == 0x01000000) | |
193 | io = &pci_ranges_buf[i]; | |
194 | } | |
195 | ||
196 | if (!mem || !mmio || !io) | |
197 | goto err; | |
198 | ||
199 | if (mem->phys_addr + mem->size[1] == mmio->phys_addr) | |
200 | mem_base = mem; | |
201 | else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr) | |
202 | mem_base = mmio; | |
203 | else | |
204 | goto err; | |
205 | ||
206 | out_be32(&pci_regs[1][0], mem_base->phys_addr | 1); | |
207 | out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1)); | |
208 | ||
209 | out_be32(&pci_regs[1][1], io->phys_addr | 1); | |
210 | out_be32(&pci_regs[2][1], ~(io->size[1] - 1)); | |
211 | ||
212 | out_le32(&pci_regs[0][0], mem->pci_addr[1] >> 12); | |
213 | out_le32(&pci_regs[0][2], mem->phys_addr >> 12); | |
214 | out_le32(&pci_regs[0][4], (~(mem->size[1] - 1) >> 12) | 0xa0000000); | |
215 | ||
216 | out_le32(&pci_regs[0][6], mmio->pci_addr[1] >> 12); | |
217 | out_le32(&pci_regs[0][8], mmio->phys_addr >> 12); | |
218 | out_le32(&pci_regs[0][10], (~(mmio->size[1] - 1) >> 12) | 0x80000000); | |
219 | ||
220 | out_le32(&pci_regs[0][12], io->pci_addr[1] >> 12); | |
221 | out_le32(&pci_regs[0][14], io->phys_addr >> 12); | |
222 | out_le32(&pci_regs[0][16], (~(io->size[1] - 1) >> 12) | 0xc0000000); | |
223 | ||
224 | /* Inbound translation */ | |
225 | out_le32(&pci_regs[0][58], 0); | |
226 | out_le32(&pci_regs[0][60], 0); | |
227 | ||
228 | mem_log2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1); | |
229 | out_le32(&pci_regs[0][62], 0xa0000000 | ~((1 << (mem_log2 - 12)) - 1)); | |
230 | ||
231 | /* If PCI is disabled, drive RST high to enable. */ | |
232 | if (!(in_le32(&pci_regs[0][32]) & 1)) { | |
233 | /* Tpvrh (Power valid to RST# high) 100 ms */ | |
234 | udelay(100000); | |
235 | ||
236 | out_le32(&pci_regs[0][32], 1); | |
237 | ||
238 | /* Trhfa (RST# high to first cfg access) 2^25 clocks */ | |
239 | udelay(1020000); | |
240 | } | |
241 | ||
242 | /* Enable bus master and memory access */ | |
243 | out_le32(&pci_regs[0][64], 0x80000004); | |
244 | out_le32(&pci_regs[0][65], in_le32(&pci_regs[0][65]) | 6); | |
245 | ||
246 | /* Park the bus on PCI, and elevate PCI's arbitration priority, | |
247 | * as required by section 9.6 of the user's manual. | |
248 | */ | |
249 | out_8(&soc_regs[0x10028], 3); | |
250 | out_be32((u32 *)&soc_regs[0x1002c], 0x01236745); | |
251 | ||
252 | return; | |
253 | ||
254 | err: | |
255 | printf("Bad PCI node\r\n"); | |
256 | } | |
257 | ||
258 | static void pq2_platform_fixups(void) | |
259 | { | |
260 | void *node; | |
261 | ||
262 | dt_fixup_memory(bd.bi_memstart, bd.bi_memsize); | |
263 | dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr); | |
264 | dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq); | |
265 | ||
266 | node = finddevice("/soc/cpm"); | |
6d817aa7 | 267 | if (node) |
e5d8d54d | 268 | setprop(node, "clock-frequency", &bd.bi_cpmfreq, 4); |
6d817aa7 SW |
269 | |
270 | node = finddevice("/soc/cpm/brg"); | |
271 | if (node) | |
272 | setprop(node, "clock-frequency", &bd.bi_brgfreq, 4); | |
e5d8d54d SW |
273 | |
274 | update_cs_ranges(); | |
275 | fixup_pci(); | |
276 | } | |
277 | ||
278 | void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, | |
279 | unsigned long r6, unsigned long r7) | |
280 | { | |
281 | CUBOOT_INIT(); | |
282 | ft_init(_dtb_start, _dtb_end - _dtb_start, 32); | |
283 | serial_console_init(); | |
284 | platform_ops.fixups = pq2_platform_fixups; | |
285 | } |